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G, Manjunath Kondaiah59de3cf2010-12-20 18:27:19 -08001/*
2 * OMAP2+ DMA driver
3 *
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
11 *
12 * Copyright (C) 2009 Texas Instruments
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
16 * Converted DMA library into platform driver
17 * - G, Manjunath Kondaiah <manjugk@ti.com>
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 */
23
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/slab.h>
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/device.h>
Tony Lindgrenbe1f9482013-01-11 11:24:19 -080030#include <linux/dma-mapping.h>
Jon Hunter8d306622013-02-26 12:27:24 -060031#include <linux/of.h>
Tony Lindgren45c3eb72012-11-30 08:41:50 -080032#include <linux/omap-dma.h>
G, Manjunath Kondaiah59de3cf2010-12-20 18:27:19 -080033
Tony Lindgrene4c060d2012-10-05 13:25:59 -070034#include "soc.h"
Tony Lindgren2a296c82012-10-02 17:41:35 -070035#include "omap_hwmod.h"
Tony Lindgren25c7d492012-10-02 17:25:48 -070036#include "omap_device.h"
37
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -080038static struct omap_dma_dev_attr *d;
39
Russell Kingad0c3812013-11-08 14:53:35 +000040static enum omap_reg_offsets dma_common_ch_end;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -080041
Russell King64a2dc32013-11-08 18:04:06 +000042static const struct omap_dma_reg reg_map[] = {
43 [REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
44 [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
45 [IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
46 [IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
47 [IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
48 [IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
49 [IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
50 [IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
51 [IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
52 [IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
53 [SYSSTATUS] = { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
54 [OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
55 [CAPS_0] = { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
56 [CAPS_2] = { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
57 [CAPS_3] = { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
58 [CAPS_4] = { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -080059
60 /* Common register offsets */
Russell King64a2dc32013-11-08 18:04:06 +000061 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
62 [CLNK_CTRL] = { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
63 [CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
64 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
65 [CSDP] = { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
66 [CEN] = { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
67 [CFN] = { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
68 [CSEI] = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
69 [CSFI] = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
70 [CDEI] = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
71 [CDFI] = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
72 [CSAC] = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
73 [CDAC] = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -080074
75 /* Channel specific register offsets */
Russell King64a2dc32013-11-08 18:04:06 +000076 [CSSA] = { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
77 [CDSA] = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
78 [CCEN] = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
79 [CCFN] = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
80 [COLOR] = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -080081
82 /* OMAP4 specific registers */
Russell King64a2dc32013-11-08 18:04:06 +000083 [CDP] = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
84 [CNDP] = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
85 [CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -080086};
87
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -080088static void __iomem *dma_base;
89static inline void dma_write(u32 val, int reg, int lch)
90{
Russell King64a2dc32013-11-08 18:04:06 +000091 void __iomem *addr = dma_base;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -080092
Russell King64a2dc32013-11-08 18:04:06 +000093 addr += reg_map[reg].offset;
94 addr += reg_map[reg].stride * lch;
95
96 __raw_writel(val, addr);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -080097}
98
99static inline u32 dma_read(int reg, int lch)
100{
Russell King64a2dc32013-11-08 18:04:06 +0000101 void __iomem *addr = dma_base;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800102
Russell King64a2dc32013-11-08 18:04:06 +0000103 addr += reg_map[reg].offset;
104 addr += reg_map[reg].stride * lch;
105
106 return __raw_readl(addr);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800107}
108
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800109static void omap2_clear_dma(int lch)
110{
Russell Kingad0c3812013-11-08 14:53:35 +0000111 int i;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800112
Russell Kingad0c3812013-11-08 14:53:35 +0000113 for (i = CSDP; i <= dma_common_ch_end; i += 1)
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800114 dma_write(0, i, lch);
115}
116
117static void omap2_show_dma_caps(void)
118{
119 u8 revision = dma_read(REVISION, 0) & 0xff;
120 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
121 revision >> 4, revision & 0xf);
122 return;
123}
124
Russell King0ef64982013-11-08 18:06:37 +0000125static unsigned configure_dma_errata(void)
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800126{
Russell King0ef64982013-11-08 18:06:37 +0000127 unsigned errata = 0;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800128
129 /*
130 * Errata applicable for OMAP2430ES1.0 and all omap2420
131 *
132 * I.
133 * Erratum ID: Not Available
134 * Inter Frame DMA buffering issue DMA will wrongly
135 * buffer elements if packing and bursting is enabled. This might
136 * result in data gets stalled in FIFO at the end of the block.
137 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
138 * guarantee no data will stay in the DMA FIFO in case inter frame
139 * buffering occurs
140 *
141 * II.
142 * Erratum ID: Not Available
143 * DMA may hang when several channels are used in parallel
144 * In the following configuration, DMA channel hanging can occur:
145 * a. Channel i, hardware synchronized, is enabled
146 * b. Another channel (Channel x), software synchronized, is enabled.
147 * c. Channel i is disabled before end of transfer
148 * d. Channel i is reenabled.
149 * e. Steps 1 to 4 are repeated a certain number of times.
150 * f. A third channel (Channel y), software synchronized, is enabled.
151 * Channel x and Channel y may hang immediately after step 'f'.
152 * Workaround:
153 * For any channel used - make sure NextLCH_ID is set to the value j.
154 */
155 if (cpu_is_omap2420() || (cpu_is_omap2430() &&
156 (omap_type() == OMAP2430_REV_ES1_0))) {
157
158 SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
159 SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
160 }
161
162 /*
163 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
164 * after a transaction error.
165 * Workaround: SW should explicitely disable the channel.
166 */
167 if (cpu_class_is_omap2())
168 SET_DMA_ERRATA(DMA_ERRATA_i378);
169
170 /*
171 * Erratum ID: i541: sDMA FIFO draining does not finish
172 * If sDMA channel is disabled on the fly, sDMA enters standby even
173 * through FIFO Drain is still in progress
174 * Workaround: Put sDMA in NoStandby more before a logical channel is
175 * disabled, then put it back to SmartStandby right after the channel
176 * finishes FIFO draining.
177 */
178 if (cpu_is_omap34xx())
179 SET_DMA_ERRATA(DMA_ERRATA_i541);
180
181 /*
182 * Erratum ID: i88 : Special programming model needed to disable DMA
183 * before end of block.
184 * Workaround: software must ensure that the DMA is configured in No
185 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
186 */
187 if (omap_type() == OMAP3430_REV_ES1_0)
188 SET_DMA_ERRATA(DMA_ERRATA_i88);
189
190 /*
191 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
192 * read before the DMA controller finished disabling the channel.
193 */
194 SET_DMA_ERRATA(DMA_ERRATA_3_3);
195
196 /*
197 * Erratum ID: Not Available
198 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
199 * after secure sram context save and restore.
200 * Work around: Hence we need to manually clear those IRQs to avoid
201 * spurious interrupts. This affects only secure devices.
202 */
203 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
204 SET_DMA_ERRATA(DMA_ROMCODE_BUG);
205
206 return errata;
207}
208
G, Manjunath Kondaiah59de3cf2010-12-20 18:27:19 -0800209/* One time initializations */
210static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
211{
Kevin Hilman3528c582011-07-21 13:48:45 -0700212 struct platform_device *pdev;
G, Manjunath Kondaiah59de3cf2010-12-20 18:27:19 -0800213 struct omap_system_dma_plat_info *p;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800214 struct resource *mem;
G, Manjunath Kondaiah59de3cf2010-12-20 18:27:19 -0800215 char *name = "omap_dma_system";
216
217 p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
218 if (!p) {
219 pr_err("%s: Unable to allocate pdata for %s:%s\n",
220 __func__, name, oh->name);
221 return -ENOMEM;
222 }
223
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800224 p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800225 p->show_dma_caps = omap2_show_dma_caps;
226 p->clear_dma = omap2_clear_dma;
227 p->dma_write = dma_write;
228 p->dma_read = dma_read;
229
230 p->clear_lch_regs = NULL;
231
232 p->errata = configure_dma_errata();
233
Paul Walmsleyc1d1cd52013-01-26 00:48:53 -0700234 pdev = omap_device_build(name, 0, oh, p, sizeof(*p));
G, Manjunath Kondaiah59de3cf2010-12-20 18:27:19 -0800235 kfree(p);
Kevin Hilman3528c582011-07-21 13:48:45 -0700236 if (IS_ERR(pdev)) {
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300237 pr_err("%s: Can't build omap_device for %s:%s.\n",
G, Manjunath Kondaiah59de3cf2010-12-20 18:27:19 -0800238 __func__, name, oh->name);
Kevin Hilman3528c582011-07-21 13:48:45 -0700239 return PTR_ERR(pdev);
G, Manjunath Kondaiah59de3cf2010-12-20 18:27:19 -0800240 }
241
Kevin Hilman3528c582011-07-21 13:48:45 -0700242 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800243 if (!mem) {
Kevin Hilman3528c582011-07-21 13:48:45 -0700244 dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800245 return -EINVAL;
246 }
247 dma_base = ioremap(mem->start, resource_size(mem));
248 if (!dma_base) {
Kevin Hilman3528c582011-07-21 13:48:45 -0700249 dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800250 return -ENOMEM;
251 }
252
253 d = oh->dev_attr;
254 d->chan = kzalloc(sizeof(struct omap_dma_lch) *
255 (d->lch_count), GFP_KERNEL);
256
257 if (!d->chan) {
Kevin Hilman3528c582011-07-21 13:48:45 -0700258 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800259 return -ENOMEM;
260 }
R Sricharanf6d5e072012-05-07 14:02:25 +0530261
Tony Lindgren82809602012-10-30 11:03:22 -0700262 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
263 d->dev_caps |= HS_CHANNELS_RESERVED;
264
R Sricharanf6d5e072012-05-07 14:02:25 +0530265 /* Check the capabilities register for descriptor loading feature */
266 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
267 dma_common_ch_end = CCDN;
268 else
269 dma_common_ch_end = CCFN;
270
G, Manjunath Kondaiah59de3cf2010-12-20 18:27:19 -0800271 return 0;
272}
273
Tony Lindgrenbe1f9482013-01-11 11:24:19 -0800274static const struct platform_device_info omap_dma_dev_info = {
275 .name = "omap-dma-engine",
276 .id = -1,
277 .dma_mask = DMA_BIT_MASK(32),
278};
279
G, Manjunath Kondaiah59de3cf2010-12-20 18:27:19 -0800280static int __init omap2_system_dma_init(void)
281{
Tony Lindgrenbe1f9482013-01-11 11:24:19 -0800282 struct platform_device *pdev;
283 int res;
284
285 res = omap_hwmod_for_each_by_class("dma",
G, Manjunath Kondaiah59de3cf2010-12-20 18:27:19 -0800286 omap2_system_dma_init_dev, NULL);
Tony Lindgrenbe1f9482013-01-11 11:24:19 -0800287 if (res)
288 return res;
289
Jon Hunter8d306622013-02-26 12:27:24 -0600290 if (of_have_populated_dt())
291 return res;
292
Tony Lindgrenbe1f9482013-01-11 11:24:19 -0800293 pdev = platform_device_register_full(&omap_dma_dev_info);
294 if (IS_ERR(pdev))
295 return PTR_ERR(pdev);
296
297 return res;
G, Manjunath Kondaiah59de3cf2010-12-20 18:27:19 -0800298}
Tony Lindgrenb76c8b192013-01-11 11:24:18 -0800299omap_arch_initcall(omap2_system_dma_init);