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gerrit-public.fairphone.software / kernel / msm-5.4 / 17b1639b30e080dc577cbffe7a08d063708ec789 / . / include / linux / platform_data / spi-s3c64xx.h
blob: ceba18d23a5a530ef233f5f5ecfe0e987cb87274 [file] [log] [blame]
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]1/* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S3C64XX_PLAT_SPI_H
12#define __S3C64XX_PLAT_SPI_H
13
Mark Brown5b0b34e2011-12-29 18:01:08 +0900[diff] [blame]14struct platform_device;
15
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]16/**
17 * struct s3c64xx_spi_csinfo - ChipSelect description
18 * @fb_delay: Slave specific feedback delay.
19 * Refer to FB_CLK_SEL register definition in SPI chapter.
20 * @line: Custom 'identity' of the CS line.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]21 *
22 * This is per SPI-Slave Chipselect information.
23 * Allocate and initialize one in machine init code and make the
24 * spi_board_info.controller_data point to it.
25 */
26struct s3c64xx_spi_csinfo {
27 u8 fb_delay;
28 unsigned line;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]29};
30
31/**
32 * struct s3c64xx_spi_info - SPI Controller defining structure
33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]34 * @num_cs: Number of CS this controller emulates.
35 * @cfg_gpio: Configure pins for this SPI controller.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]36 */
37struct s3c64xx_spi_info {
38 int src_clk_nr;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]39 int num_cs;
Thomas Abraham868dee92012-07-13 07:15:14 +0900[diff] [blame]40 int (*cfg_gpio)(void);
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]41};
42
43/**
Padmavathi Venna875a5932011-12-23 10:14:31 +0900[diff] [blame]44 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]45 * initialization code.
Thomas Abraham4d0efdd2012-07-13 07:15:14 +0900[diff] [blame]46 * @cfg_gpio: Pointer to gpio setup function.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]47 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
48 * @num_cs: Number of elements in the 'cs' array.
49 *
50 * Call this from machine init code for each SPI Controller that
51 * has some chips attached to it.
52 */
Thomas Abraham4d0efdd2012-07-13 07:15:14 +0900[diff] [blame]53extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
54 int num_cs);
55extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
56 int num_cs);
57extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
58 int num_cs);
Padmavathi Venna4566c7f2011-12-23 10:14:36 +0900[diff] [blame]59
60/* defined by architecture to configure gpio */
Thomas Abraham868dee92012-07-13 07:15:14 +0900[diff] [blame]61extern int s3c64xx_spi0_cfg_gpio(void);
62extern int s3c64xx_spi1_cfg_gpio(void);
63extern int s3c64xx_spi2_cfg_gpio(void);
Padmavathi Venna4566c7f2011-12-23 10:14:36 +0900[diff] [blame]64
65extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
66extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
Padmavathi Venna323d7712011-12-23 10:14:45 +0900[diff] [blame]67extern struct s3c64xx_spi_info s3c64xx_spi2_pdata;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]68#endif /* __S3C64XX_PLAT_SPI_H */