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gerrit-public.fairphone.software / kernel / msm-5.4 / 17febfa6071bc673892edda6b1998ccfc7456c4e / . / sound / soc / codecs / rt5665.c
blob: 285ec74953796e2fb7da3923258764797b2d6f10 [file] [log] [blame]
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1/*
2 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
3 *
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <linux/acpi.h>
21#include <linux/gpio.h>
22#include <linux/of_gpio.h>
23#include <linux/regulator/consumer.h>
24#include <linux/mutex.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/jack.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <sound/rt5665.h>
34
35#include "rl6231.h"
36#include "rt5665.h"
37
38#define RT5665_NUM_SUPPLIES 3
39
40static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
41 "AVDD",
42 "MICVDD",
43 "VBAT",
44};
45
46struct rt5665_priv {
47 struct snd_soc_codec *codec;
48 struct rt5665_platform_data pdata;
49 struct regmap *regmap;
50 struct gpio_desc *gpiod_ldo1_en;
51 struct gpio_desc *gpiod_reset;
52 struct snd_soc_jack *hs_jack;
53 struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
54 struct delayed_work jack_detect_work;
55 struct delayed_work calibrate_work;
56 struct delayed_work jd_check_work;
57 struct mutex calibrate_mutex;
58
59 int sysclk;
60 int sysclk_src;
61 int lrck[RT5665_AIFS];
62 int bclk[RT5665_AIFS];
63 int master[RT5665_AIFS];
64 int id;
65
66 int pll_src;
67 int pll_in;
68 int pll_out;
69
70 int jack_type;
71 int irq_work_delay_time;
72 unsigned int sar_adc_value;
73};
74
75static const struct reg_default rt5665_reg[] = {
76 {0x0000, 0x0000},
77 {0x0001, 0xc8c8},
78 {0x0002, 0x8080},
79 {0x0003, 0x8000},
80 {0x0004, 0xc80a},
81 {0x0005, 0x0000},
82 {0x0006, 0x0000},
83 {0x0007, 0x0000},
84 {0x000a, 0x0000},
85 {0x000b, 0x0000},
86 {0x000c, 0x0000},
87 {0x000d, 0x0000},
88 {0x000f, 0x0808},
89 {0x0010, 0x4040},
90 {0x0011, 0x0000},
91 {0x0012, 0x1404},
92 {0x0013, 0x1000},
93 {0x0014, 0xa00a},
94 {0x0015, 0x0404},
95 {0x0016, 0x0404},
96 {0x0017, 0x0011},
97 {0x0018, 0xafaf},
98 {0x0019, 0xafaf},
99 {0x001a, 0xafaf},
100 {0x001b, 0x0011},
101 {0x001c, 0x2f2f},
102 {0x001d, 0x2f2f},
103 {0x001e, 0x2f2f},
104 {0x001f, 0x0000},
105 {0x0020, 0x0000},
106 {0x0021, 0x0000},
107 {0x0022, 0x5757},
108 {0x0023, 0x0039},
109 {0x0026, 0xc0c0},
110 {0x0027, 0xc0c0},
111 {0x0028, 0xc0c0},
112 {0x0029, 0x8080},
113 {0x002a, 0xaaaa},
114 {0x002b, 0xaaaa},
115 {0x002c, 0xaba8},
116 {0x002d, 0x0000},
117 {0x002e, 0x0000},
118 {0x002f, 0x0000},
119 {0x0030, 0x0000},
120 {0x0031, 0x5000},
121 {0x0032, 0x0000},
122 {0x0033, 0x0000},
123 {0x0034, 0x0000},
124 {0x0035, 0x0000},
125 {0x003a, 0x0000},
126 {0x003b, 0x0000},
127 {0x003c, 0x00ff},
128 {0x003d, 0x0000},
129 {0x003e, 0x00ff},
130 {0x003f, 0x0000},
131 {0x0040, 0x0000},
132 {0x0041, 0x00ff},
133 {0x0042, 0x0000},
134 {0x0043, 0x00ff},
135 {0x0044, 0x0c0c},
136 {0x0049, 0xc00b},
137 {0x004a, 0x0000},
138 {0x004b, 0x031f},
139 {0x004d, 0x0000},
140 {0x004e, 0x001f},
141 {0x004f, 0x0000},
142 {0x0050, 0x001f},
143 {0x0052, 0xf000},
144 {0x0061, 0x0000},
145 {0x0062, 0x0000},
146 {0x0063, 0x003e},
147 {0x0064, 0x0000},
148 {0x0065, 0x0000},
149 {0x0066, 0x003f},
150 {0x0067, 0x0000},
151 {0x006b, 0x0000},
152 {0x006d, 0xff00},
153 {0x006e, 0x2808},
154 {0x006f, 0x000a},
155 {0x0070, 0x8000},
156 {0x0071, 0x8000},
157 {0x0072, 0x8000},
158 {0x0073, 0x7000},
159 {0x0074, 0x7770},
160 {0x0075, 0x0002},
161 {0x0076, 0x0001},
162 {0x0078, 0x00f0},
163 {0x0079, 0x0000},
164 {0x007a, 0x0000},
165 {0x007b, 0x0000},
166 {0x007c, 0x0000},
167 {0x007d, 0x0123},
168 {0x007e, 0x4500},
169 {0x007f, 0x8003},
170 {0x0080, 0x0000},
171 {0x0081, 0x0000},
172 {0x0082, 0x0000},
173 {0x0083, 0x0000},
174 {0x0084, 0x0000},
175 {0x0085, 0x0000},
176 {0x0086, 0x0008},
177 {0x0087, 0x0000},
178 {0x0088, 0x0000},
179 {0x0089, 0x0000},
180 {0x008a, 0x0000},
181 {0x008b, 0x0000},
182 {0x008c, 0x0003},
183 {0x008e, 0x0060},
184 {0x008f, 0x1000},
185 {0x0091, 0x0c26},
186 {0x0092, 0x0073},
187 {0x0093, 0x0000},
188 {0x0094, 0x0080},
189 {0x0098, 0x0000},
190 {0x0099, 0x0000},
191 {0x009a, 0x0007},
192 {0x009f, 0x0000},
193 {0x00a0, 0x0000},
194 {0x00a1, 0x0002},
195 {0x00a2, 0x0001},
196 {0x00a3, 0x0002},
197 {0x00a4, 0x0001},
198 {0x00ae, 0x2040},
199 {0x00af, 0x0000},
200 {0x00b6, 0x0000},
201 {0x00b7, 0x0000},
202 {0x00b8, 0x0000},
203 {0x00b9, 0x0000},
204 {0x00ba, 0x0002},
205 {0x00bb, 0x0000},
206 {0x00be, 0x0000},
207 {0x00c0, 0x0000},
208 {0x00c1, 0x0aaa},
209 {0x00c2, 0xaa80},
210 {0x00c3, 0x0003},
211 {0x00c4, 0x0000},
212 {0x00d0, 0x0000},
213 {0x00d1, 0x2244},
214 {0x00d3, 0x3300},
215 {0x00d4, 0x2200},
216 {0x00d9, 0x0809},
217 {0x00da, 0x0000},
218 {0x00db, 0x0008},
219 {0x00dc, 0x00c0},
220 {0x00dd, 0x6724},
221 {0x00de, 0x3131},
222 {0x00df, 0x0008},
223 {0x00e0, 0x4000},
224 {0x00e1, 0x3131},
225 {0x00e2, 0x600c},
226 {0x00ea, 0xb320},
227 {0x00eb, 0x0000},
228 {0x00ec, 0xb300},
229 {0x00ed, 0x0000},
230 {0x00ee, 0xb320},
231 {0x00ef, 0x0000},
232 {0x00f0, 0x0201},
233 {0x00f1, 0x0ddd},
234 {0x00f2, 0x0ddd},
235 {0x00f6, 0x0000},
236 {0x00f7, 0x0000},
237 {0x00f8, 0x0000},
238 {0x00fa, 0x0000},
239 {0x00fb, 0x0000},
240 {0x00fc, 0x0000},
241 {0x00fd, 0x0000},
242 {0x00fe, 0x10ec},
243 {0x00ff, 0x6451},
244 {0x0100, 0xaaaa},
245 {0x0101, 0x000a},
246 {0x010a, 0xaaaa},
247 {0x010b, 0xa0a0},
248 {0x010c, 0xaeae},
249 {0x010d, 0xaaaa},
250 {0x010e, 0xaaaa},
251 {0x010f, 0xaaaa},
252 {0x0110, 0xe002},
253 {0x0111, 0xa402},
254 {0x0112, 0xaaaa},
255 {0x0113, 0x2000},
256 {0x0117, 0x0f00},
257 {0x0125, 0x0410},
258 {0x0132, 0x0000},
259 {0x0133, 0x0000},
260 {0x0137, 0x5540},
261 {0x0138, 0x3700},
262 {0x0139, 0x79a1},
263 {0x013a, 0x2020},
264 {0x013b, 0x2020},
265 {0x013c, 0x2005},
266 {0x013f, 0x0000},
267 {0x0145, 0x0002},
268 {0x0146, 0x0000},
269 {0x0147, 0x0000},
270 {0x0148, 0x0000},
271 {0x0150, 0x0000},
272 {0x0160, 0x4eff},
273 {0x0161, 0x0080},
274 {0x0162, 0x0200},
275 {0x0163, 0x0800},
276 {0x0164, 0x0000},
277 {0x0165, 0x0000},
278 {0x0166, 0x0000},
279 {0x0167, 0x000f},
280 {0x0170, 0x4e87},
281 {0x0171, 0x0080},
282 {0x0172, 0x0200},
283 {0x0173, 0x0800},
284 {0x0174, 0x00ff},
285 {0x0175, 0x0000},
286 {0x0190, 0x413d},
287 {0x0191, 0x4139},
288 {0x0192, 0x4135},
289 {0x0193, 0x413d},
290 {0x0194, 0x0000},
291 {0x0195, 0x0000},
292 {0x0196, 0x0000},
293 {0x0197, 0x0000},
294 {0x0198, 0x0000},
295 {0x0199, 0x0000},
296 {0x01a0, 0x1e64},
297 {0x01a1, 0x06a3},
298 {0x01a2, 0x0000},
299 {0x01a3, 0x0000},
300 {0x01a4, 0x0000},
301 {0x01a5, 0x0000},
302 {0x01a6, 0x0000},
303 {0x01a7, 0x8000},
304 {0x01a8, 0x0000},
305 {0x01a9, 0x0000},
306 {0x01aa, 0x0000},
307 {0x01ab, 0x0000},
308 {0x01b5, 0x0000},
309 {0x01b6, 0x01c3},
310 {0x01b7, 0x02a0},
311 {0x01b8, 0x03e9},
312 {0x01b9, 0x1389},
313 {0x01ba, 0xc351},
314 {0x01bb, 0x0009},
315 {0x01bc, 0x0018},
316 {0x01bd, 0x002a},
317 {0x01be, 0x004c},
318 {0x01bf, 0x0097},
319 {0x01c0, 0x433d},
320 {0x01c1, 0x0000},
321 {0x01c2, 0x0000},
322 {0x01c3, 0x0000},
323 {0x01c4, 0x0000},
324 {0x01c5, 0x0000},
325 {0x01c6, 0x0000},
326 {0x01c7, 0x0000},
327 {0x01c8, 0x40af},
328 {0x01c9, 0x0702},
329 {0x01ca, 0x0000},
330 {0x01cb, 0x0000},
331 {0x01cc, 0x5757},
332 {0x01cd, 0x5757},
333 {0x01ce, 0x5757},
334 {0x01cf, 0x5757},
335 {0x01d0, 0x5757},
336 {0x01d1, 0x5757},
337 {0x01d2, 0x5757},
338 {0x01d3, 0x5757},
339 {0x01d4, 0x5757},
340 {0x01d5, 0x5757},
341 {0x01d6, 0x003c},
342 {0x01da, 0x0000},
343 {0x01db, 0x0000},
344 {0x01dc, 0x0000},
345 {0x01de, 0x7c00},
346 {0x01df, 0x0320},
347 {0x01e0, 0x06a1},
348 {0x01e1, 0x0000},
349 {0x01e2, 0x0000},
350 {0x01e3, 0x0000},
351 {0x01e4, 0x0000},
352 {0x01e6, 0x0001},
353 {0x01e7, 0x0000},
354 {0x01e8, 0x0000},
355 {0x01ea, 0xbf3f},
356 {0x01eb, 0x0000},
357 {0x01ec, 0x0000},
358 {0x01ed, 0x0000},
359 {0x01ee, 0x0000},
360 {0x01ef, 0x0000},
361 {0x01f0, 0x0000},
362 {0x01f1, 0x0000},
363 {0x01f2, 0x0000},
364 {0x01f3, 0x0000},
365 {0x01f4, 0x0000},
366 {0x0200, 0x0000},
367 {0x0201, 0x0000},
368 {0x0202, 0x0000},
369 {0x0203, 0x0000},
370 {0x0204, 0x0000},
371 {0x0205, 0x0000},
372 {0x0206, 0x0000},
373 {0x0207, 0x0000},
374 {0x0208, 0x0000},
375 {0x0210, 0x60b1},
376 {0x0211, 0xa005},
377 {0x0212, 0x024c},
378 {0x0213, 0xf7ff},
379 {0x0214, 0x024c},
380 {0x0215, 0x0102},
381 {0x0216, 0x00a3},
382 {0x0217, 0x0048},
383 {0x0218, 0xa2c0},
384 {0x0219, 0x0400},
385 {0x021a, 0x00c8},
386 {0x021b, 0x00c0},
387 {0x02ff, 0x0110},
388 {0x0300, 0x001f},
389 {0x0301, 0x032c},
390 {0x0302, 0x5f21},
391 {0x0303, 0x4000},
392 {0x0304, 0x4000},
393 {0x0305, 0x06d5},
394 {0x0306, 0x8000},
395 {0x0307, 0x0700},
396 {0x0310, 0x4560},
397 {0x0311, 0xa4a8},
398 {0x0312, 0x7418},
399 {0x0313, 0x0000},
400 {0x0314, 0x0006},
401 {0x0315, 0xffff},
402 {0x0316, 0xc400},
403 {0x0317, 0x0000},
404 {0x0330, 0x00a6},
405 {0x0331, 0x04c3},
406 {0x0332, 0x27c8},
407 {0x0333, 0xbf50},
408 {0x0334, 0x0045},
409 {0x0335, 0x0007},
410 {0x0336, 0x7418},
411 {0x0337, 0x0501},
412 {0x0338, 0x0000},
413 {0x0339, 0x0010},
414 {0x033a, 0x1010},
415 {0x03c0, 0x7e00},
416 {0x03c1, 0x8000},
417 {0x03c2, 0x8000},
418 {0x03c3, 0x8000},
419 {0x03c4, 0x8000},
420 {0x03c5, 0x8000},
421 {0x03c6, 0x8000},
422 {0x03c7, 0x8000},
423 {0x03c8, 0x8000},
424 {0x03c9, 0x8000},
425 {0x03ca, 0x8000},
426 {0x03cb, 0x8000},
427 {0x03cc, 0x8000},
428 {0x03d0, 0x0000},
429 {0x03d1, 0x0000},
430 {0x03d2, 0x0000},
431 {0x03d3, 0x0000},
432 {0x03d4, 0x2000},
433 {0x03d5, 0x2000},
434 {0x03d6, 0x0000},
435 {0x03d7, 0x0000},
436 {0x03d8, 0x2000},
437 {0x03d9, 0x2000},
438 {0x03da, 0x2000},
439 {0x03db, 0x2000},
440 {0x03dc, 0x0000},
441 {0x03dd, 0x0000},
442 {0x03de, 0x0000},
443 {0x03df, 0x2000},
444 {0x03e0, 0x0000},
445 {0x03e1, 0x0000},
446 {0x03e2, 0x0000},
447 {0x03e3, 0x0000},
448 {0x03e4, 0x0000},
449 {0x03e5, 0x0000},
450 {0x03e6, 0x0000},
451 {0x03e7, 0x0000},
452 {0x03e8, 0x0000},
453 {0x03e9, 0x0000},
454 {0x03ea, 0x0000},
455 {0x03eb, 0x0000},
456 {0x03ec, 0x0000},
457 {0x03ed, 0x0000},
458 {0x03ee, 0x0000},
459 {0x03ef, 0x0000},
460 {0x03f0, 0x0800},
461 {0x03f1, 0x0800},
462 {0x03f2, 0x0800},
463 {0x03f3, 0x0800},
464};
465
466static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
467{
468 switch (reg) {
469 case RT5665_RESET:
470 case RT5665_EJD_CTRL_2:
471 case RT5665_GPIO_STA:
472 case RT5665_INT_ST_1:
473 case RT5665_IL_CMD_1:
474 case RT5665_4BTN_IL_CMD_1:
475 case RT5665_PSV_IL_CMD_1:
476 case RT5665_AJD1_CTRL:
477 case RT5665_JD_CTRL_3:
478 case RT5665_STO_NG2_CTRL_1:
479 case RT5665_SAR_IL_CMD_4:
480 case RT5665_DEVICE_ID:
481 case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
482 case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
483 case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
484 case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
485 return true;
486 default:
487 return false;
488 }
489}
490
491static bool rt5665_readable_register(struct device *dev, unsigned int reg)
492{
493 switch (reg) {
494 case RT5665_RESET:
495 case RT5665_VENDOR_ID:
496 case RT5665_VENDOR_ID_1:
497 case RT5665_DEVICE_ID:
498 case RT5665_LOUT:
499 case RT5665_HP_CTRL_1:
500 case RT5665_HP_CTRL_2:
501 case RT5665_MONO_OUT:
502 case RT5665_HPL_GAIN:
503 case RT5665_HPR_GAIN:
504 case RT5665_MONO_GAIN:
505 case RT5665_CAL_BST_CTRL:
506 case RT5665_CBJ_BST_CTRL:
507 case RT5665_IN1_IN2:
508 case RT5665_IN3_IN4:
509 case RT5665_INL1_INR1_VOL:
510 case RT5665_EJD_CTRL_1:
511 case RT5665_EJD_CTRL_2:
512 case RT5665_EJD_CTRL_3:
513 case RT5665_EJD_CTRL_4:
514 case RT5665_EJD_CTRL_5:
515 case RT5665_EJD_CTRL_6:
516 case RT5665_EJD_CTRL_7:
517 case RT5665_DAC2_CTRL:
518 case RT5665_DAC2_DIG_VOL:
519 case RT5665_DAC1_DIG_VOL:
520 case RT5665_DAC3_DIG_VOL:
521 case RT5665_DAC3_CTRL:
522 case RT5665_STO1_ADC_DIG_VOL:
523 case RT5665_MONO_ADC_DIG_VOL:
524 case RT5665_STO2_ADC_DIG_VOL:
525 case RT5665_STO1_ADC_BOOST:
526 case RT5665_MONO_ADC_BOOST:
527 case RT5665_STO2_ADC_BOOST:
528 case RT5665_HP_IMP_GAIN_1:
529 case RT5665_HP_IMP_GAIN_2:
530 case RT5665_STO1_ADC_MIXER:
531 case RT5665_MONO_ADC_MIXER:
532 case RT5665_STO2_ADC_MIXER:
533 case RT5665_AD_DA_MIXER:
534 case RT5665_STO1_DAC_MIXER:
535 case RT5665_MONO_DAC_MIXER:
536 case RT5665_STO2_DAC_MIXER:
537 case RT5665_A_DAC1_MUX:
538 case RT5665_A_DAC2_MUX:
539 case RT5665_DIG_INF2_DATA:
540 case RT5665_DIG_INF3_DATA:
541 case RT5665_PDM_OUT_CTRL:
542 case RT5665_PDM_DATA_CTRL_1:
543 case RT5665_PDM_DATA_CTRL_2:
544 case RT5665_PDM_DATA_CTRL_3:
545 case RT5665_PDM_DATA_CTRL_4:
546 case RT5665_REC1_GAIN:
547 case RT5665_REC1_L1_MIXER:
548 case RT5665_REC1_L2_MIXER:
549 case RT5665_REC1_R1_MIXER:
550 case RT5665_REC1_R2_MIXER:
551 case RT5665_REC2_GAIN:
552 case RT5665_REC2_L1_MIXER:
553 case RT5665_REC2_L2_MIXER:
554 case RT5665_REC2_R1_MIXER:
555 case RT5665_REC2_R2_MIXER:
556 case RT5665_CAL_REC:
557 case RT5665_ALC_BACK_GAIN:
558 case RT5665_MONOMIX_GAIN:
559 case RT5665_MONOMIX_IN_GAIN:
560 case RT5665_OUT_L_GAIN:
561 case RT5665_OUT_L_MIXER:
562 case RT5665_OUT_R_GAIN:
563 case RT5665_OUT_R_MIXER:
564 case RT5665_LOUT_MIXER:
565 case RT5665_PWR_DIG_1:
566 case RT5665_PWR_DIG_2:
567 case RT5665_PWR_ANLG_1:
568 case RT5665_PWR_ANLG_2:
569 case RT5665_PWR_ANLG_3:
570 case RT5665_PWR_MIXER:
571 case RT5665_PWR_VOL:
572 case RT5665_CLK_DET:
573 case RT5665_HPF_CTRL1:
574 case RT5665_DMIC_CTRL_1:
575 case RT5665_DMIC_CTRL_2:
576 case RT5665_I2S1_SDP:
577 case RT5665_I2S2_SDP:
578 case RT5665_I2S3_SDP:
579 case RT5665_ADDA_CLK_1:
580 case RT5665_ADDA_CLK_2:
581 case RT5665_I2S1_F_DIV_CTRL_1:
582 case RT5665_I2S1_F_DIV_CTRL_2:
583 case RT5665_TDM_CTRL_1:
584 case RT5665_TDM_CTRL_2:
585 case RT5665_TDM_CTRL_3:
586 case RT5665_TDM_CTRL_4:
587 case RT5665_TDM_CTRL_5:
588 case RT5665_TDM_CTRL_6:
589 case RT5665_TDM_CTRL_7:
590 case RT5665_TDM_CTRL_8:
591 case RT5665_GLB_CLK:
592 case RT5665_PLL_CTRL_1:
593 case RT5665_PLL_CTRL_2:
594 case RT5665_ASRC_1:
595 case RT5665_ASRC_2:
596 case RT5665_ASRC_3:
597 case RT5665_ASRC_4:
598 case RT5665_ASRC_5:
599 case RT5665_ASRC_6:
600 case RT5665_ASRC_7:
601 case RT5665_ASRC_8:
602 case RT5665_ASRC_9:
603 case RT5665_ASRC_10:
604 case RT5665_DEPOP_1:
605 case RT5665_DEPOP_2:
606 case RT5665_HP_CHARGE_PUMP_1:
607 case RT5665_HP_CHARGE_PUMP_2:
608 case RT5665_MICBIAS_1:
609 case RT5665_MICBIAS_2:
610 case RT5665_ASRC_12:
611 case RT5665_ASRC_13:
612 case RT5665_ASRC_14:
613 case RT5665_RC_CLK_CTRL:
614 case RT5665_I2S_M_CLK_CTRL_1:
615 case RT5665_I2S2_F_DIV_CTRL_1:
616 case RT5665_I2S2_F_DIV_CTRL_2:
617 case RT5665_I2S3_F_DIV_CTRL_1:
618 case RT5665_I2S3_F_DIV_CTRL_2:
619 case RT5665_EQ_CTRL_1:
620 case RT5665_EQ_CTRL_2:
621 case RT5665_IRQ_CTRL_1:
622 case RT5665_IRQ_CTRL_2:
623 case RT5665_IRQ_CTRL_3:
624 case RT5665_IRQ_CTRL_4:
625 case RT5665_IRQ_CTRL_5:
626 case RT5665_IRQ_CTRL_6:
627 case RT5665_INT_ST_1:
628 case RT5665_GPIO_CTRL_1:
629 case RT5665_GPIO_CTRL_2:
630 case RT5665_GPIO_CTRL_3:
631 case RT5665_GPIO_CTRL_4:
632 case RT5665_GPIO_STA:
633 case RT5665_HP_AMP_DET_CTRL_1:
634 case RT5665_HP_AMP_DET_CTRL_2:
635 case RT5665_MID_HP_AMP_DET:
636 case RT5665_LOW_HP_AMP_DET:
637 case RT5665_SV_ZCD_1:
638 case RT5665_SV_ZCD_2:
639 case RT5665_IL_CMD_1:
640 case RT5665_IL_CMD_2:
641 case RT5665_IL_CMD_3:
642 case RT5665_IL_CMD_4:
643 case RT5665_4BTN_IL_CMD_1:
644 case RT5665_4BTN_IL_CMD_2:
645 case RT5665_4BTN_IL_CMD_3:
646 case RT5665_PSV_IL_CMD_1:
647 case RT5665_ADC_STO1_HP_CTRL_1:
648 case RT5665_ADC_STO1_HP_CTRL_2:
649 case RT5665_ADC_MONO_HP_CTRL_1:
650 case RT5665_ADC_MONO_HP_CTRL_2:
651 case RT5665_ADC_STO2_HP_CTRL_1:
652 case RT5665_ADC_STO2_HP_CTRL_2:
653 case RT5665_AJD1_CTRL:
654 case RT5665_JD1_THD:
655 case RT5665_JD2_THD:
656 case RT5665_JD_CTRL_1:
657 case RT5665_JD_CTRL_2:
658 case RT5665_JD_CTRL_3:
659 case RT5665_DIG_MISC:
660 case RT5665_DUMMY_2:
661 case RT5665_DUMMY_3:
662 case RT5665_DAC_ADC_DIG_VOL1:
663 case RT5665_DAC_ADC_DIG_VOL2:
664 case RT5665_BIAS_CUR_CTRL_1:
665 case RT5665_BIAS_CUR_CTRL_2:
666 case RT5665_BIAS_CUR_CTRL_3:
667 case RT5665_BIAS_CUR_CTRL_4:
668 case RT5665_BIAS_CUR_CTRL_5:
669 case RT5665_BIAS_CUR_CTRL_6:
670 case RT5665_BIAS_CUR_CTRL_7:
671 case RT5665_BIAS_CUR_CTRL_8:
672 case RT5665_BIAS_CUR_CTRL_9:
673 case RT5665_BIAS_CUR_CTRL_10:
674 case RT5665_VREF_REC_OP_FB_CAP_CTRL:
675 case RT5665_CHARGE_PUMP_1:
676 case RT5665_DIG_IN_CTRL_1:
677 case RT5665_DIG_IN_CTRL_2:
678 case RT5665_PAD_DRIVING_CTRL:
679 case RT5665_SOFT_RAMP_DEPOP:
680 case RT5665_PLL:
681 case RT5665_CHOP_DAC:
682 case RT5665_CHOP_ADC:
683 case RT5665_CALIB_ADC_CTRL:
684 case RT5665_VOL_TEST:
685 case RT5665_TEST_MODE_CTRL_1:
686 case RT5665_TEST_MODE_CTRL_2:
687 case RT5665_TEST_MODE_CTRL_3:
688 case RT5665_TEST_MODE_CTRL_4:
689 case RT5665_BASSBACK_CTRL:
690 case RT5665_STO_NG2_CTRL_1:
691 case RT5665_STO_NG2_CTRL_2:
692 case RT5665_STO_NG2_CTRL_3:
693 case RT5665_STO_NG2_CTRL_4:
694 case RT5665_STO_NG2_CTRL_5:
695 case RT5665_STO_NG2_CTRL_6:
696 case RT5665_STO_NG2_CTRL_7:
697 case RT5665_STO_NG2_CTRL_8:
698 case RT5665_MONO_NG2_CTRL_1:
699 case RT5665_MONO_NG2_CTRL_2:
700 case RT5665_MONO_NG2_CTRL_3:
701 case RT5665_MONO_NG2_CTRL_4:
702 case RT5665_MONO_NG2_CTRL_5:
703 case RT5665_MONO_NG2_CTRL_6:
704 case RT5665_STO1_DAC_SIL_DET:
705 case RT5665_MONOL_DAC_SIL_DET:
706 case RT5665_MONOR_DAC_SIL_DET:
707 case RT5665_STO2_DAC_SIL_DET:
708 case RT5665_SIL_PSV_CTRL1:
709 case RT5665_SIL_PSV_CTRL2:
710 case RT5665_SIL_PSV_CTRL3:
711 case RT5665_SIL_PSV_CTRL4:
712 case RT5665_SIL_PSV_CTRL5:
713 case RT5665_SIL_PSV_CTRL6:
714 case RT5665_MONO_AMP_CALIB_CTRL_1:
715 case RT5665_MONO_AMP_CALIB_CTRL_2:
716 case RT5665_MONO_AMP_CALIB_CTRL_3:
717 case RT5665_MONO_AMP_CALIB_CTRL_4:
718 case RT5665_MONO_AMP_CALIB_CTRL_5:
719 case RT5665_MONO_AMP_CALIB_CTRL_6:
720 case RT5665_MONO_AMP_CALIB_CTRL_7:
721 case RT5665_MONO_AMP_CALIB_STA1:
722 case RT5665_MONO_AMP_CALIB_STA2:
723 case RT5665_MONO_AMP_CALIB_STA3:
724 case RT5665_MONO_AMP_CALIB_STA4:
725 case RT5665_MONO_AMP_CALIB_STA6:
726 case RT5665_HP_IMP_SENS_CTRL_01:
727 case RT5665_HP_IMP_SENS_CTRL_02:
728 case RT5665_HP_IMP_SENS_CTRL_03:
729 case RT5665_HP_IMP_SENS_CTRL_04:
730 case RT5665_HP_IMP_SENS_CTRL_05:
731 case RT5665_HP_IMP_SENS_CTRL_06:
732 case RT5665_HP_IMP_SENS_CTRL_07:
733 case RT5665_HP_IMP_SENS_CTRL_08:
734 case RT5665_HP_IMP_SENS_CTRL_09:
735 case RT5665_HP_IMP_SENS_CTRL_10:
736 case RT5665_HP_IMP_SENS_CTRL_11:
737 case RT5665_HP_IMP_SENS_CTRL_12:
738 case RT5665_HP_IMP_SENS_CTRL_13:
739 case RT5665_HP_IMP_SENS_CTRL_14:
740 case RT5665_HP_IMP_SENS_CTRL_15:
741 case RT5665_HP_IMP_SENS_CTRL_16:
742 case RT5665_HP_IMP_SENS_CTRL_17:
743 case RT5665_HP_IMP_SENS_CTRL_18:
744 case RT5665_HP_IMP_SENS_CTRL_19:
745 case RT5665_HP_IMP_SENS_CTRL_20:
746 case RT5665_HP_IMP_SENS_CTRL_21:
747 case RT5665_HP_IMP_SENS_CTRL_22:
748 case RT5665_HP_IMP_SENS_CTRL_23:
749 case RT5665_HP_IMP_SENS_CTRL_24:
750 case RT5665_HP_IMP_SENS_CTRL_25:
751 case RT5665_HP_IMP_SENS_CTRL_26:
752 case RT5665_HP_IMP_SENS_CTRL_27:
753 case RT5665_HP_IMP_SENS_CTRL_28:
754 case RT5665_HP_IMP_SENS_CTRL_29:
755 case RT5665_HP_IMP_SENS_CTRL_30:
756 case RT5665_HP_IMP_SENS_CTRL_31:
757 case RT5665_HP_IMP_SENS_CTRL_32:
758 case RT5665_HP_IMP_SENS_CTRL_33:
759 case RT5665_HP_IMP_SENS_CTRL_34:
760 case RT5665_HP_LOGIC_CTRL_1:
761 case RT5665_HP_LOGIC_CTRL_2:
762 case RT5665_HP_LOGIC_CTRL_3:
763 case RT5665_HP_CALIB_CTRL_1:
764 case RT5665_HP_CALIB_CTRL_2:
765 case RT5665_HP_CALIB_CTRL_3:
766 case RT5665_HP_CALIB_CTRL_4:
767 case RT5665_HP_CALIB_CTRL_5:
768 case RT5665_HP_CALIB_CTRL_6:
769 case RT5665_HP_CALIB_CTRL_7:
770 case RT5665_HP_CALIB_CTRL_9:
771 case RT5665_HP_CALIB_CTRL_10:
772 case RT5665_HP_CALIB_CTRL_11:
773 case RT5665_HP_CALIB_STA_1:
774 case RT5665_HP_CALIB_STA_2:
775 case RT5665_HP_CALIB_STA_3:
776 case RT5665_HP_CALIB_STA_4:
777 case RT5665_HP_CALIB_STA_5:
778 case RT5665_HP_CALIB_STA_6:
779 case RT5665_HP_CALIB_STA_7:
780 case RT5665_HP_CALIB_STA_8:
781 case RT5665_HP_CALIB_STA_9:
782 case RT5665_HP_CALIB_STA_10:
783 case RT5665_HP_CALIB_STA_11:
784 case RT5665_PGM_TAB_CTRL1:
785 case RT5665_PGM_TAB_CTRL2:
786 case RT5665_PGM_TAB_CTRL3:
787 case RT5665_PGM_TAB_CTRL4:
788 case RT5665_PGM_TAB_CTRL5:
789 case RT5665_PGM_TAB_CTRL6:
790 case RT5665_PGM_TAB_CTRL7:
791 case RT5665_PGM_TAB_CTRL8:
792 case RT5665_PGM_TAB_CTRL9:
793 case RT5665_SAR_IL_CMD_1:
794 case RT5665_SAR_IL_CMD_2:
795 case RT5665_SAR_IL_CMD_3:
796 case RT5665_SAR_IL_CMD_4:
797 case RT5665_SAR_IL_CMD_5:
798 case RT5665_SAR_IL_CMD_6:
799 case RT5665_SAR_IL_CMD_7:
800 case RT5665_SAR_IL_CMD_8:
801 case RT5665_SAR_IL_CMD_9:
802 case RT5665_SAR_IL_CMD_10:
803 case RT5665_SAR_IL_CMD_11:
804 case RT5665_SAR_IL_CMD_12:
805 case RT5665_DRC1_CTRL_0:
806 case RT5665_DRC1_CTRL_1:
807 case RT5665_DRC1_CTRL_2:
808 case RT5665_DRC1_CTRL_3:
809 case RT5665_DRC1_CTRL_4:
810 case RT5665_DRC1_CTRL_5:
811 case RT5665_DRC1_CTRL_6:
812 case RT5665_DRC1_HARD_LMT_CTRL_1:
813 case RT5665_DRC1_HARD_LMT_CTRL_2:
814 case RT5665_DRC1_PRIV_1:
815 case RT5665_DRC1_PRIV_2:
816 case RT5665_DRC1_PRIV_3:
817 case RT5665_DRC1_PRIV_4:
818 case RT5665_DRC1_PRIV_5:
819 case RT5665_DRC1_PRIV_6:
820 case RT5665_DRC1_PRIV_7:
821 case RT5665_DRC1_PRIV_8:
822 case RT5665_ALC_PGA_CTRL_1:
823 case RT5665_ALC_PGA_CTRL_2:
824 case RT5665_ALC_PGA_CTRL_3:
825 case RT5665_ALC_PGA_CTRL_4:
826 case RT5665_ALC_PGA_CTRL_5:
827 case RT5665_ALC_PGA_CTRL_6:
828 case RT5665_ALC_PGA_CTRL_7:
829 case RT5665_ALC_PGA_CTRL_8:
830 case RT5665_ALC_PGA_STA_1:
831 case RT5665_ALC_PGA_STA_2:
832 case RT5665_ALC_PGA_STA_3:
833 case RT5665_EQ_AUTO_RCV_CTRL1:
834 case RT5665_EQ_AUTO_RCV_CTRL2:
835 case RT5665_EQ_AUTO_RCV_CTRL3:
836 case RT5665_EQ_AUTO_RCV_CTRL4:
837 case RT5665_EQ_AUTO_RCV_CTRL5:
838 case RT5665_EQ_AUTO_RCV_CTRL6:
839 case RT5665_EQ_AUTO_RCV_CTRL7:
840 case RT5665_EQ_AUTO_RCV_CTRL8:
841 case RT5665_EQ_AUTO_RCV_CTRL9:
842 case RT5665_EQ_AUTO_RCV_CTRL10:
843 case RT5665_EQ_AUTO_RCV_CTRL11:
844 case RT5665_EQ_AUTO_RCV_CTRL12:
845 case RT5665_EQ_AUTO_RCV_CTRL13:
846 case RT5665_ADC_L_EQ_LPF1_A1:
847 case RT5665_R_EQ_LPF1_A1:
848 case RT5665_L_EQ_LPF1_H0:
849 case RT5665_R_EQ_LPF1_H0:
850 case RT5665_L_EQ_BPF1_A1:
851 case RT5665_R_EQ_BPF1_A1:
852 case RT5665_L_EQ_BPF1_A2:
853 case RT5665_R_EQ_BPF1_A2:
854 case RT5665_L_EQ_BPF1_H0:
855 case RT5665_R_EQ_BPF1_H0:
856 case RT5665_L_EQ_BPF2_A1:
857 case RT5665_R_EQ_BPF2_A1:
858 case RT5665_L_EQ_BPF2_A2:
859 case RT5665_R_EQ_BPF2_A2:
860 case RT5665_L_EQ_BPF2_H0:
861 case RT5665_R_EQ_BPF2_H0:
862 case RT5665_L_EQ_BPF3_A1:
863 case RT5665_R_EQ_BPF3_A1:
864 case RT5665_L_EQ_BPF3_A2:
865 case RT5665_R_EQ_BPF3_A2:
866 case RT5665_L_EQ_BPF3_H0:
867 case RT5665_R_EQ_BPF3_H0:
868 case RT5665_L_EQ_BPF4_A1:
869 case RT5665_R_EQ_BPF4_A1:
870 case RT5665_L_EQ_BPF4_A2:
871 case RT5665_R_EQ_BPF4_A2:
872 case RT5665_L_EQ_BPF4_H0:
873 case RT5665_R_EQ_BPF4_H0:
874 case RT5665_L_EQ_HPF1_A1:
875 case RT5665_R_EQ_HPF1_A1:
876 case RT5665_L_EQ_HPF1_H0:
877 case RT5665_R_EQ_HPF1_H0:
878 case RT5665_L_EQ_PRE_VOL:
879 case RT5665_R_EQ_PRE_VOL:
880 case RT5665_L_EQ_POST_VOL:
881 case RT5665_R_EQ_POST_VOL:
882 case RT5665_SCAN_MODE_CTRL:
883 case RT5665_I2C_MODE:
884 return true;
885 default:
886 return false;
887 }
888}
889
890static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
891static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
892static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
893static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
894static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
895static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
896static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
897static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
898
899/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
900static const DECLARE_TLV_DB_RANGE(bst_tlv,
901 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
902 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
903 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
904 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
905 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
906 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
907 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
908);
909
910/* Interface data select */
911static const char * const rt5665_data_select[] = {
912 "L/R", "R/L", "L/L", "R/R"
913};
914
915static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
916 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
917
918static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
919 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
920
921static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
922 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
923
924static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
925 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
926
927static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
928 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
929
930static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
931 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
932
933static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
934 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
935
936static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
937 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
938
939static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
940 RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
941
942static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
943 RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
944
945static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
946 RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
947
948static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
949 RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
950
951static const SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
952 RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
953
954static const SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
955 RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
956
957static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
958 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
959
960static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
961 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
962
963static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
964 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
965
966static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
967 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
968
969static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
970 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
971
972static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
973 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
974
975static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
976 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
977
978static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
979 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
980
981static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
982 SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
983
984static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
985 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
986
987static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
988 SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
989
990static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
991 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
992
993static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
994 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
995
996static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
997 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
998
999static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1001{
1002 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1003 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1004
1005 if (snd_soc_read(codec, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
1006 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1007 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1008 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1009 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1010 }
1011
1012 return ret;
1013}
1014
1015static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
1016 struct snd_ctl_elem_value *ucontrol)
1017{
1018 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1019 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1020
1021 if (snd_soc_read(codec, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
1022 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1023 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1024 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1025 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1026 }
1027
1028 return ret;
1029}
1030
1031/**
1032 * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
1033 * @codec: SoC audio codec device.
1034 * @filter_mask: mask of filters.
1035 * @clk_src: clock source
1036 *
1037 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
1038 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1039 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1040 * ASRC function will track i2s clock and generate a corresponding system clock
1041 * for codec. This function provides an API to select the clock source for a
1042 * set of filters specified by the mask. And the codec driver will turn on ASRC
1043 * for these filters if ASRC is selected as their clock source.
1044 */
1045int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
1046 unsigned int filter_mask, unsigned int clk_src)
1047{
1048 unsigned int asrc2_mask = 0;
1049 unsigned int asrc2_value = 0;
1050 unsigned int asrc3_mask = 0;
1051 unsigned int asrc3_value = 0;
1052
1053 switch (clk_src) {
1054 case RT5665_CLK_SEL_SYS:
1055 case RT5665_CLK_SEL_I2S1_ASRC:
1056 case RT5665_CLK_SEL_I2S2_ASRC:
1057 case RT5665_CLK_SEL_I2S3_ASRC:
1058 case RT5665_CLK_SEL_SYS2:
1059 case RT5665_CLK_SEL_SYS3:
1060 case RT5665_CLK_SEL_SYS4:
1061 break;
1062
1063 default:
1064 return -EINVAL;
1065 }
1066
1067 if (filter_mask & RT5665_DA_STEREO1_FILTER) {
1068 asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
1069 asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
1070 | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
1071 }
1072
1073 if (filter_mask & RT5665_DA_STEREO2_FILTER) {
1074 asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
1075 asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
1076 | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
1077 }
1078
1079 if (filter_mask & RT5665_DA_MONO_L_FILTER) {
1080 asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
1081 asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
1082 | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
1083 }
1084
1085 if (filter_mask & RT5665_DA_MONO_R_FILTER) {
1086 asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
1087 asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
1088 | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
1089 }
1090
1091 if (filter_mask & RT5665_AD_STEREO1_FILTER) {
1092 asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
1093 asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
1094 | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
1095 }
1096
1097 if (filter_mask & RT5665_AD_STEREO2_FILTER) {
1098 asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
1099 asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
1100 | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
1101 }
1102
1103 if (filter_mask & RT5665_AD_MONO_L_FILTER) {
1104 asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
1105 asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
1106 | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
1107 }
1108
1109 if (filter_mask & RT5665_AD_MONO_R_FILTER) {
1110 asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
1111 asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
1112 | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
1113 }
1114
1115 if (asrc2_mask)
1116 snd_soc_update_bits(codec, RT5665_ASRC_2,
1117 asrc2_mask, asrc2_value);
1118
1119 if (asrc3_mask)
1120 snd_soc_update_bits(codec, RT5665_ASRC_3,
1121 asrc3_mask, asrc3_value);
1122
1123 return 0;
1124}
1125EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
1126
1127static int rt5665_button_detect(struct snd_soc_codec *codec)
1128{
1129 int btn_type, val;
1130
1131 val = snd_soc_read(codec, RT5665_4BTN_IL_CMD_1);
1132 btn_type = val & 0xfff0;
1133 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, val);
1134
1135 return btn_type;
1136}
1137
1138static void rt5665_enable_push_button_irq(struct snd_soc_codec *codec,
1139 bool enable)
1140{
1141 if (enable) {
Bard Liao246126b2017-03-08 19:05:33 +0800[diff] [blame]1142 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, 0x0003);
1143 snd_soc_update_bits(codec, RT5665_SAR_IL_CMD_9, 0x1, 0x1);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1144 snd_soc_write(codec, RT5665_IL_CMD_1, 0x0048);
1145 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1146 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
1147 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
1148 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1149 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
1150 } else {
1151 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1152 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
1153 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1154 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
1155 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1156 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
1157 }
1158}
1159
1160/**
1161 * rt5665_headset_detect - Detect headset.
1162 * @codec: SoC audio codec device.
1163 * @jack_insert: Jack insert or not.
1164 *
1165 * Detect whether is headset or not when jack inserted.
1166 *
1167 * Returns detect status.
1168 */
1169static int rt5665_headset_detect(struct snd_soc_codec *codec, int jack_insert)
1170{
1171 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1172 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1173 unsigned int sar_hs_type, val;
1174
1175 if (jack_insert) {
1176 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1177 snd_soc_dapm_sync(dapm);
1178
1179 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1180 0x100);
1181
1182 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1183 if (val & 0x4) {
1184 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1185 0x100, 0);
1186
1187 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1188 while (val & 0x4) {
1189 usleep_range(10000, 15000);
1190 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1191 &val);
1192 }
1193 }
1194
1195 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
Bard Liao39841942017-03-08 19:05:30 +0800[diff] [blame]1196 0x1a0, 0x120);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1197 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
Bard Liao39841942017-03-08 19:05:30 +0800[diff] [blame]1198 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1199 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1200
Bard Liao39841942017-03-08 19:05:30 +0800[diff] [blame]1201 usleep_range(10000, 15000);
1202
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1203 rt5665->sar_adc_value = snd_soc_read(rt5665->codec,
1204 RT5665_SAR_IL_CMD_4) & 0x7ff;
1205
1206 sar_hs_type = rt5665->pdata.sar_hs_type ?
1207 rt5665->pdata.sar_hs_type : 729;
1208
1209 if (rt5665->sar_adc_value > sar_hs_type) {
1210 rt5665->jack_type = SND_JACK_HEADSET;
1211 rt5665_enable_push_button_irq(codec, true);
1212 } else {
1213 rt5665->jack_type = SND_JACK_HEADPHONE;
1214 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1215 0x2291);
1216 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1217 0x100, 0);
1218 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1219 snd_soc_dapm_sync(dapm);
1220 }
1221 } else {
1222 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1223 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1224 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1225 snd_soc_dapm_sync(dapm);
1226 if (rt5665->jack_type == SND_JACK_HEADSET)
1227 rt5665_enable_push_button_irq(codec, false);
1228 rt5665->jack_type = 0;
1229 }
1230
1231 dev_dbg(codec->dev, "jack_type = %d\n", rt5665->jack_type);
1232 return rt5665->jack_type;
1233}
1234
1235static irqreturn_t rt5665_irq(int irq, void *data)
1236{
1237 struct rt5665_priv *rt5665 = data;
1238
1239 mod_delayed_work(system_power_efficient_wq,
1240 &rt5665->jack_detect_work, msecs_to_jiffies(250));
1241
1242 return IRQ_HANDLED;
1243}
1244
1245static void rt5665_jd_check_handler(struct work_struct *work)
1246{
1247 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
Bard Liaof1994a92017-03-08 19:03:10 +0800[diff] [blame]1248 jd_check_work.work);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1249
1250 if (snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010) {
1251 /* jack out */
1252 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1253
1254 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1255 SND_JACK_HEADSET |
1256 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1257 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1258 } else {
1259 schedule_delayed_work(&rt5665->jd_check_work, 500);
1260 }
1261}
1262
1263int rt5665_set_jack_detect(struct snd_soc_codec *codec,
1264 struct snd_soc_jack *hs_jack)
1265{
1266 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1267
1268 switch (rt5665->pdata.jd_src) {
1269 case RT5665_JD1:
1270 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1271 RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
1272 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1273 0xc000, 0xc000);
1274 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1275 RT5665_PWR_JD1, RT5665_PWR_JD1);
1276 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1277 break;
1278
1279 case RT5665_JD_NULL:
1280 break;
1281
1282 default:
1283 dev_warn(codec->dev, "Wrong JD source\n");
1284 break;
1285 }
1286
1287 rt5665->hs_jack = hs_jack;
1288
1289 return 0;
1290}
1291EXPORT_SYMBOL_GPL(rt5665_set_jack_detect);
1292
1293static void rt5665_jack_detect_handler(struct work_struct *work)
1294{
1295 struct rt5665_priv *rt5665 =
1296 container_of(work, struct rt5665_priv, jack_detect_work.work);
1297 int val, btn_type;
1298
1299 while (!rt5665->codec) {
1300 pr_debug("%s codec = null\n", __func__);
1301 usleep_range(10000, 15000);
1302 }
1303
1304 while (!rt5665->codec->component.card->instantiated) {
1305 pr_debug("%s\n", __func__);
1306 usleep_range(10000, 15000);
1307 }
1308
1309 mutex_lock(&rt5665->calibrate_mutex);
1310
1311 val = snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010;
1312 if (!val) {
1313 /* jack in */
1314 if (rt5665->jack_type == 0) {
1315 /* jack was out, report jack type */
1316 rt5665->jack_type =
1317 rt5665_headset_detect(rt5665->codec, 1);
1318 } else {
1319 /* jack is already in, report button event */
1320 rt5665->jack_type = SND_JACK_HEADSET;
1321 btn_type = rt5665_button_detect(rt5665->codec);
1322 /**
1323 * rt5665 can report three kinds of button behavior,
1324 * one click, double click and hold. However,
1325 * currently we will report button pressed/released
1326 * event. So all the three button behaviors are
1327 * treated as button pressed.
1328 */
1329 switch (btn_type) {
1330 case 0x8000:
1331 case 0x4000:
1332 case 0x2000:
1333 rt5665->jack_type |= SND_JACK_BTN_0;
1334 break;
1335 case 0x1000:
1336 case 0x0800:
1337 case 0x0400:
1338 rt5665->jack_type |= SND_JACK_BTN_1;
1339 break;
1340 case 0x0200:
1341 case 0x0100:
1342 case 0x0080:
1343 rt5665->jack_type |= SND_JACK_BTN_2;
1344 break;
1345 case 0x0040:
1346 case 0x0020:
1347 case 0x0010:
1348 rt5665->jack_type |= SND_JACK_BTN_3;
1349 break;
1350 case 0x0000: /* unpressed */
1351 break;
1352 default:
1353 btn_type = 0;
1354 dev_err(rt5665->codec->dev,
1355 "Unexpected button code 0x%04x\n",
1356 btn_type);
1357 break;
1358 }
1359 }
1360 } else {
1361 /* jack out */
1362 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1363 }
1364
1365 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1366 SND_JACK_HEADSET |
1367 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1368 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1369
1370 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1371 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1372 schedule_delayed_work(&rt5665->jd_check_work, 0);
1373 else
1374 cancel_delayed_work_sync(&rt5665->jd_check_work);
1375
1376 mutex_unlock(&rt5665->calibrate_mutex);
1377}
1378
1379static const struct snd_kcontrol_new rt5665_snd_controls[] = {
1380 /* Headphone Output Volume */
1381 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
1382 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
1383 rt5665_hp_vol_put, hp_vol_tlv),
1384
1385 /* Mono Output Volume */
1386 SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
1387 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
1388 rt5665_mono_vol_put, mono_vol_tlv),
1389
1390 /* Output Volume */
1391 SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
1392 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
1393
1394 /* DAC Digital Volume */
1395 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
1396 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1397 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
1398 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1399 SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
1400 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
1401
1402 /* IN1/IN2/IN3/IN4 Volume */
1403 SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
1404 RT5665_BST1_SFT, 69, 0, in_bst_tlv),
1405 SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
1406 RT5665_BST2_SFT, 69, 0, in_bst_tlv),
1407 SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
1408 RT5665_BST3_SFT, 69, 0, in_bst_tlv),
1409 SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
1410 RT5665_BST4_SFT, 69, 0, in_bst_tlv),
1411 SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
1412 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
1413
1414 /* INL/INR Volume Control */
1415 SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
1416 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
1417
1418 /* ADC Digital Volume Control */
1419 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
1420 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1421 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
1422 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1423 SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
1424 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1425 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
1426 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1427 SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
1428 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1429 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
1430 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1431
1432 /* ADC Boost Volume Control */
1433 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
1434 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
1435 3, 0, adc_bst_tlv),
1436
1437 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
1438 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
1439 3, 0, adc_bst_tlv),
1440
1441 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
1442 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
1443 3, 0, adc_bst_tlv),
1444};
1445
1446/**
1447 * set_dmic_clk - Set parameter of dmic.
1448 *
1449 * @w: DAPM widget.
1450 * @kcontrol: The kcontrol of this widget.
1451 * @event: Event id.
1452 *
1453 * Choose dmic clock between 1MHz and 3MHz.
1454 * It is better for clock to approximate 3MHz.
1455 */
1456static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1457 struct snd_kcontrol *kcontrol, int event)
1458{
1459 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1460 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1461 int pd, idx = -EINVAL;
1462
1463 pd = rl6231_get_pre_div(rt5665->regmap,
1464 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
1465 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1466
1467 if (idx < 0)
1468 dev_err(codec->dev, "Failed to set DMIC clock\n");
1469 else {
1470 snd_soc_update_bits(codec, RT5665_DMIC_CTRL_1,
1471 RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
1472 }
1473 return idx;
1474}
1475
1476static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
1477 struct snd_kcontrol *kcontrol, int event)
1478{
1479 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1480
1481 switch (event) {
1482 case SND_SOC_DAPM_PRE_PMU:
1483 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1484 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1485 RT5665_PM_HP_HV | RT5665_OSW_L_EN);
1486 break;
1487 case SND_SOC_DAPM_POST_PMD:
1488 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1489 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1490 RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
1491 break;
1492 default:
1493 return 0;
1494 }
1495
1496 return 0;
1497}
1498
1499static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1500 struct snd_soc_dapm_widget *sink)
1501{
1502 unsigned int val;
1503 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1504
1505 val = snd_soc_read(codec, RT5665_GLB_CLK);
1506 val &= RT5665_SCLK_SRC_MASK;
1507 if (val == RT5665_SCLK_SRC_PLL1)
1508 return 1;
1509 else
1510 return 0;
1511}
1512
1513static int is_using_asrc(struct snd_soc_dapm_widget *w,
1514 struct snd_soc_dapm_widget *sink)
1515{
1516 unsigned int reg, shift, val;
1517 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1518
1519 switch (w->shift) {
1520 case RT5665_ADC_MONO_R_ASRC_SFT:
1521 reg = RT5665_ASRC_3;
1522 shift = RT5665_AD_MONOR_CLK_SEL_SFT;
1523 break;
1524 case RT5665_ADC_MONO_L_ASRC_SFT:
1525 reg = RT5665_ASRC_3;
1526 shift = RT5665_AD_MONOL_CLK_SEL_SFT;
1527 break;
1528 case RT5665_ADC_STO1_ASRC_SFT:
1529 reg = RT5665_ASRC_3;
1530 shift = RT5665_AD_STO1_CLK_SEL_SFT;
1531 break;
1532 case RT5665_ADC_STO2_ASRC_SFT:
1533 reg = RT5665_ASRC_3;
1534 shift = RT5665_AD_STO2_CLK_SEL_SFT;
1535 break;
1536 case RT5665_DAC_MONO_R_ASRC_SFT:
1537 reg = RT5665_ASRC_2;
1538 shift = RT5665_DA_MONOR_CLK_SEL_SFT;
1539 break;
1540 case RT5665_DAC_MONO_L_ASRC_SFT:
1541 reg = RT5665_ASRC_2;
1542 shift = RT5665_DA_MONOL_CLK_SEL_SFT;
1543 break;
1544 case RT5665_DAC_STO1_ASRC_SFT:
1545 reg = RT5665_ASRC_2;
1546 shift = RT5665_DA_STO1_CLK_SEL_SFT;
1547 break;
1548 case RT5665_DAC_STO2_ASRC_SFT:
1549 reg = RT5665_ASRC_2;
1550 shift = RT5665_DA_STO2_CLK_SEL_SFT;
1551 break;
1552 default:
1553 return 0;
1554 }
1555
1556 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
1557 switch (val) {
1558 case RT5665_CLK_SEL_I2S1_ASRC:
1559 case RT5665_CLK_SEL_I2S2_ASRC:
1560 case RT5665_CLK_SEL_I2S3_ASRC:
1561 /* I2S_Pre_Div1 should be 1 in asrc mode */
1562 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
1563 RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
1564 return 1;
1565 default:
1566 return 0;
1567 }
1568
1569}
1570
1571/* Digital Mixer */
1572static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
1573 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1574 RT5665_M_STO1_ADC_L1_SFT, 1, 1),
1575 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1576 RT5665_M_STO1_ADC_L2_SFT, 1, 1),
1577};
1578
1579static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
1580 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1581 RT5665_M_STO1_ADC_R1_SFT, 1, 1),
1582 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1583 RT5665_M_STO1_ADC_R2_SFT, 1, 1),
1584};
1585
1586static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
1587 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1588 RT5665_M_STO2_ADC_L1_SFT, 1, 1),
1589 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1590 RT5665_M_STO2_ADC_L2_SFT, 1, 1),
1591};
1592
1593static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
1594 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1595 RT5665_M_STO2_ADC_R1_SFT, 1, 1),
1596 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1597 RT5665_M_STO2_ADC_R2_SFT, 1, 1),
1598};
1599
1600static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
1601 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1602 RT5665_M_MONO_ADC_L1_SFT, 1, 1),
1603 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1604 RT5665_M_MONO_ADC_L2_SFT, 1, 1),
1605};
1606
1607static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
1608 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1609 RT5665_M_MONO_ADC_R1_SFT, 1, 1),
1610 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1611 RT5665_M_MONO_ADC_R2_SFT, 1, 1),
1612};
1613
1614static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
1615 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1616 RT5665_M_ADCMIX_L_SFT, 1, 1),
1617 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1618 RT5665_M_DAC1_L_SFT, 1, 1),
1619};
1620
1621static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
1622 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1623 RT5665_M_ADCMIX_R_SFT, 1, 1),
1624 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1625 RT5665_M_DAC1_R_SFT, 1, 1),
1626};
1627
1628static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
1629 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1630 RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
1631 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1632 RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
1633 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1634 RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
1635 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1636 RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
1637};
1638
1639static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
1640 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1641 RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
1642 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1643 RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
1644 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1645 RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
1646 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1647 RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
1648};
1649
1650static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
1651 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
1652 RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
1653 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
1654 RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
1655 SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
1656 RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
1657};
1658
1659static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
1660 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
1661 RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
1662 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
1663 RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
1664 SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
1665 RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
1666};
1667
1668static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
1669 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1670 RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
1671 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1672 RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
1673 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1674 RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
1675 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1676 RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
1677};
1678
1679static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
1680 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1681 RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
1682 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1683 RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
1684 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1685 RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
1686 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1687 RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
1688};
1689
1690/* Analog Input Mixer */
1691static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
1692 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
1693 RT5665_M_CBJ_RM1_L_SFT, 1, 1),
1694 SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
1695 RT5665_M_INL_RM1_L_SFT, 1, 1),
1696 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
1697 RT5665_M_INR_RM1_L_SFT, 1, 1),
1698 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
1699 RT5665_M_BST4_RM1_L_SFT, 1, 1),
1700 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
1701 RT5665_M_BST3_RM1_L_SFT, 1, 1),
1702 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
1703 RT5665_M_BST2_RM1_L_SFT, 1, 1),
1704 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
1705 RT5665_M_BST1_RM1_L_SFT, 1, 1),
1706};
1707
1708static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
1709 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
1710 RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
1711 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
1712 RT5665_M_INR_RM1_R_SFT, 1, 1),
1713 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
1714 RT5665_M_BST4_RM1_R_SFT, 1, 1),
1715 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
1716 RT5665_M_BST3_RM1_R_SFT, 1, 1),
1717 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
1718 RT5665_M_BST2_RM1_R_SFT, 1, 1),
1719 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
1720 RT5665_M_BST1_RM1_R_SFT, 1, 1),
1721};
1722
1723static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
1724 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
1725 RT5665_M_INL_RM2_L_SFT, 1, 1),
1726 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
1727 RT5665_M_INR_RM2_L_SFT, 1, 1),
1728 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
1729 RT5665_M_CBJ_RM2_L_SFT, 1, 1),
1730 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
1731 RT5665_M_BST4_RM2_L_SFT, 1, 1),
1732 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
1733 RT5665_M_BST3_RM2_L_SFT, 1, 1),
1734 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
1735 RT5665_M_BST2_RM2_L_SFT, 1, 1),
1736 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
1737 RT5665_M_BST1_RM2_L_SFT, 1, 1),
1738};
1739
1740static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
1741 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
1742 RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
1743 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
1744 RT5665_M_INL_RM2_R_SFT, 1, 1),
1745 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
1746 RT5665_M_INR_RM2_R_SFT, 1, 1),
1747 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
1748 RT5665_M_BST4_RM2_R_SFT, 1, 1),
1749 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
1750 RT5665_M_BST3_RM2_R_SFT, 1, 1),
1751 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
1752 RT5665_M_BST2_RM2_R_SFT, 1, 1),
1753 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
1754 RT5665_M_BST1_RM2_R_SFT, 1, 1),
1755};
1756
1757static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
1758 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1759 RT5665_M_DAC_L2_MM_SFT, 1, 1),
1760 SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
1761 RT5665_M_RECMIC2L_MM_SFT, 1, 1),
1762 SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
1763 RT5665_M_BST1_MM_SFT, 1, 1),
1764 SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
1765 RT5665_M_BST2_MM_SFT, 1, 1),
1766 SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
1767 RT5665_M_BST3_MM_SFT, 1, 1),
1768};
1769
1770static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
1771 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
1772 RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
1773 SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
1774 RT5665_M_IN_L_OM_L_SFT, 1, 1),
1775 SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
1776 RT5665_M_BST1_OM_L_SFT, 1, 1),
1777 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
1778 RT5665_M_BST2_OM_L_SFT, 1, 1),
1779 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
1780 RT5665_M_BST3_OM_L_SFT, 1, 1),
1781};
1782
1783static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
1784 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
1785 RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
1786 SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
1787 RT5665_M_IN_R_OM_R_SFT, 1, 1),
1788 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
1789 RT5665_M_BST2_OM_R_SFT, 1, 1),
1790 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
1791 RT5665_M_BST3_OM_R_SFT, 1, 1),
1792 SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
1793 RT5665_M_BST4_OM_R_SFT, 1, 1),
1794};
1795
1796static const struct snd_kcontrol_new rt5665_mono_mix[] = {
1797 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1798 RT5665_M_DAC_L2_MA_SFT, 1, 1),
1799 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
1800 RT5665_M_MONOVOL_MA_SFT, 1, 1),
1801};
1802
1803static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
1804 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
1805 RT5665_M_DAC_L2_LM_SFT, 1, 1),
1806 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
1807 RT5665_M_OV_L_LM_SFT, 1, 1),
1808};
1809
1810static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
1811 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
1812 RT5665_M_DAC_R2_LM_SFT, 1, 1),
1813 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
1814 RT5665_M_OV_R_LM_SFT, 1, 1),
1815};
1816
1817/*DAC L2, DAC R2*/
1818/*MX-17 [6:4], MX-17 [2:0]*/
1819static const char * const rt5665_dac2_src[] = {
1820 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
1821};
1822
1823static const SOC_ENUM_SINGLE_DECL(
1824 rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
1825 RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
1826
1827static const struct snd_kcontrol_new rt5665_dac_l2_mux =
1828 SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
1829
1830static const SOC_ENUM_SINGLE_DECL(
1831 rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
1832 RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
1833
1834static const struct snd_kcontrol_new rt5665_dac_r2_mux =
1835 SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
1836
1837/*DAC L3, DAC R3*/
1838/*MX-1B [6:4], MX-1B [2:0]*/
1839static const char * const rt5665_dac3_src[] = {
1840 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
1841};
1842
1843static const SOC_ENUM_SINGLE_DECL(
1844 rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
1845 RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
1846
1847static const struct snd_kcontrol_new rt5665_dac_l3_mux =
1848 SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
1849
1850static const SOC_ENUM_SINGLE_DECL(
1851 rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
1852 RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
1853
1854static const struct snd_kcontrol_new rt5665_dac_r3_mux =
1855 SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
1856
1857/* STO1 ADC1 Source */
1858/* MX-26 [13] [5] */
1859static const char * const rt5665_sto1_adc1_src[] = {
1860 "DD Mux", "ADC"
1861};
1862
1863static const SOC_ENUM_SINGLE_DECL(
1864 rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
1865 RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
1866
1867static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
1868 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
1869
1870static const SOC_ENUM_SINGLE_DECL(
1871 rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
1872 RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
1873
1874static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
1875 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
1876
1877/* STO1 ADC Source */
1878/* MX-26 [11:10] [3:2] */
1879static const char * const rt5665_sto1_adc_src[] = {
1880 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1881};
1882
1883static const SOC_ENUM_SINGLE_DECL(
1884 rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
1885 RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
1886
1887static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
1888 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
1889
1890static const SOC_ENUM_SINGLE_DECL(
1891 rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
1892 RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
1893
1894static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
1895 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
1896
1897/* STO1 ADC2 Source */
1898/* MX-26 [12] [4] */
1899static const char * const rt5665_sto1_adc2_src[] = {
1900 "DAC MIX", "DMIC"
1901};
1902
1903static const SOC_ENUM_SINGLE_DECL(
1904 rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
1905 RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
1906
1907static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
1908 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
1909
1910static const SOC_ENUM_SINGLE_DECL(
1911 rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
1912 RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
1913
1914static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
1915 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
1916
1917/* STO1 DMIC Source */
1918/* MX-26 [8] */
1919static const char * const rt5665_sto1_dmic_src[] = {
1920 "DMIC1", "DMIC2"
1921};
1922
1923static const SOC_ENUM_SINGLE_DECL(
1924 rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
1925 RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
1926
1927static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
1928 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1929
1930/* MX-26 [9] */
1931static const char * const rt5665_sto1_dd_l_src[] = {
1932 "STO2 DAC", "MONO DAC"
1933};
1934
1935static const SOC_ENUM_SINGLE_DECL(
1936 rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
1937 RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
1938
1939static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
1940 SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
1941
1942/* MX-26 [1:0] */
1943static const char * const rt5665_sto1_dd_r_src[] = {
1944 "STO2 DAC", "MONO DAC", "AEC REF"
1945};
1946
1947static const SOC_ENUM_SINGLE_DECL(
1948 rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
1949 RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
1950
1951static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
1952 SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
1953
1954/* MONO ADC L2 Source */
1955/* MX-27 [12] */
1956static const char * const rt5665_mono_adc_l2_src[] = {
1957 "DAC MIXL", "DMIC"
1958};
1959
1960static const SOC_ENUM_SINGLE_DECL(
1961 rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
1962 RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
1963
1964static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
1965 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
1966
1967
1968/* MONO ADC L1 Source */
1969/* MX-27 [13] */
1970static const char * const rt5665_mono_adc_l1_src[] = {
1971 "DD Mux", "ADC"
1972};
1973
1974static const SOC_ENUM_SINGLE_DECL(
1975 rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
1976 RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
1977
1978static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
1979 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
1980
1981/* MX-27 [9][1]*/
1982static const char * const rt5665_mono_dd_src[] = {
1983 "STO2 DAC", "MONO DAC"
1984};
1985
1986static const SOC_ENUM_SINGLE_DECL(
1987 rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
1988 RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
1989
1990static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
1991 SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
1992
1993static const SOC_ENUM_SINGLE_DECL(
1994 rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
1995 RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
1996
1997static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
1998 SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
1999
2000/* MONO ADC L Source, MONO ADC R Source*/
2001/* MX-27 [11:10], MX-27 [3:2] */
2002static const char * const rt5665_mono_adc_src[] = {
2003 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2004};
2005
2006static const SOC_ENUM_SINGLE_DECL(
2007 rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
2008 RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
2009
2010static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
2011 SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
2012
2013static const SOC_ENUM_SINGLE_DECL(
2014 rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
2015 RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
2016
2017static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
2018 SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
2019
2020/* MONO DMIC L Source */
2021/* MX-27 [8] */
2022static const char * const rt5665_mono_dmic_l_src[] = {
2023 "DMIC1 L", "DMIC2 L"
2024};
2025
2026static const SOC_ENUM_SINGLE_DECL(
2027 rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
2028 RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
2029
2030static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
2031 SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
2032
2033/* MONO ADC R2 Source */
2034/* MX-27 [4] */
2035static const char * const rt5665_mono_adc_r2_src[] = {
2036 "DAC MIXR", "DMIC"
2037};
2038
2039static const SOC_ENUM_SINGLE_DECL(
2040 rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
2041 RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
2042
2043static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
2044 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
2045
2046/* MONO ADC R1 Source */
2047/* MX-27 [5] */
2048static const char * const rt5665_mono_adc_r1_src[] = {
2049 "DD Mux", "ADC"
2050};
2051
2052static const SOC_ENUM_SINGLE_DECL(
2053 rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
2054 RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
2055
2056static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
2057 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
2058
2059/* MONO DMIC R Source */
2060/* MX-27 [0] */
2061static const char * const rt5665_mono_dmic_r_src[] = {
2062 "DMIC1 R", "DMIC2 R"
2063};
2064
2065static const SOC_ENUM_SINGLE_DECL(
2066 rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
2067 RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
2068
2069static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
2070 SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
2071
2072
2073/* STO2 ADC1 Source */
2074/* MX-28 [13] [5] */
2075static const char * const rt5665_sto2_adc1_src[] = {
2076 "DD Mux", "ADC"
2077};
2078
2079static const SOC_ENUM_SINGLE_DECL(
2080 rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
2081 RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
2082
2083static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
2084 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
2085
2086static const SOC_ENUM_SINGLE_DECL(
2087 rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
2088 RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
2089
2090static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
2091 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
2092
2093/* STO2 ADC Source */
2094/* MX-28 [11:10] [3:2] */
2095static const char * const rt5665_sto2_adc_src[] = {
2096 "ADC1 L", "ADC1 R", "ADC2 L"
2097};
2098
2099static const SOC_ENUM_SINGLE_DECL(
2100 rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
2101 RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
2102
2103static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
2104 SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
2105
2106static const SOC_ENUM_SINGLE_DECL(
2107 rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
2108 RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
2109
2110static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
2111 SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
2112
2113/* STO2 ADC2 Source */
2114/* MX-28 [12] [4] */
2115static const char * const rt5665_sto2_adc2_src[] = {
2116 "DAC MIX", "DMIC"
2117};
2118
2119static const SOC_ENUM_SINGLE_DECL(
2120 rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
2121 RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
2122
2123static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
2124 SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
2125
2126static const SOC_ENUM_SINGLE_DECL(
2127 rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
2128 RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
2129
2130static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
2131 SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
2132
2133/* STO2 DMIC Source */
2134/* MX-28 [8] */
2135static const char * const rt5665_sto2_dmic_src[] = {
2136 "DMIC1", "DMIC2"
2137};
2138
2139static const SOC_ENUM_SINGLE_DECL(
2140 rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
2141 RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
2142
2143static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
2144 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
2145
2146/* MX-28 [9] */
2147static const char * const rt5665_sto2_dd_l_src[] = {
2148 "STO2 DAC", "MONO DAC"
2149};
2150
2151static const SOC_ENUM_SINGLE_DECL(
2152 rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
2153 RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
2154
2155static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
2156 SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
2157
2158/* MX-28 [1] */
2159static const char * const rt5665_sto2_dd_r_src[] = {
2160 "STO2 DAC", "MONO DAC"
2161};
2162
2163static const SOC_ENUM_SINGLE_DECL(
2164 rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
2165 RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
2166
2167static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
2168 SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
2169
2170/* DAC R1 Source, DAC L1 Source*/
2171/* MX-29 [11:10], MX-29 [9:8]*/
2172static const char * const rt5665_dac1_src[] = {
2173 "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
2174};
2175
2176static const SOC_ENUM_SINGLE_DECL(
2177 rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
2178 RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
2179
2180static const struct snd_kcontrol_new rt5665_dac_r1_mux =
2181 SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
2182
2183static const SOC_ENUM_SINGLE_DECL(
2184 rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
2185 RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
2186
2187static const struct snd_kcontrol_new rt5665_dac_l1_mux =
2188 SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
2189
2190/* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2191/* MX-2D [13:12], MX-2D [9:8]*/
2192static const char * const rt5665_dig_dac_mix_src[] = {
2193 "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
2194};
2195
2196static const SOC_ENUM_SINGLE_DECL(
2197 rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
2198 RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
2199
2200static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
2201 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
2202
2203static const SOC_ENUM_SINGLE_DECL(
2204 rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
2205 RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
2206
2207static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
2208 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
2209
2210/* Analog DAC L1 Source, Analog DAC R1 Source*/
2211/* MX-2D [5:4], MX-2D [1:0]*/
2212static const char * const rt5665_alg_dac1_src[] = {
2213 "Stereo1 DAC Mixer", "DAC1", "DMIC1"
2214};
2215
2216static const SOC_ENUM_SINGLE_DECL(
2217 rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
2218 RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
2219
2220static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
2221 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
2222
2223static const SOC_ENUM_SINGLE_DECL(
2224 rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
2225 RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
2226
2227static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
2228 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
2229
2230/* Analog DAC LR Source, Analog DAC R2 Source*/
2231/* MX-2E [5:4], MX-2E [0]*/
2232static const char * const rt5665_alg_dac2_src[] = {
2233 "Mono DAC Mixer", "DAC2"
2234};
2235
2236static const SOC_ENUM_SINGLE_DECL(
2237 rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
2238 RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
2239
2240static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
2241 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
2242
2243static const SOC_ENUM_SINGLE_DECL(
2244 rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
2245 RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
2246
2247static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
2248 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
2249
2250/* Interface2 ADC Data Input*/
2251/* MX-2F [14:12] */
2252static const char * const rt5665_if2_1_adc_in_src[] = {
2253 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2254 "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
2255};
2256
2257static const SOC_ENUM_SINGLE_DECL(
2258 rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
2259 RT5665_IF3_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
2260
2261static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
2262 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
2263
2264/* MX-2F [6:4] */
2265static const char * const rt5665_if2_2_adc_in_src[] = {
2266 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2267 "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
2268};
2269
2270static const SOC_ENUM_SINGLE_DECL(
2271 rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
2272 RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
2273
2274static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
2275 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
2276
2277/* Interface3 ADC Data Input*/
2278/* MX-30 [6:4] */
2279static const char * const rt5665_if3_adc_in_src[] = {
2280 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2281 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
2282};
2283
2284static const SOC_ENUM_SINGLE_DECL(
2285 rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
2286 RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
2287
2288static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
2289 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
2290
2291/* PDM 1 L/R*/
2292/* MX-31 [11:10] [9:8] */
2293static const char * const rt5665_pdm_src[] = {
2294 "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
2295};
2296
2297static const SOC_ENUM_SINGLE_DECL(
2298 rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
2299 RT5665_PDM1_L_SFT, rt5665_pdm_src);
2300
2301static const struct snd_kcontrol_new rt5665_pdm_l_mux =
2302 SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
2303
2304static const SOC_ENUM_SINGLE_DECL(
2305 rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
2306 RT5665_PDM1_R_SFT, rt5665_pdm_src);
2307
2308static const struct snd_kcontrol_new rt5665_pdm_r_mux =
2309 SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
2310
2311
2312/* I2S1 TDM ADCDAT Source */
2313/* MX-7a[10] */
2314static const char * const rt5665_if1_1_adc1_data_src[] = {
2315 "STO1 ADC", "IF2_1 DAC",
2316};
2317
2318static const SOC_ENUM_SINGLE_DECL(
2319 rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
2320 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
2321
2322static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
2323 SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
2324
2325/* MX-7a[9] */
2326static const char * const rt5665_if1_1_adc2_data_src[] = {
2327 "STO2 ADC", "IF2_2 DAC",
2328};
2329
2330static const SOC_ENUM_SINGLE_DECL(
2331 rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
2332 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
2333
2334static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
2335 SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
2336
2337/* MX-7a[8] */
2338static const char * const rt5665_if1_1_adc3_data_src[] = {
2339 "MONO ADC", "IF3 DAC",
2340};
2341
2342static const SOC_ENUM_SINGLE_DECL(
2343 rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
2344 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
2345
2346static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
2347 SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
2348
2349/* MX-7b[10] */
2350static const char * const rt5665_if1_2_adc1_data_src[] = {
2351 "STO1 ADC", "IF1 DAC",
2352};
2353
2354static const SOC_ENUM_SINGLE_DECL(
2355 rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
2356 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
2357
2358static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
2359 SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
2360
2361/* MX-7b[9] */
2362static const char * const rt5665_if1_2_adc2_data_src[] = {
2363 "STO2 ADC", "IF2_1 DAC",
2364};
2365
2366static const SOC_ENUM_SINGLE_DECL(
2367 rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
2368 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
2369
2370static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
2371 SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
2372
2373/* MX-7b[8] */
2374static const char * const rt5665_if1_2_adc3_data_src[] = {
2375 "MONO ADC", "IF2_2 DAC",
2376};
2377
2378static const SOC_ENUM_SINGLE_DECL(
2379 rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
2380 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
2381
2382static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
2383 SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
2384
2385/* MX-7b[7] */
2386static const char * const rt5665_if1_2_adc4_data_src[] = {
2387 "DAC1", "IF3 DAC",
2388};
2389
2390static const SOC_ENUM_SINGLE_DECL(
2391 rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
2392 RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
2393
2394static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
2395 SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
2396
2397/* MX-7a[4:0] MX-7b[4:0] */
2398static const char * const rt5665_tdm_adc_data_src[] = {
2399 "1234", "1243", "1324", "1342", "1432", "1423",
2400 "2134", "2143", "2314", "2341", "2431", "2413",
2401 "3124", "3142", "3214", "3241", "3412", "3421",
2402 "4123", "4132", "4213", "4231", "4312", "4321"
2403};
2404
2405static const SOC_ENUM_SINGLE_DECL(
2406 rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
2407 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2408
2409static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
2410 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2411
2412static const SOC_ENUM_SINGLE_DECL(
2413 rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
2414 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2415
2416static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
2417 SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
2418
2419/* Out Volume Switch */
2420static const struct snd_kcontrol_new monovol_switch =
2421 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
2422
2423static const struct snd_kcontrol_new outvol_l_switch =
2424 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
2425
2426static const struct snd_kcontrol_new outvol_r_switch =
2427 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
2428
2429/* Out Switch */
2430static const struct snd_kcontrol_new mono_switch =
2431 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
2432
2433static const struct snd_kcontrol_new hpo_switch =
2434 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
2435 RT5665_VOL_L_SFT, 1, 0);
2436
2437static const struct snd_kcontrol_new lout_l_switch =
2438 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
2439
2440static const struct snd_kcontrol_new lout_r_switch =
2441 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
2442
2443static const struct snd_kcontrol_new pdm_l_switch =
2444 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2445 RT5665_M_PDM1_L_SFT, 1, 1);
2446
2447static const struct snd_kcontrol_new pdm_r_switch =
2448 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2449 RT5665_M_PDM1_R_SFT, 1, 1);
2450
2451static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
2452 struct snd_kcontrol *kcontrol, int event)
2453{
2454 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2455
2456 switch (event) {
2457 case SND_SOC_DAPM_PRE_PMU:
2458 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2459 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2460 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2461 0x0);
2462 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0x10);
2463 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0x20);
2464 break;
2465
2466 case SND_SOC_DAPM_POST_PMD:
2467 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0);
2468 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0);
2469 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2470 0x40);
2471 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2472 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2473 break;
2474
2475 default:
2476 return 0;
2477 }
2478
2479 return 0;
2480
2481}
2482
2483static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
2484 struct snd_kcontrol *kcontrol, int event)
2485{
2486 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2487
2488 switch (event) {
2489 case SND_SOC_DAPM_PRE_PMU:
2490 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2491 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2492 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0003);
2493 break;
2494
2495 case SND_SOC_DAPM_POST_PMD:
2496 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0002);
2497 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2498 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2499 break;
2500
2501 default:
2502 return 0;
2503 }
2504
2505 return 0;
2506
2507}
2508
2509static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
2510 struct snd_kcontrol *kcontrol, int event)
2511{
2512 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2513
2514 switch (event) {
2515 case SND_SOC_DAPM_POST_PMU:
2516 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2517 RT5665_PUMP_EN, RT5665_PUMP_EN);
2518 break;
2519
2520 case SND_SOC_DAPM_PRE_PMD:
2521 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2522 RT5665_PUMP_EN, 0);
2523 break;
2524
2525 default:
2526 return 0;
2527 }
2528
2529 return 0;
2530
2531}
2532
2533static int set_dmic_power(struct snd_soc_dapm_widget *w,
2534 struct snd_kcontrol *kcontrol, int event)
2535{
2536 switch (event) {
2537 case SND_SOC_DAPM_POST_PMU:
2538 /*Add delay to avoid pop noise*/
2539 msleep(150);
2540 break;
2541
2542 default:
2543 return 0;
2544 }
2545
2546 return 0;
2547}
2548
2549static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
2550 struct snd_kcontrol *kcontrol, int event)
2551{
2552 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2553
2554 switch (event) {
2555 case SND_SOC_DAPM_PRE_PMU:
2556 switch (w->shift) {
2557 case RT5665_PWR_VREF1_BIT:
2558 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2559 RT5665_PWR_FV1, 0);
2560 break;
2561
2562 case RT5665_PWR_VREF2_BIT:
2563 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2564 RT5665_PWR_FV2, 0);
2565 break;
2566
2567 case RT5665_PWR_VREF3_BIT:
2568 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2569 RT5665_PWR_FV3, 0);
2570 break;
2571
2572 default:
2573 break;
2574 }
2575 break;
2576
2577 case SND_SOC_DAPM_POST_PMU:
2578 usleep_range(15000, 20000);
2579 switch (w->shift) {
2580 case RT5665_PWR_VREF1_BIT:
2581 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2582 RT5665_PWR_FV1, RT5665_PWR_FV1);
2583 break;
2584
2585 case RT5665_PWR_VREF2_BIT:
2586 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2587 RT5665_PWR_FV2, RT5665_PWR_FV2);
2588 break;
2589
2590 case RT5665_PWR_VREF3_BIT:
2591 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2592 RT5665_PWR_FV3, RT5665_PWR_FV3);
2593 break;
2594
2595 default:
2596 break;
2597 }
2598 break;
2599
2600 default:
2601 return 0;
2602 }
2603
2604 return 0;
2605}
2606
Bard Liao9b5d3862017-03-16 13:58:41 +0800[diff] [blame]2607static int rt5665_i2s_pin_event(struct snd_soc_dapm_widget *w,
2608 struct snd_kcontrol *kcontrol, int event)
2609{
2610 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2611 unsigned int val1, val2, mask1, mask2 = 0;
2612
2613 switch (w->shift) {
2614 case RT5665_PWR_I2S2_1_BIT:
2615 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2616 RT5665_GP4_PIN_MASK | RT5665_GP5_PIN_MASK;
2617 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2618 RT5665_GP4_PIN_DACDAT2_1 | RT5665_GP5_PIN_ADCDAT2_1;
2619 break;
2620 case RT5665_PWR_I2S2_2_BIT:
2621 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2622 RT5665_GP8_PIN_MASK;
2623 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2624 RT5665_GP8_PIN_DACDAT2_2;
2625 mask2 = RT5665_GP9_PIN_MASK;
2626 val2 = RT5665_GP9_PIN_ADCDAT2_2;
2627 break;
2628 case RT5665_PWR_I2S3_BIT:
2629 mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK |
2630 RT5665_GP8_PIN_MASK;
2631 val1 = RT5665_GP6_PIN_BCLK3 | RT5665_GP7_PIN_LRCK3 |
2632 RT5665_GP8_PIN_DACDAT3;
2633 mask2 = RT5665_GP9_PIN_MASK;
2634 val2 = RT5665_GP9_PIN_ADCDAT3;
2635 break;
2636 }
2637 switch (event) {
2638 case SND_SOC_DAPM_PRE_PMU:
2639 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_1, mask1, val1);
2640 if (mask2)
2641 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_2,
2642 mask2, val2);
2643 break;
2644 case SND_SOC_DAPM_POST_PMD:
2645 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_1, mask1, 0);
2646 if (mask2)
2647 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_2,
2648 mask2, 0);
2649 break;
2650 default:
2651 return 0;
2652 }
2653
2654 return 0;
2655}
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2656
2657static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
2658 SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
2659 NULL, 0),
2660 SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
2661 NULL, 0),
2662 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
2663 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
2664 SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
2665 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2666 SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
2667 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2668 SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
2669 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2670
2671 /* ASRC */
2672 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2673 RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
2674 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2675 RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
2676 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2677 RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
2678 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2679 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
2680 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2681 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
2682 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2683 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2684 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2685 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2686 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2687 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2688 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2689 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2690 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2691 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2692 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2693 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
2694 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2695 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
2696 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2697 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
2698 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2699 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
2700
2701 /* Input Side */
2702 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
2703 0, NULL, 0),
2704 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
2705 0, NULL, 0),
2706 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
2707 0, NULL, 0),
2708
2709 /* Input Lines */
2710 SND_SOC_DAPM_INPUT("DMIC L1"),
2711 SND_SOC_DAPM_INPUT("DMIC R1"),
2712 SND_SOC_DAPM_INPUT("DMIC L2"),
2713 SND_SOC_DAPM_INPUT("DMIC R2"),
2714
2715 SND_SOC_DAPM_INPUT("IN1P"),
2716 SND_SOC_DAPM_INPUT("IN1N"),
2717 SND_SOC_DAPM_INPUT("IN2P"),
2718 SND_SOC_DAPM_INPUT("IN2N"),
2719 SND_SOC_DAPM_INPUT("IN3P"),
2720 SND_SOC_DAPM_INPUT("IN3N"),
2721 SND_SOC_DAPM_INPUT("IN4P"),
2722 SND_SOC_DAPM_INPUT("IN4N"),
2723
2724 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2725 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2726
2727 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2728 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2729 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
2730 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2731 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2732 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2733
2734 /* Boost */
2735 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
2736 0, 0, NULL, 0),
2737 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
2738 0, 0, NULL, 0),
2739 SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
2740 0, 0, NULL, 0),
2741 SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
2742 0, 0, NULL, 0),
2743 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
2744 0, 0, NULL, 0),
2745 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
2746 RT5665_PWR_BST1_BIT, 0, NULL, 0),
2747 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
2748 RT5665_PWR_BST2_BIT, 0, NULL, 0),
2749 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
2750 RT5665_PWR_BST3_BIT, 0, NULL, 0),
2751 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
2752 RT5665_PWR_BST4_BIT, 0, NULL, 0),
2753 SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
2754 RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
2755 SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
2756 RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
2757 SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
2758 RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
2759 SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
2760 RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
2761 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
2762 RT5665_PWR_CBJ_BIT, 0, NULL, 0),
2763
2764
2765 /* Input Volume */
2766 SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
2767 0, NULL, 0),
2768 SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
2769 0, NULL, 0),
2770
2771 /* REC Mixer */
2772 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
2773 ARRAY_SIZE(rt5665_rec1_l_mix)),
2774 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
2775 ARRAY_SIZE(rt5665_rec1_r_mix)),
2776 SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
2777 ARRAY_SIZE(rt5665_rec2_l_mix)),
2778 SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
2779 ARRAY_SIZE(rt5665_rec2_r_mix)),
2780 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
2781 RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
2782 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
2783 RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
2784 SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
2785 RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
2786 SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
2787 RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
2788
2789 /* ADCs */
2790 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2791 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2792 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2793 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2794
2795 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
2796 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
2797 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
2798 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
2799 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
2800 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
2801 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
2802 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
2803 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
2804 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
2805 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
2806 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
2807
2808 /* ADC Mux */
2809 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2810 &rt5665_sto1_dmic_mux),
2811 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2812 &rt5665_sto1_dmic_mux),
2813 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2814 &rt5665_sto1_adc1l_mux),
2815 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2816 &rt5665_sto1_adc1r_mux),
2817 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2818 &rt5665_sto1_adc2l_mux),
2819 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2820 &rt5665_sto1_adc2r_mux),
2821 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2822 &rt5665_sto1_adcl_mux),
2823 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2824 &rt5665_sto1_adcr_mux),
2825 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2826 &rt5665_sto1_dd_l_mux),
2827 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2828 &rt5665_sto1_dd_r_mux),
2829 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2830 &rt5665_mono_adc_l2_mux),
2831 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2832 &rt5665_mono_adc_r2_mux),
2833 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2834 &rt5665_mono_adc_l1_mux),
2835 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2836 &rt5665_mono_adc_r1_mux),
2837 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2838 &rt5665_mono_dmic_l_mux),
2839 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2840 &rt5665_mono_dmic_r_mux),
2841 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2842 &rt5665_mono_adc_l_mux),
2843 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2844 &rt5665_mono_adc_r_mux),
2845 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2846 &rt5665_mono_dd_l_mux),
2847 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2848 &rt5665_mono_dd_r_mux),
2849 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2850 &rt5665_sto2_dmic_mux),
2851 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2852 &rt5665_sto2_dmic_mux),
2853 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2854 &rt5665_sto2_adc1l_mux),
2855 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2856 &rt5665_sto2_adc1r_mux),
2857 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2858 &rt5665_sto2_adc2l_mux),
2859 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2860 &rt5665_sto2_adc2r_mux),
2861 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2862 &rt5665_sto2_adcl_mux),
2863 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2864 &rt5665_sto2_adcr_mux),
2865 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2866 &rt5665_sto2_dd_l_mux),
2867 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2868 &rt5665_sto2_dd_r_mux),
2869 /* ADC Mixer */
2870 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
2871 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
2872 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
2873 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
2874 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
2875 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
2876 ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
2877 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
2878 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
2879 ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
2880 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
2881 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
2882 ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
2883 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
2884 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
2885 ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
2886 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
2887 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2888 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
2889 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
2890 ARRAY_SIZE(rt5665_mono_adc_l_mix)),
2891 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
2892 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2893 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
2894 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
2895 ARRAY_SIZE(rt5665_mono_adc_r_mix)),
2896
2897 /* ADC PGA */
2898 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2899 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2900 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2901
2902 /* Digital Interface */
2903 SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
2904 0, NULL, 0),
2905 SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
2906 0, NULL, 0),
2907 SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
Bard Liao9b5d3862017-03-16 13:58:41 +0800[diff] [blame]2908 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2909 SND_SOC_DAPM_POST_PMD),
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2910 SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
Bard Liao9b5d3862017-03-16 13:58:41 +0800[diff] [blame]2911 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2912 SND_SOC_DAPM_POST_PMD),
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2913 SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
Bard Liao9b5d3862017-03-16 13:58:41 +0800[diff] [blame]2914 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2915 SND_SOC_DAPM_POST_PMD),
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2916 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2917 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2918 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2919 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2920 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2921 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2922 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2923 SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2924 SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2925
2926 SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2927 SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2928 SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2929 SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2930 SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2931 SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2932 SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2933 SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2934
2935 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2936 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2937 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2938 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2939
2940 /* Digital Interface Select */
2941 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2942 &rt5665_if1_1_adc1_mux),
2943 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2944 &rt5665_if1_1_adc2_mux),
2945 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2946 &rt5665_if1_1_adc3_mux),
2947 SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2948 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2949 &rt5665_if1_2_adc1_mux),
2950 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2951 &rt5665_if1_2_adc2_mux),
2952 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2953 &rt5665_if1_2_adc3_mux),
2954 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2955 &rt5665_if1_2_adc4_mux),
2956 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2957 &rt5665_tdm1_adc_mux),
2958 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2959 &rt5665_tdm1_adc_mux),
2960 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2961 &rt5665_tdm1_adc_mux),
2962 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2963 &rt5665_tdm1_adc_mux),
2964 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2965 &rt5665_tdm2_adc_mux),
2966 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2967 &rt5665_tdm2_adc_mux),
2968 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2969 &rt5665_tdm2_adc_mux),
2970 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2971 &rt5665_tdm2_adc_mux),
2972 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
2973 &rt5665_if2_1_adc_in_mux),
2974 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
2975 &rt5665_if2_2_adc_in_mux),
2976 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2977 &rt5665_if3_adc_in_mux),
2978 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2979 &rt5665_if1_1_01_adc_swap_mux),
2980 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2981 &rt5665_if1_1_01_adc_swap_mux),
2982 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2983 &rt5665_if1_1_23_adc_swap_mux),
2984 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2985 &rt5665_if1_1_23_adc_swap_mux),
2986 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2987 &rt5665_if1_1_45_adc_swap_mux),
2988 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2989 &rt5665_if1_1_45_adc_swap_mux),
2990 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2991 &rt5665_if1_1_67_adc_swap_mux),
2992 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2993 &rt5665_if1_1_67_adc_swap_mux),
2994 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2995 &rt5665_if1_2_01_adc_swap_mux),
2996 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2997 &rt5665_if1_2_01_adc_swap_mux),
2998 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2999 &rt5665_if1_2_23_adc_swap_mux),
3000 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3001 &rt5665_if1_2_23_adc_swap_mux),
3002 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3003 &rt5665_if1_2_45_adc_swap_mux),
3004 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3005 &rt5665_if1_2_45_adc_swap_mux),
3006 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3007 &rt5665_if1_2_67_adc_swap_mux),
3008 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3009 &rt5665_if1_2_67_adc_swap_mux),
3010 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3011 &rt5665_if2_1_dac_swap_mux),
3012 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3013 &rt5665_if2_1_adc_swap_mux),
3014 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3015 &rt5665_if2_2_dac_swap_mux),
3016 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3017 &rt5665_if2_2_adc_swap_mux),
3018 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3019 &rt5665_if3_dac_swap_mux),
3020 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3021 &rt5665_if3_adc_swap_mux),
3022
3023 /* Audio Interface */
3024 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
3025 0, SND_SOC_NOPM, 0, 0),
3026 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
3027 1, SND_SOC_NOPM, 0, 0),
3028 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
3029 2, SND_SOC_NOPM, 0, 0),
3030 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
3031 3, SND_SOC_NOPM, 0, 0),
3032 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
3033 4, SND_SOC_NOPM, 0, 0),
3034 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
3035 5, SND_SOC_NOPM, 0, 0),
3036 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
3037 6, SND_SOC_NOPM, 0, 0),
3038 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
3039 7, SND_SOC_NOPM, 0, 0),
3040 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
3041 0, SND_SOC_NOPM, 0, 0),
3042 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
3043 1, SND_SOC_NOPM, 0, 0),
3044 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
3045 2, SND_SOC_NOPM, 0, 0),
3046 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
3047 3, SND_SOC_NOPM, 0, 0),
3048 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
3049 4, SND_SOC_NOPM, 0, 0),
3050 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
3051 5, SND_SOC_NOPM, 0, 0),
3052 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
3053 6, SND_SOC_NOPM, 0, 0),
3054 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
3055 7, SND_SOC_NOPM, 0, 0),
3056 SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
3057 0, SND_SOC_NOPM, 0, 0),
3058 SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
3059 0, SND_SOC_NOPM, 0, 0),
3060 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
3061 0, SND_SOC_NOPM, 0, 0),
3062 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
3063 0, SND_SOC_NOPM, 0, 0),
3064 SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
3065 0, SND_SOC_NOPM, 0, 0),
3066 SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
3067 0, SND_SOC_NOPM, 0, 0),
3068 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
3069 0, SND_SOC_NOPM, 0, 0),
3070
3071 /* Output Side */
3072 /* DAC mixer before sound effect */
3073 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3074 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
3075 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3076 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
3077
3078 /* DAC channel Mux */
3079 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3080 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3081 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3082 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3083 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3084 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3085
3086 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
3087 &rt5665_alg_dac_l1_mux),
3088 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
3089 &rt5665_alg_dac_r1_mux),
3090 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
3091 &rt5665_alg_dac_l2_mux),
3092 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
3093 &rt5665_alg_dac_r2_mux),
3094
3095 /* DAC Mixer */
3096 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
3097 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
3098 SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
3099 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
3100 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
3101 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
3102 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
3103 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
3104 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
3105 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
3106 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
3107 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
3108 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
3109 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
3110 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
3111 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
3112 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3113 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
3114 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3115 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
3116 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
3117 &rt5665_dig_dac_mixl_mux),
3118 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
3119 &rt5665_dig_dac_mixr_mux),
3120
3121 /* DACs */
3122 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
3123 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
3124
3125 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
3126 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
3127 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
3128 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
3129 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
3130 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
3131 SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3132
3133 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
3134 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
3135 SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
3136 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
3137
3138 /* OUT Mixer */
3139 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
3140 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
3141 SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
3142 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
3143 SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
3144 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
3145
3146 /* Output Volume */
3147 SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
3148 &monovol_switch),
3149 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
3150 &outvol_l_switch),
3151 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
3152 &outvol_r_switch),
3153
3154 /* MONO/HPO/LOUT */
3155 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
3156 ARRAY_SIZE(rt5665_mono_mix)),
3157 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
3158 ARRAY_SIZE(rt5665_lout_l_mix)),
3159 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
3160 ARRAY_SIZE(rt5665_lout_r_mix)),
3161 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
3162 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
3163 SND_SOC_DAPM_PRE_PMU),
3164 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
3165 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3166 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
3167 RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
3168 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
3169 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3170
3171 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
3172 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
3173 SND_SOC_DAPM_POST_PMD),
3174
3175 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
3176 &mono_switch),
3177 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
3178 &hpo_switch),
3179 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
3180 &lout_l_switch),
3181 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
3182 &lout_r_switch),
3183 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
3184 &pdm_l_switch),
3185 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
3186 &pdm_r_switch),
3187
3188 /* PDM */
3189 SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
3190 RT5665_PWR_PDM1_BIT, 0, NULL, 0),
3191 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3192 0, 1, &rt5665_pdm_l_mux),
3193 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3194 0, 1, &rt5665_pdm_r_mux),
3195
3196 /* CLK DET */
3197 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
3198 0, NULL, 0),
3199 SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
3200 0, NULL, 0),
3201 SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
3202 0, NULL, 0),
3203 SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
3204 0, NULL, 0),
3205 SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
3206 0, NULL, 0),
3207
3208 /* Output Lines */
3209 SND_SOC_DAPM_OUTPUT("HPOL"),
3210 SND_SOC_DAPM_OUTPUT("HPOR"),
3211 SND_SOC_DAPM_OUTPUT("LOUTL"),
3212 SND_SOC_DAPM_OUTPUT("LOUTR"),
3213 SND_SOC_DAPM_OUTPUT("MONOOUT"),
3214 SND_SOC_DAPM_OUTPUT("PDML"),
3215 SND_SOC_DAPM_OUTPUT("PDMR"),
3216};
3217
3218static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
3219 /*PLL*/
3220 {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3221 {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3222 {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3223 {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3224 {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3225 {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3226 {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3227 {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3228
3229 /*ASRC*/
3230 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
3231 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3232 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3233 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3234 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3235 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3236 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
Bard Liao09b50c32017-03-08 19:05:32 +0800[diff] [blame]3237 {"I2S1 ASRC", NULL, "CLKDET"},
3238 {"I2S2 ASRC", NULL, "CLKDET"},
3239 {"I2S3 ASRC", NULL, "CLKDET"},
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]3240
3241 /*Vref*/
3242 {"Mic Det Power", NULL, "Vref2"},
3243 {"MICBIAS1", NULL, "Vref1"},
3244 {"MICBIAS1", NULL, "Vref2"},
3245 {"MICBIAS2", NULL, "Vref1"},
3246 {"MICBIAS2", NULL, "Vref2"},
3247 {"MICBIAS3", NULL, "Vref1"},
3248 {"MICBIAS3", NULL, "Vref2"},
3249
3250 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3251 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3252 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3253 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3254 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3255 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3256
3257 {"I2S1_1", NULL, "I2S1 ASRC"},
3258 {"I2S1_2", NULL, "I2S1 ASRC"},
3259 {"I2S2_1", NULL, "I2S2 ASRC"},
3260 {"I2S2_2", NULL, "I2S2 ASRC"},
3261 {"I2S3", NULL, "I2S3 ASRC"},
3262
3263 {"CLKDET SYS", NULL, "CLKDET"},
3264 {"CLKDET HP", NULL, "CLKDET"},
3265 {"CLKDET MONO", NULL, "CLKDET"},
3266 {"CLKDET LOUT", NULL, "CLKDET"},
3267
3268 {"IN1P", NULL, "LDO2"},
3269 {"IN2P", NULL, "LDO2"},
3270 {"IN3P", NULL, "LDO2"},
3271 {"IN4P", NULL, "LDO2"},
3272
3273 {"DMIC1", NULL, "DMIC L1"},
3274 {"DMIC1", NULL, "DMIC R1"},
3275 {"DMIC2", NULL, "DMIC L2"},
3276 {"DMIC2", NULL, "DMIC R2"},
3277
3278 {"BST1", NULL, "IN1P"},
3279 {"BST1", NULL, "IN1N"},
3280 {"BST1", NULL, "BST1 Power"},
3281 {"BST1", NULL, "BST1P Power"},
3282 {"BST2", NULL, "IN2P"},
3283 {"BST2", NULL, "IN2N"},
3284 {"BST2", NULL, "BST2 Power"},
3285 {"BST2", NULL, "BST2P Power"},
3286 {"BST3", NULL, "IN3P"},
3287 {"BST3", NULL, "IN3N"},
3288 {"BST3", NULL, "BST3 Power"},
3289 {"BST3", NULL, "BST3P Power"},
3290 {"BST4", NULL, "IN4P"},
3291 {"BST4", NULL, "IN4N"},
3292 {"BST4", NULL, "BST4 Power"},
3293 {"BST4", NULL, "BST4P Power"},
3294 {"BST1 CBJ", NULL, "IN1P"},
3295 {"BST1 CBJ", NULL, "IN1N"},
3296 {"BST1 CBJ", NULL, "CBJ Power"},
3297 {"CBJ Power", NULL, "Vref2"},
3298
3299 {"INL VOL", NULL, "IN3P"},
3300 {"INR VOL", NULL, "IN3N"},
3301
3302 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
3303 {"RECMIX1L", "INL Switch", "INL VOL"},
3304 {"RECMIX1L", "INR Switch", "INR VOL"},
3305 {"RECMIX1L", "BST4 Switch", "BST4"},
3306 {"RECMIX1L", "BST3 Switch", "BST3"},
3307 {"RECMIX1L", "BST2 Switch", "BST2"},
3308 {"RECMIX1L", "BST1 Switch", "BST1"},
3309 {"RECMIX1L", NULL, "RECMIX1L Power"},
3310
3311 {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
3312 {"RECMIX1R", "INR Switch", "INR VOL"},
3313 {"RECMIX1R", "BST4 Switch", "BST4"},
3314 {"RECMIX1R", "BST3 Switch", "BST3"},
3315 {"RECMIX1R", "BST2 Switch", "BST2"},
3316 {"RECMIX1R", "BST1 Switch", "BST1"},
3317 {"RECMIX1R", NULL, "RECMIX1R Power"},
3318
3319 {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
3320 {"RECMIX2L", "INL Switch", "INL VOL"},
3321 {"RECMIX2L", "INR Switch", "INR VOL"},
3322 {"RECMIX2L", "BST4 Switch", "BST4"},
3323 {"RECMIX2L", "BST3 Switch", "BST3"},
3324 {"RECMIX2L", "BST2 Switch", "BST2"},
3325 {"RECMIX2L", "BST1 Switch", "BST1"},
3326 {"RECMIX2L", NULL, "RECMIX2L Power"},
3327
3328 {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
3329 {"RECMIX2R", "INL Switch", "INL VOL"},
3330 {"RECMIX2R", "INR Switch", "INR VOL"},
3331 {"RECMIX2R", "BST4 Switch", "BST4"},
3332 {"RECMIX2R", "BST3 Switch", "BST3"},
3333 {"RECMIX2R", "BST2 Switch", "BST2"},
3334 {"RECMIX2R", "BST1 Switch", "BST1"},
3335 {"RECMIX2R", NULL, "RECMIX2R Power"},
3336
3337 {"ADC1 L", NULL, "RECMIX1L"},
3338 {"ADC1 L", NULL, "ADC1 L Power"},
3339 {"ADC1 L", NULL, "ADC1 clock"},
3340 {"ADC1 R", NULL, "RECMIX1R"},
3341 {"ADC1 R", NULL, "ADC1 R Power"},
3342 {"ADC1 R", NULL, "ADC1 clock"},
3343
3344 {"ADC2 L", NULL, "RECMIX2L"},
3345 {"ADC2 L", NULL, "ADC2 L Power"},
3346 {"ADC2 L", NULL, "ADC2 clock"},
3347 {"ADC2 R", NULL, "RECMIX2R"},
3348 {"ADC2 R", NULL, "ADC2 R Power"},
3349 {"ADC2 R", NULL, "ADC2 clock"},
3350
3351 {"DMIC L1", NULL, "DMIC CLK"},
3352 {"DMIC L1", NULL, "DMIC1 Power"},
3353 {"DMIC R1", NULL, "DMIC CLK"},
3354 {"DMIC R1", NULL, "DMIC1 Power"},
3355 {"DMIC L2", NULL, "DMIC CLK"},
3356 {"DMIC L2", NULL, "DMIC2 Power"},
3357 {"DMIC R2", NULL, "DMIC CLK"},
3358 {"DMIC R2", NULL, "DMIC2 Power"},
3359
3360 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3361 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3362
3363 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3364 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3365
3366 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3367 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3368
3369 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3370 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3371
3372 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3373 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3374
3375 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3376 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3377
3378 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3379 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3380 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3381 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3382 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3383 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3384 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3385 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3386
3387 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3388 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3389
3390 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3391 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3392
3393 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3394 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3395 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3396 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3397
3398 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3399 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3400 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3401 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3402
3403 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3404 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3405 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3406 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3407
3408 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3409 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3410 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3411 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3412
3413 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3414 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3415
3416 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3417 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3418
3419 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3420 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3421 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3422 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3423
3424 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3425 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3426 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3427 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3428
3429 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3430 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3431 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3432 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3433 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3434 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3435
3436 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3437 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3438
3439 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3440 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3441
3442 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3443 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3444 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3445 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3446
3447 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3448 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3449 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3450 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3451
3452 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3453 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3454 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
3455
3456 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3457 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3458 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
3459
3460 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3461 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3462 {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
3463
3464 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3465 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3466 {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
3467
3468 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3469 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3470 {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
3471
3472 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3473 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3474 {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
3475
3476 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
3477 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
3478 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
3479 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
3480 {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
3481 {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
3482
3483 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3484 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3485 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3486 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3487 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3488 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3489 {"IF1_1_ADC4", NULL, "DAC1 MIX"},
3490
3491 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3492 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3493 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3494 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3495 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3496 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3497 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3498 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3499
3500 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3501 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3502 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3503 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3504 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3505 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3506 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3507 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3508 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3509 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3510 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3511 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3512 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3513 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3514 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3515 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3516 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3517 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3518 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3519 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3520 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3521 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3522 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3523 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3524 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3525
3526 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3527 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3528 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3529 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3530 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3531 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3532 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3533 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3534 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3535 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3536 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3537 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3538 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3539 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3540 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3541 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3542 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3543 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3544 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3545 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3546 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3547 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3548 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3549 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3550 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3551
3552 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3553 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3554 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3555 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3556 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3557 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3558 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3559 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3560 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3561 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3562 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3563 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3564 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3565 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3566 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3567 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3568 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3569 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3570 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3571 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3572 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3573 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3574 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3575 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3576 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3577
3578 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3579 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3580 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3581 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3582 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3583 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3584 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3585 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3586 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3587 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3588 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3589 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3590 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3591 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3592 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3593 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3594 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3595 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3596 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3597 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3598 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3599 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3600 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3601 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3602 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3603
3604
3605 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3606 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3607 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3608 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3609 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3610 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3611 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3612 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3613 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3614 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3615 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3616 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3617 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3618 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3619 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3620 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3621 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3622 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3623 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3624 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3625 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3626 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3627 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3628 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3629 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3630
3631 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3632 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3633 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3634 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3635 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3636 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3637 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3638 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3639 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3640 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3641 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3642 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3643 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3644 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3645 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3646 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3647 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3648 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3649 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3650 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3651 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3652 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3653 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3654 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3655 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3656
3657 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3658 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3659 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3660 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3661 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3662 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3663 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3664 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3665 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3666 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3667 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3668 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3669 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3670 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3671 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3672 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3673 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3674 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3675 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3676 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3677 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3678 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3679 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3680 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3681 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3682
3683 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3684 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3685 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3686 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3687 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3688 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3689 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3690 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3691 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3692 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3693 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3694 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3695 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3696 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3697 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3698 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3699 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3700 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3701 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3702 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3703 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3704 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3705 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3706 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3707 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3708
3709 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3710 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3711 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3712 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3713 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3714 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3715 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3716 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3717 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3718 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3719 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3720 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3721 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3722 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3723 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3724 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3725 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3726 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3727 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3728 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3729 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3730 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3731 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3732 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3733 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3734 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3735 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3736 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3737 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3738 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3739 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3740 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3741
3742 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3743 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3744 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3745 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3746 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3747 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3748 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3749 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3750 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3751 {"IF2_1 ADC", NULL, "I2S2_1"},
3752
3753 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3754 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3755 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3756 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3757 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3758 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3759 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3760 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3761 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3762 {"IF2_2 ADC", NULL, "I2S2_2"},
3763
3764 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3765 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3766 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3767 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3768 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3769 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3770 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3771 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3772 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3773 {"IF3 ADC", NULL, "I2S3"},
3774
3775 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3776 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3777 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3778 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3779 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3780 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3781 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3782 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3783 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3784 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3785 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3786 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3787 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3788 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3789 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3790 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3791 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3792 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3793 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3794 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3795 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3796 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3797 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3798 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3799 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3800 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3801 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3802 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3803 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3804 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3805 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3806
3807 {"IF1 DAC1", NULL, "AIF1RX"},
3808 {"IF1 DAC2", NULL, "AIF1RX"},
3809 {"IF1 DAC3", NULL, "AIF1RX"},
3810 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3811 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3812 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3813 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3814 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3815 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3816 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3817 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3818 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3819 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3820 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3821 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3822 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3823 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3824 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3825
3826 {"IF1 DAC1", NULL, "I2S1_1"},
3827 {"IF1 DAC2", NULL, "I2S1_1"},
3828 {"IF1 DAC3", NULL, "I2S1_1"},
3829 {"IF2_1 DAC", NULL, "I2S2_1"},
3830 {"IF2_2 DAC", NULL, "I2S2_2"},
3831 {"IF3 DAC", NULL, "I2S3"},
3832
3833 {"IF1 DAC1 L", NULL, "IF1 DAC1"},
3834 {"IF1 DAC1 R", NULL, "IF1 DAC1"},
3835 {"IF1 DAC2 L", NULL, "IF1 DAC2"},
3836 {"IF1 DAC2 R", NULL, "IF1 DAC2"},
3837 {"IF1 DAC3 L", NULL, "IF1 DAC3"},
3838 {"IF1 DAC3 R", NULL, "IF1 DAC3"},
3839 {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
3840 {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
3841 {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
3842 {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
3843 {"IF3 DAC L", NULL, "IF3 DAC"},
3844 {"IF3 DAC R", NULL, "IF3 DAC"},
3845
3846 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3847 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3848 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3849 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3850 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3851
3852 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3853 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3854 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3855 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3856 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3857
3858 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
3859 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3860 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
3861 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3862
3863 {"DAC1 MIX", NULL, "DAC1 MIXL"},
3864 {"DAC1 MIX", NULL, "DAC1 MIXR"},
3865
3866 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3867 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3868 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3869 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3870 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3871 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3872
3873 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3874 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3875 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3876 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3877 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3878 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3879
3880 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3881 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3882 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3883 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3884 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3885 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3886
3887 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3888 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3889 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3890 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3891 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3892 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3893
3894 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3895 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3896 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3897 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3898
3899 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3900 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3901 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3902 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3903
3904 {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3905 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3906 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3907
3908 {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3909 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3910 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3911
3912 {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3913 {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3914 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3915 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3916 {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3917 {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3918 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3919 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3920
3921 {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3922 {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
3923 {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
3924 {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3925 {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
3926 {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
3927
3928 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
3929 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3930 {"DAC L1 Source", "DMIC1", "DMIC L1"},
3931 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
3932 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3933 {"DAC R1 Source", "DMIC1", "DMIC R1"},
3934
3935 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3936 {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
3937 {"DAC L2 Source", NULL, "DAC L2 Power"},
3938 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3939 {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
3940 {"DAC R2 Source", NULL, "DAC R2 Power"},
3941
3942 {"DAC L1", NULL, "DAC L1 Source"},
3943 {"DAC R1", NULL, "DAC R1 Source"},
3944 {"DAC L2", NULL, "DAC L2 Source"},
3945 {"DAC R2", NULL, "DAC R2 Source"},
3946
3947 {"DAC L1", NULL, "DAC 1 Clock"},
3948 {"DAC R1", NULL, "DAC 1 Clock"},
3949 {"DAC L2", NULL, "DAC 2 Clock"},
3950 {"DAC R2", NULL, "DAC 2 Clock"},
3951
3952 {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
3953 {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
3954 {"MONOVOL MIX", "BST1 Switch", "BST1"},
3955 {"MONOVOL MIX", "BST2 Switch", "BST2"},
3956 {"MONOVOL MIX", "BST3 Switch", "BST3"},
3957
3958 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
3959 {"OUT MIXL", "INL Switch", "INL VOL"},
3960 {"OUT MIXL", "BST1 Switch", "BST1"},
3961 {"OUT MIXL", "BST2 Switch", "BST2"},
3962 {"OUT MIXL", "BST3 Switch", "BST3"},
3963 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
3964 {"OUT MIXR", "INR Switch", "INR VOL"},
3965 {"OUT MIXR", "BST2 Switch", "BST2"},
3966 {"OUT MIXR", "BST3 Switch", "BST3"},
3967 {"OUT MIXR", "BST4 Switch", "BST4"},
3968
3969 {"MONOVOL", "Switch", "MONOVOL MIX"},
3970 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
3971 {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
3972 {"Mono Amp", NULL, "Mono MIX"},
3973 {"Mono Amp", NULL, "Vref2"},
Bard Liao8f365312017-03-08 19:05:31 +0800[diff] [blame]3974 {"Mono Amp", NULL, "Vref3"},
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]3975 {"Mono Amp", NULL, "CLKDET SYS"},
3976 {"Mono Amp", NULL, "CLKDET MONO"},
3977 {"Mono Playback", "Switch", "Mono Amp"},
3978 {"MONOOUT", NULL, "Mono Playback"},
3979
3980 {"HP Amp", NULL, "DAC L1"},
3981 {"HP Amp", NULL, "DAC R1"},
3982 {"HP Amp", NULL, "Charge Pump"},
3983 {"HP Amp", NULL, "CLKDET SYS"},
3984 {"HP Amp", NULL, "CLKDET HP"},
3985 {"HP Amp", NULL, "CBJ Power"},
3986 {"HP Amp", NULL, "Vref2"},
3987 {"HPO Playback", "Switch", "HP Amp"},
3988 {"HPOL", NULL, "HPO Playback"},
3989 {"HPOR", NULL, "HPO Playback"},
3990
3991 {"OUTVOL L", "Switch", "OUT MIXL"},
3992 {"OUTVOL R", "Switch", "OUT MIXR"},
3993 {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
3994 {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
3995 {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
3996 {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
3997 {"LOUT Amp", NULL, "LOUT L MIX"},
3998 {"LOUT Amp", NULL, "LOUT R MIX"},
3999 {"LOUT Amp", NULL, "Vref1"},
4000 {"LOUT Amp", NULL, "Vref2"},
4001 {"LOUT Amp", NULL, "CLKDET SYS"},
4002 {"LOUT Amp", NULL, "CLKDET LOUT"},
4003 {"LOUT L Playback", "Switch", "LOUT Amp"},
4004 {"LOUT R Playback", "Switch", "LOUT Amp"},
4005 {"LOUTL", NULL, "LOUT L Playback"},
4006 {"LOUTR", NULL, "LOUT R Playback"},
4007
4008 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
4009 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
4010 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
4011 {"PDM L Mux", NULL, "PDM Power"},
4012 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
4013 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
4014 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
4015 {"PDM R Mux", NULL, "PDM Power"},
4016 {"PDM L Playback", "Switch", "PDM L Mux"},
4017 {"PDM R Playback", "Switch", "PDM R Mux"},
4018 {"PDML", NULL, "PDM L Playback"},
4019 {"PDMR", NULL, "PDM R Playback"},
4020};
4021
Bard Liao948059d2017-03-08 19:05:36 +0800[diff] [blame]4022static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4023 unsigned int rx_mask, int slots, int slot_width)
4024{
4025 struct snd_soc_codec *codec = dai->codec;
4026 unsigned int val = 0;
4027
4028 if (rx_mask || tx_mask)
4029 val |= RT5665_I2S1_MODE_TDM;
4030
4031 switch (slots) {
4032 case 4:
4033 val |= RT5665_TDM_IN_CH_4;
4034 val |= RT5665_TDM_OUT_CH_4;
4035 break;
4036 case 6:
4037 val |= RT5665_TDM_IN_CH_6;
4038 val |= RT5665_TDM_OUT_CH_6;
4039 break;
4040 case 8:
4041 val |= RT5665_TDM_IN_CH_8;
4042 val |= RT5665_TDM_OUT_CH_8;
4043 break;
4044 case 2:
4045 break;
4046 default:
4047 return -EINVAL;
4048 }
4049
4050 switch (slot_width) {
4051 case 20:
4052 val |= RT5665_TDM_IN_LEN_20;
4053 val |= RT5665_TDM_OUT_LEN_20;
4054 break;
4055 case 24:
4056 val |= RT5665_TDM_IN_LEN_24;
4057 val |= RT5665_TDM_OUT_LEN_24;
4058 break;
4059 case 32:
4060 val |= RT5665_TDM_IN_LEN_32;
4061 val |= RT5665_TDM_OUT_LEN_32;
4062 break;
4063 case 16:
4064 break;
4065 default:
4066 return -EINVAL;
4067 }
4068
4069 snd_soc_update_bits(codec, RT5665_TDM_CTRL_1,
4070 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
4071 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
4072 RT5665_TDM_OUT_LEN_MASK, val);
4073
4074 return 0;
4075}
4076
4077
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4078static int rt5665_hw_params(struct snd_pcm_substream *substream,
4079 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4080{
4081 struct snd_soc_codec *codec = dai->codec;
4082 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
Bard Liao17febfa2017-03-20 10:20:54 +0800[diff] [blame^]4083 unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4084 int pre_div, frame_size;
4085
4086 rt5665->lrck[dai->id] = params_rate(params);
4087 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
4088 if (pre_div < 0) {
4089 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
4090 rt5665->lrck[dai->id], dai->id);
4091 return -EINVAL;
4092 }
4093 frame_size = snd_soc_params_to_frame_size(params);
4094 if (frame_size < 0) {
4095 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4096 return -EINVAL;
4097 }
4098
4099 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
4100 rt5665->lrck[dai->id], pre_div, dai->id);
4101
4102 switch (params_width(params)) {
4103 case 16:
4104 val_bits = 0x0100;
4105 break;
4106 case 20:
4107 val_len |= RT5665_I2S_DL_20;
4108 val_bits = 0x1300;
4109 break;
4110 case 24:
4111 val_len |= RT5665_I2S_DL_24;
4112 val_bits = 0x2500;
4113 break;
4114 case 8:
4115 val_len |= RT5665_I2S_DL_8;
4116 break;
4117 default:
4118 return -EINVAL;
4119 }
4120
4121 switch (dai->id) {
4122 case RT5665_AIF1_1:
4123 case RT5665_AIF1_2:
Bard Liao948059d2017-03-08 19:05:36 +0800[diff] [blame]4124 if (params_channels(params) > 2)
4125 rt5665_set_tdm_slot(dai, 0xf, 0xf,
4126 params_channels(params), params_width(params));
Bard Liao17febfa2017-03-20 10:20:54 +0800[diff] [blame^]4127 reg_clk = RT5665_ADDA_CLK_1;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4128 mask_clk = RT5665_I2S_PD1_MASK;
4129 val_clk = pre_div << RT5665_I2S_PD1_SFT;
4130 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4131 RT5665_I2S_DL_MASK, val_len);
4132 break;
4133 case RT5665_AIF2_1:
4134 case RT5665_AIF2_2:
Bard Liao17febfa2017-03-20 10:20:54 +0800[diff] [blame^]4135 reg_clk = RT5665_ADDA_CLK_2;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4136 mask_clk = RT5665_I2S_PD2_MASK;
4137 val_clk = pre_div << RT5665_I2S_PD2_SFT;
4138 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4139 RT5665_I2S_DL_MASK, val_len);
4140 break;
4141 case RT5665_AIF3:
Bard Liao17febfa2017-03-20 10:20:54 +0800[diff] [blame^]4142 reg_clk = RT5665_ADDA_CLK_2;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4143 mask_clk = RT5665_I2S_PD3_MASK;
4144 val_clk = pre_div << RT5665_I2S_PD3_SFT;
4145 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4146 RT5665_I2S_DL_MASK, val_len);
4147 break;
4148 default:
4149 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4150 return -EINVAL;
4151 }
4152
Bard Liao17febfa2017-03-20 10:20:54 +0800[diff] [blame^]4153 snd_soc_update_bits(codec, reg_clk, mask_clk, val_clk);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4154 snd_soc_update_bits(codec, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
4155
4156 switch (rt5665->lrck[dai->id]) {
4157 case 192000:
4158 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4159 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4160 RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
4161 break;
4162 case 96000:
4163 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4164 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4165 RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
4166 break;
4167 default:
4168 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4169 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4170 RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
4171 break;
4172 }
4173
4174 return 0;
4175}
4176
4177static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4178{
4179 struct snd_soc_codec *codec = dai->codec;
4180 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4181 unsigned int reg_val = 0;
4182
4183 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4184 case SND_SOC_DAIFMT_CBM_CFM:
4185 rt5665->master[dai->id] = 1;
4186 break;
4187 case SND_SOC_DAIFMT_CBS_CFS:
4188 reg_val |= RT5665_I2S_MS_S;
4189 rt5665->master[dai->id] = 0;
4190 break;
4191 default:
4192 return -EINVAL;
4193 }
4194
4195 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4196 case SND_SOC_DAIFMT_NB_NF:
4197 break;
4198 case SND_SOC_DAIFMT_IB_NF:
4199 reg_val |= RT5665_I2S_BP_INV;
4200 break;
4201 default:
4202 return -EINVAL;
4203 }
4204
4205 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4206 case SND_SOC_DAIFMT_I2S:
4207 break;
4208 case SND_SOC_DAIFMT_LEFT_J:
4209 reg_val |= RT5665_I2S_DF_LEFT;
4210 break;
4211 case SND_SOC_DAIFMT_DSP_A:
4212 reg_val |= RT5665_I2S_DF_PCM_A;
4213 break;
4214 case SND_SOC_DAIFMT_DSP_B:
4215 reg_val |= RT5665_I2S_DF_PCM_B;
4216 break;
4217 default:
4218 return -EINVAL;
4219 }
4220
4221 switch (dai->id) {
4222 case RT5665_AIF1_1:
4223 case RT5665_AIF1_2:
4224 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4225 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4226 RT5665_I2S_DF_MASK, reg_val);
4227 break;
4228 case RT5665_AIF2_1:
4229 case RT5665_AIF2_2:
4230 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4231 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4232 RT5665_I2S_DF_MASK, reg_val);
4233 break;
4234 case RT5665_AIF3:
4235 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4236 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4237 RT5665_I2S_DF_MASK, reg_val);
4238 break;
4239 default:
4240 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4241 return -EINVAL;
4242 }
4243 return 0;
4244}
4245
Bard Liao28d2ca32017-03-09 19:31:14 +0800[diff] [blame]4246static int rt5665_set_codec_sysclk(struct snd_soc_codec *codec, int clk_id,
4247 int source, unsigned int freq, int dir)
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4248{
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4249 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4250 unsigned int reg_val = 0;
4251
4252 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4253 return 0;
4254
4255 switch (clk_id) {
4256 case RT5665_SCLK_S_MCLK:
4257 reg_val |= RT5665_SCLK_SRC_MCLK;
4258 break;
4259 case RT5665_SCLK_S_PLL1:
4260 reg_val |= RT5665_SCLK_SRC_PLL1;
4261 break;
4262 case RT5665_SCLK_S_RCCLK:
4263 reg_val |= RT5665_SCLK_SRC_RCCLK;
4264 break;
4265 default:
4266 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4267 return -EINVAL;
4268 }
4269 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4270 RT5665_SCLK_SRC_MASK, reg_val);
4271 rt5665->sysclk = freq;
4272 rt5665->sysclk_src = clk_id;
4273
Bard Liao28d2ca32017-03-09 19:31:14 +0800[diff] [blame]4274 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4275
4276 return 0;
4277}
4278
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4279static int rt5665_set_codec_pll(struct snd_soc_codec *codec, int pll_id,
4280 int source, unsigned int freq_in,
4281 unsigned int freq_out)
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4282{
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4283 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4284 struct rl6231_pll_code pll_code;
4285 int ret;
4286
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4287 if (source == rt5665->pll_src && freq_in == rt5665->pll_in &&
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4288 freq_out == rt5665->pll_out)
4289 return 0;
4290
4291 if (!freq_in || !freq_out) {
4292 dev_dbg(codec->dev, "PLL disabled\n");
4293
4294 rt5665->pll_in = 0;
4295 rt5665->pll_out = 0;
4296 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4297 RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
4298 return 0;
4299 }
4300
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4301 switch (source) {
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4302 case RT5665_PLL1_S_MCLK:
4303 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4304 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
4305 break;
4306 case RT5665_PLL1_S_BCLK1:
4307 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4308 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
4309 break;
4310 case RT5665_PLL1_S_BCLK2:
4311 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4312 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
4313 break;
4314 case RT5665_PLL1_S_BCLK3:
4315 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4316 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
4317 break;
4318 default:
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4319 dev_err(codec->dev, "Unknown PLL Source %d\n", source);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4320 return -EINVAL;
4321 }
4322
4323 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
4324 if (ret < 0) {
4325 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4326 return ret;
4327 }
4328
4329 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
4330 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4331 pll_code.n_code, pll_code.k_code);
4332
4333 snd_soc_write(codec, RT5665_PLL_CTRL_1,
4334 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
4335 snd_soc_write(codec, RT5665_PLL_CTRL_2,
4336 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT |
4337 pll_code.m_bp << RT5665_PLL_M_BP_SFT);
4338
4339 rt5665->pll_in = freq_in;
4340 rt5665->pll_out = freq_out;
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4341 rt5665->pll_src = source;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4342
4343 return 0;
4344}
4345
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4346static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
4347{
4348 struct snd_soc_codec *codec = dai->codec;
4349 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4350
4351 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
4352
4353 rt5665->bclk[dai->id] = ratio;
4354
4355 if (ratio == 64) {
4356 switch (dai->id) {
4357 case RT5665_AIF2_1:
4358 case RT5665_AIF2_2:
4359 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4360 RT5665_I2S_BCLK_MS2_MASK,
4361 RT5665_I2S_BCLK_MS2_64);
4362 break;
4363 case RT5665_AIF3:
4364 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4365 RT5665_I2S_BCLK_MS3_MASK,
4366 RT5665_I2S_BCLK_MS3_64);
4367 break;
4368 }
4369 }
4370
4371 return 0;
4372}
4373
4374static int rt5665_set_bias_level(struct snd_soc_codec *codec,
4375 enum snd_soc_bias_level level)
4376{
4377 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4378
4379 switch (level) {
4380 case SND_SOC_BIAS_PREPARE:
4381 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4382 RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
4383 break;
4384
4385 case SND_SOC_BIAS_STANDBY:
4386 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4387 RT5665_PWR_LDO, RT5665_PWR_LDO);
4388 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4389 RT5665_PWR_MB, RT5665_PWR_MB);
4390 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4391 RT5665_DIG_GATE_CTRL, 0);
4392 break;
4393 case SND_SOC_BIAS_OFF:
4394 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4395 RT5665_PWR_LDO, 0);
4396 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4397 RT5665_PWR_MB, 0);
4398 break;
4399
4400 default:
4401 break;
4402 }
4403
4404 return 0;
4405}
4406
4407static int rt5665_probe(struct snd_soc_codec *codec)
4408{
4409 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4410
4411 rt5665->codec = codec;
4412
4413 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4414
4415 return 0;
4416}
4417
4418static int rt5665_remove(struct snd_soc_codec *codec)
4419{
4420 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4421
4422 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4423
4424 return 0;
4425}
4426
4427#ifdef CONFIG_PM
4428static int rt5665_suspend(struct snd_soc_codec *codec)
4429{
4430 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4431
4432 regcache_cache_only(rt5665->regmap, true);
4433 regcache_mark_dirty(rt5665->regmap);
4434 return 0;
4435}
4436
4437static int rt5665_resume(struct snd_soc_codec *codec)
4438{
4439 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4440
4441 regcache_cache_only(rt5665->regmap, false);
4442 regcache_sync(rt5665->regmap);
4443
4444 return 0;
4445}
4446#else
4447#define rt5665_suspend NULL
4448#define rt5665_resume NULL
4449#endif
4450
4451#define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
4452#define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4453 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4454
4455static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
4456 .hw_params = rt5665_hw_params,
4457 .set_fmt = rt5665_set_dai_fmt,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4458 .set_tdm_slot = rt5665_set_tdm_slot,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4459 .set_bclk_ratio = rt5665_set_bclk_ratio,
4460};
4461
4462static struct snd_soc_dai_driver rt5665_dai[] = {
4463 {
4464 .name = "rt5665-aif1_1",
4465 .id = RT5665_AIF1_1,
4466 .playback = {
4467 .stream_name = "AIF1 Playback",
4468 .channels_min = 1,
4469 .channels_max = 8,
4470 .rates = RT5665_STEREO_RATES,
4471 .formats = RT5665_FORMATS,
4472 },
4473 .capture = {
4474 .stream_name = "AIF1_1 Capture",
4475 .channels_min = 1,
4476 .channels_max = 8,
4477 .rates = RT5665_STEREO_RATES,
4478 .formats = RT5665_FORMATS,
4479 },
4480 .ops = &rt5665_aif_dai_ops,
4481 },
4482 {
4483 .name = "rt5665-aif1_2",
4484 .id = RT5665_AIF1_2,
4485 .capture = {
4486 .stream_name = "AIF1_2 Capture",
4487 .channels_min = 1,
4488 .channels_max = 8,
4489 .rates = RT5665_STEREO_RATES,
4490 .formats = RT5665_FORMATS,
4491 },
4492 .ops = &rt5665_aif_dai_ops,
4493 },
4494 {
4495 .name = "rt5665-aif2_1",
4496 .id = RT5665_AIF2_1,
4497 .playback = {
4498 .stream_name = "AIF2_1 Playback",
4499 .channels_min = 1,
4500 .channels_max = 2,
4501 .rates = RT5665_STEREO_RATES,
4502 .formats = RT5665_FORMATS,
4503 },
4504 .capture = {
4505 .stream_name = "AIF2_1 Capture",
4506 .channels_min = 1,
4507 .channels_max = 2,
4508 .rates = RT5665_STEREO_RATES,
4509 .formats = RT5665_FORMATS,
4510 },
4511 .ops = &rt5665_aif_dai_ops,
4512 },
4513 {
4514 .name = "rt5665-aif2_2",
4515 .id = RT5665_AIF2_2,
4516 .playback = {
4517 .stream_name = "AIF2_2 Playback",
4518 .channels_min = 1,
4519 .channels_max = 2,
4520 .rates = RT5665_STEREO_RATES,
4521 .formats = RT5665_FORMATS,
4522 },
4523 .capture = {
4524 .stream_name = "AIF2_2 Capture",
4525 .channels_min = 1,
4526 .channels_max = 2,
4527 .rates = RT5665_STEREO_RATES,
4528 .formats = RT5665_FORMATS,
4529 },
4530 .ops = &rt5665_aif_dai_ops,
4531 },
4532 {
4533 .name = "rt5665-aif3",
4534 .id = RT5665_AIF3,
4535 .playback = {
4536 .stream_name = "AIF3 Playback",
4537 .channels_min = 1,
4538 .channels_max = 2,
4539 .rates = RT5665_STEREO_RATES,
4540 .formats = RT5665_FORMATS,
4541 },
4542 .capture = {
4543 .stream_name = "AIF3 Capture",
4544 .channels_min = 1,
4545 .channels_max = 2,
4546 .rates = RT5665_STEREO_RATES,
4547 .formats = RT5665_FORMATS,
4548 },
4549 .ops = &rt5665_aif_dai_ops,
4550 },
4551};
4552
4553static struct snd_soc_codec_driver soc_codec_dev_rt5665 = {
4554 .probe = rt5665_probe,
4555 .remove = rt5665_remove,
4556 .suspend = rt5665_suspend,
4557 .resume = rt5665_resume,
4558 .set_bias_level = rt5665_set_bias_level,
4559 .idle_bias_off = true,
4560 .component_driver = {
4561 .controls = rt5665_snd_controls,
4562 .num_controls = ARRAY_SIZE(rt5665_snd_controls),
4563 .dapm_widgets = rt5665_dapm_widgets,
4564 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
4565 .dapm_routes = rt5665_dapm_routes,
4566 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4567 },
Bard Liao28d2ca32017-03-09 19:31:14 +0800[diff] [blame]4568 .set_sysclk = rt5665_set_codec_sysclk,
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4569 .set_pll = rt5665_set_codec_pll,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4570};
4571
4572
4573static const struct regmap_config rt5665_regmap = {
4574 .reg_bits = 16,
4575 .val_bits = 16,
4576 .max_register = 0x0400,
4577 .volatile_reg = rt5665_volatile_register,
4578 .readable_reg = rt5665_readable_register,
4579 .cache_type = REGCACHE_RBTREE,
4580 .reg_defaults = rt5665_reg,
4581 .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
4582 .use_single_rw = true,
4583};
4584
4585static const struct i2c_device_id rt5665_i2c_id[] = {
4586 {"rt5665", 0},
4587 {}
4588};
4589MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
4590
4591static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
4592{
4593 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4594 "realtek,in1-differential");
4595 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4596 "realtek,in2-differential");
4597 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4598 "realtek,in3-differential");
4599 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4600 "realtek,in4-differential");
4601
4602 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4603 &rt5665->pdata.dmic1_data_pin);
4604 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4605 &rt5665->pdata.dmic2_data_pin);
4606 of_property_read_u32(dev->of_node, "realtek,jd-src",
4607 &rt5665->pdata.jd_src);
4608
4609 rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
4610 "realtek,ldo1-en-gpios", 0);
4611
4612 return 0;
4613}
4614
4615static void rt5665_calibrate(struct rt5665_priv *rt5665)
4616{
4617 int value, count;
4618
4619 mutex_lock(&rt5665->calibrate_mutex);
4620
4621 regcache_cache_bypass(rt5665->regmap, true);
4622
4623 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4624 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4625 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4626 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4627 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4628 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4629 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4630 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4631 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4632 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4633 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4634 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4635 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4636 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4637 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4638 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4639 usleep_range(15000, 20000);
4640 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4641 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4642
4643 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4644 count = 0;
4645 while (true) {
4646 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4647 if (value & 0x8000)
4648 usleep_range(10000, 10005);
4649 else
4650 break;
4651
4652 if (count > 60) {
4653 pr_err("HP Calibration Failure\n");
4654 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4655 regcache_cache_bypass(rt5665->regmap, false);
Axel Lin0c956662016-11-16 21:08:41 +0800[diff] [blame]4656 goto out_unlock;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4657 }
4658
4659 count++;
4660 }
4661
4662 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4663 count = 0;
4664 while (true) {
4665 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4666 if (value & 0x8000)
4667 usleep_range(10000, 10005);
4668 else
4669 break;
4670
4671 if (count > 60) {
4672 pr_err("MONO Calibration Failure\n");
4673 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4674 regcache_cache_bypass(rt5665->regmap, false);
Axel Lin0c956662016-11-16 21:08:41 +0800[diff] [blame]4675 goto out_unlock;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4676 }
4677
4678 count++;
4679 }
4680
4681 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4682 regcache_cache_bypass(rt5665->regmap, false);
4683
4684 regcache_mark_dirty(rt5665->regmap);
4685 regcache_sync(rt5665->regmap);
4686
4687 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4688 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4689
Axel Lin0c956662016-11-16 21:08:41 +0800[diff] [blame]4690out_unlock:
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4691 mutex_unlock(&rt5665->calibrate_mutex);
4692}
4693
4694static void rt5665_calibrate_handler(struct work_struct *work)
4695{
4696 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
4697 calibrate_work.work);
4698
4699 while (!rt5665->codec->component.card->instantiated) {
4700 pr_debug("%s\n", __func__);
4701 usleep_range(10000, 15000);
4702 }
4703
4704 rt5665_calibrate(rt5665);
4705}
4706
4707static int rt5665_i2c_probe(struct i2c_client *i2c,
4708 const struct i2c_device_id *id)
4709{
4710 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4711 struct rt5665_priv *rt5665;
4712 int i, ret;
4713 unsigned int val;
4714
4715 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4716 GFP_KERNEL);
4717
4718 if (rt5665 == NULL)
4719 return -ENOMEM;
4720
4721 i2c_set_clientdata(i2c, rt5665);
4722
4723 if (pdata)
4724 rt5665->pdata = *pdata;
4725 else
4726 rt5665_parse_dt(rt5665, &i2c->dev);
4727
4728 for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
4729 rt5665->supplies[i].supply = rt5665_supply_names[i];
4730
4731 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
4732 rt5665->supplies);
4733 if (ret != 0) {
4734 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4735 return ret;
4736 }
4737
4738 ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
4739 rt5665->supplies);
4740 if (ret != 0) {
4741 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4742 return ret;
4743 }
4744
4745 if (gpio_is_valid(rt5665->pdata.ldo1_en)) {
Axel Linf2826c12016-11-16 21:08:42 +0800[diff] [blame]4746 if (devm_gpio_request_one(&i2c->dev, rt5665->pdata.ldo1_en,
4747 GPIOF_OUT_INIT_HIGH, "rt5665"))
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4748 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4749 }
4750
4751 /* Sleep for 300 ms miniumum */
4752 usleep_range(300000, 350000);
4753
4754 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4755 if (IS_ERR(rt5665->regmap)) {
4756 ret = PTR_ERR(rt5665->regmap);
4757 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4758 ret);
4759 return ret;
4760 }
4761
4762 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4763 if (val != DEVICE_ID) {
4764 dev_err(&i2c->dev,
4765 "Device with ID register %x is not rt5665\n", val);
4766 return -ENODEV;
4767 }
4768
4769 regmap_read(rt5665->regmap, RT5665_RESET, &val);
4770 switch (val) {
4771 case 0x0:
4772 rt5665->id = CODEC_5666;
4773 break;
4774 case 0x6:
4775 rt5665->id = CODEC_5668;
4776 break;
4777 case 0x3:
4778 default:
4779 rt5665->id = CODEC_5665;
4780 break;
4781 }
4782
4783 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4784
4785 /* line in diff mode*/
4786 if (rt5665->pdata.in1_diff)
4787 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4788 RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
4789 if (rt5665->pdata.in2_diff)
4790 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4791 RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
4792 if (rt5665->pdata.in3_diff)
4793 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4794 RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
4795 if (rt5665->pdata.in4_diff)
4796 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4797 RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
4798
4799 /* DMIC pin*/
4800 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4801 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4802 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4803 RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
4804 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4805 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
4806 switch (rt5665->pdata.dmic1_data_pin) {
4807 case RT5665_DMIC1_DATA_IN2N:
4808 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4809 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
4810 break;
4811
4812 case RT5665_DMIC1_DATA_GPIO4:
4813 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4814 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
4815 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4816 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
4817 break;
4818
4819 default:
4820 dev_dbg(&i2c->dev, "no DMIC1\n");
4821 break;
4822 }
4823
4824 switch (rt5665->pdata.dmic2_data_pin) {
4825 case RT5665_DMIC2_DATA_IN2P:
4826 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4827 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
4828 break;
4829
4830 case RT5665_DMIC2_DATA_GPIO5:
4831 regmap_update_bits(rt5665->regmap,
4832 RT5665_DMIC_CTRL_1,
4833 RT5665_DMIC_2_DP_MASK,
4834 RT5665_DMIC_2_DP_GPIO5);
4835 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4836 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
4837 break;
4838
4839 default:
4840 dev_dbg(&i2c->dev, "no DMIC2\n");
4841 break;
4842
4843 }
4844 }
4845
4846 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4847 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
Bard Liao39841942017-03-08 19:05:30 +0800[diff] [blame]4848 0xf000 | RT5665_VREF_POW_MASK, 0xe000 | RT5665_VREF_POW_REG);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4849 /* Work around for pow_pump */
4850 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4851 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
4852
4853 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4854 RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
4855
4856 /* Set GPIO4,8 as input for combo jack */
4857 if (rt5665->id == CODEC_5666) {
4858 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4859 RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
4860 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4861 RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
4862 }
4863
4864 /* Enhance performance*/
4865 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4866 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
Bard Liao593dd5d2017-03-08 19:05:29 +0800[diff] [blame]4867 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4868
4869 INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4870 rt5665_jack_detect_handler);
4871 INIT_DELAYED_WORK(&rt5665->calibrate_work,
4872 rt5665_calibrate_handler);
4873 INIT_DELAYED_WORK(&rt5665->jd_check_work,
4874 rt5665_jd_check_handler);
4875
4876 mutex_init(&rt5665->calibrate_mutex);
4877
4878 if (i2c->irq) {
4879 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4880 rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4881 | IRQF_ONESHOT, "rt5665", rt5665);
4882 if (ret)
4883 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4884
4885 }
4886
4887 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5665,
4888 rt5665_dai, ARRAY_SIZE(rt5665_dai));
4889}
4890
4891static int rt5665_i2c_remove(struct i2c_client *i2c)
4892{
4893 snd_soc_unregister_codec(&i2c->dev);
4894
4895 return 0;
4896}
4897
4898static void rt5665_i2c_shutdown(struct i2c_client *client)
4899{
4900 struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
4901
4902 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4903}
4904
4905#ifdef CONFIG_OF
4906static const struct of_device_id rt5665_of_match[] = {
4907 {.compatible = "realtek,rt5665"},
4908 {.compatible = "realtek,rt5666"},
4909 {.compatible = "realtek,rt5668"},
4910 {},
4911};
4912MODULE_DEVICE_TABLE(of, rt5665_of_match);
4913#endif
4914
4915#ifdef CONFIG_ACPI
4916static struct acpi_device_id rt5665_acpi_match[] = {
4917 {"10EC5665", 0,},
4918 {"10EC5666", 0,},
4919 {"10EC5668", 0,},
4920 {},
4921};
4922MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
4923#endif
4924
4925struct i2c_driver rt5665_i2c_driver = {
4926 .driver = {
4927 .name = "rt5665",
4928 .of_match_table = of_match_ptr(rt5665_of_match),
4929 .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
4930 },
4931 .probe = rt5665_i2c_probe,
4932 .remove = rt5665_i2c_remove,
4933 .shutdown = rt5665_i2c_shutdown,
4934 .id_table = rt5665_i2c_id,
4935};
4936module_i2c_driver(rt5665_i2c_driver);
4937
4938MODULE_DESCRIPTION("ASoC RT5665 driver");
4939MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4940MODULE_LICENSE("GPL v2");