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gerrit-public.fairphone.software / kernel / msm-5.4 / 184cd4a3b962a4769889615430eaf40076b97969 / . / arch / powerpc / platforms / powernv / pci.h
blob: 28ae4ca512c4752db3ede399e37a581b98da0dc5 [file] [log] [blame]
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]1#ifndef __POWERNV_PCI_H
2#define __POWERNV_PCI_H
3
4struct pci_dn;
5
6enum pnv_phb_type {
7 PNV_PHB_P5IOC2,
8 PNV_PHB_IODA1,
9 PNV_PHB_IODA2,
10};
11
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame^]12/* Data associated with a PE, including IOMMU tracking etc.. */
13struct pnv_ioda_pe {
14 /* A PE can be associated with a single device or an
15 * entire bus (& children). In the former case, pdev
16 * is populated, in the later case, pbus is.
17 */
18 struct pci_dev *pdev;
19 struct pci_bus *pbus;
20
21 /* Effective RID (device RID for a device PE and base bus
22 * RID with devfn 0 for a bus PE)
23 */
24 unsigned int rid;
25
26 /* PE number */
27 unsigned int pe_number;
28
29 /* "Weight" assigned to the PE for the sake of DMA resource
30 * allocations
31 */
32 unsigned int dma_weight;
33
34 /* This is a PCI-E -> PCI-X bridge, this points to the
35 * corresponding bus PE
36 */
37 struct pnv_ioda_pe *bus_pe;
38
39 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
40 int tce32_seg;
41 int tce32_segcount;
42 struct iommu_table tce32_table;
43
44 /* XXX TODO: Add support for additional 64-bit iommus */
45
46 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
47 * and -1 if not supported. (It's actually identical to the
48 * PE number)
49 */
50 int mve_number;
51
52 /* Link in list of PE#s */
53 struct list_head link;
54};
55
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]56struct pnv_phb {
57 struct pci_controller *hose;
58 enum pnv_phb_type type;
59 u64 opal_id;
60 void __iomem *regs;
61 spinlock_t lock;
62
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]63#ifdef CONFIG_PCI_MSI
64 unsigned long *msi_map;
65 unsigned int msi_base;
66 unsigned int msi_count;
67 unsigned int msi_next;
68 unsigned int msi32_support;
69#endif
70 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
71 unsigned int hwirq, unsigned int is_64,
72 struct msi_msg *msg);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]73 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
74 void (*fixup_phb)(struct pci_controller *hose);
75 u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
76
77 union {
78 struct {
79 struct iommu_table iommu_table;
80 } p5ioc2;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame^]81
82 struct {
83 /* Global bridge info */
84 unsigned int total_pe;
85 unsigned int m32_size;
86 unsigned int m32_segsize;
87 unsigned int m32_pci_base;
88 unsigned int io_size;
89 unsigned int io_segsize;
90 unsigned int io_pci_base;
91
92 /* PE allocation bitmap */
93 unsigned long *pe_alloc;
94
95 /* M32 & IO segment maps */
96 unsigned int *m32_segmap;
97 unsigned int *io_segmap;
98 struct pnv_ioda_pe *pe_array;
99
100 /* Reverse map of PEs, will have to extend if
101 * we are to support more than 256 PEs, indexed
102 * bus { bus, devfn }
103 */
104 unsigned char pe_rmap[0x10000];
105
106 /* 32-bit TCE tables allocation */
107 unsigned long tce32_count;
108
109 /* Total "weight" for the sake of DMA resources
110 * allocation
111 */
112 unsigned int dma_weight;
113 unsigned int dma_pe_count;
114
115 /* Sorted list of used PE's, sorted at
116 * boot for resource allocation purposes
117 */
118 struct list_head pe_list;
119 } ioda;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]120 };
121};
122
123extern struct pci_ops pnv_pci_ops;
124
125extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
126 void *tce_mem, u64 tce_size,
127 u64 dma_offset);
128extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame^]129extern void pnv_pci_init_ioda_hub(struct device_node *np);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]130
131
132#endif /* __POWERNV_PCI_H */