blob: acf1a318fda9000e9ec102784254310ed735ef2f [file] [log] [blame]
Eugeni Dodonov85208be2012-04-16 22:20:34 -03001/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -030028#include <linux/cpufreq.h>
Eugeni Dodonov85208be2012-04-16 22:20:34 -030029#include "i915_drv.h"
30#include "intel_drv.h"
Daniel Vettereb48eb02012-04-26 23:28:12 +020031#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
Eugeni Dodonov85208be2012-04-16 22:20:34 -030033
Ben Widawskydc39fff2013-10-18 12:32:07 -070034/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
Damien Lespiauda2078c2013-02-13 15:27:27 +000055static void gen9_init_clock_gating(struct drm_device *dev)
56{
Damien Lespiauacd5c342014-03-26 16:55:46 +000057 struct drm_i915_private *dev_priv = dev->dev_private;
58
Damien Lespiau77719d22015-02-09 19:33:13 +000059 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62}
Damien Lespiau91e41d12014-03-26 17:42:50 +000063
Damien Lespiau45db2192015-02-09 19:33:09 +000064static void skl_init_clock_gating(struct drm_device *dev)
Damien Lespiauda2078c2013-02-13 15:27:27 +000065{
Damien Lespiauacd5c342014-03-26 16:55:46 +000066 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau3ca5da42014-03-26 18:18:01 +000067
Damien Lespiau77719d22015-02-09 19:33:13 +000068 gen9_init_clock_gating(dev);
69
Damien Lespiau669506e2015-02-26 18:20:38 +000070 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
Hoath, Nicholas3dcd0202015-02-05 10:47:21 +000071 /*
72 * WaDisableSDEUnitClockGating:skl
Damien Lespiau9253c2e2015-02-09 19:33:10 +000073 * WaSetGAPSunitClckGateDisable:skl
Hoath, Nicholas3dcd0202015-02-05 10:47:21 +000074 */
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
Damien Lespiau9253c2e2015-02-09 19:33:10 +000076 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
Hoath, Nicholas3dcd0202015-02-05 10:47:21 +000077 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
Damien Lespiauf9fc42f2015-02-26 18:20:39 +000078
79 /* WaDisableVFUnitClockGating:skl */
80 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
81 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
Hoath, Nicholas3dcd0202015-02-05 10:47:21 +000082 }
Damien Lespiau8bc0ccf2015-02-09 19:33:18 +000083
Damien Lespiau2caa3b22015-02-09 19:33:20 +000084 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
Damien Lespiau81e231a2015-02-09 19:33:19 +000085 /* WaDisableHDCInvalidation:skl */
86 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
87 BDW_DISABLE_HDC_INVALIDATION);
88
Damien Lespiau2caa3b22015-02-09 19:33:20 +000089 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
90 I915_WRITE(FF_SLICE_CS_CHICKEN2,
91 I915_READ(FF_SLICE_CS_CHICKEN2) |
92 GEN9_TSG_BARRIER_ACK_DISABLE);
93 }
Damien Lespiau81e231a2015-02-09 19:33:19 +000094
Damien Lespiau8bc0ccf2015-02-09 19:33:18 +000095 if (INTEL_REVID(dev) <= SKL_REVID_E0)
96 /* WaDisableLSQCROPERFforOCL:skl */
97 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
98 GEN8_LQSC_RO_PERF_DIS);
Damien Lespiauda2078c2013-02-13 15:27:27 +000099}
100
Daniel Vetterc921aba2012-04-26 23:28:17 +0200101static void i915_pineview_get_mem_freq(struct drm_device *dev)
102{
Jani Nikula50227e12014-03-31 14:27:21 +0300103 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterc921aba2012-04-26 23:28:17 +0200104 u32 tmp;
105
106 tmp = I915_READ(CLKCFG);
107
108 switch (tmp & CLKCFG_FSB_MASK) {
109 case CLKCFG_FSB_533:
110 dev_priv->fsb_freq = 533; /* 133*4 */
111 break;
112 case CLKCFG_FSB_800:
113 dev_priv->fsb_freq = 800; /* 200*4 */
114 break;
115 case CLKCFG_FSB_667:
116 dev_priv->fsb_freq = 667; /* 167*4 */
117 break;
118 case CLKCFG_FSB_400:
119 dev_priv->fsb_freq = 400; /* 100*4 */
120 break;
121 }
122
123 switch (tmp & CLKCFG_MEM_MASK) {
124 case CLKCFG_MEM_533:
125 dev_priv->mem_freq = 533;
126 break;
127 case CLKCFG_MEM_667:
128 dev_priv->mem_freq = 667;
129 break;
130 case CLKCFG_MEM_800:
131 dev_priv->mem_freq = 800;
132 break;
133 }
134
135 /* detect pineview DDR3 setting */
136 tmp = I915_READ(CSHRDDR3CTL);
137 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
138}
139
140static void i915_ironlake_get_mem_freq(struct drm_device *dev)
141{
Jani Nikula50227e12014-03-31 14:27:21 +0300142 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterc921aba2012-04-26 23:28:17 +0200143 u16 ddrpll, csipll;
144
145 ddrpll = I915_READ16(DDRMPLL1);
146 csipll = I915_READ16(CSIPLL0);
147
148 switch (ddrpll & 0xff) {
149 case 0xc:
150 dev_priv->mem_freq = 800;
151 break;
152 case 0x10:
153 dev_priv->mem_freq = 1066;
154 break;
155 case 0x14:
156 dev_priv->mem_freq = 1333;
157 break;
158 case 0x18:
159 dev_priv->mem_freq = 1600;
160 break;
161 default:
162 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
163 ddrpll & 0xff);
164 dev_priv->mem_freq = 0;
165 break;
166 }
167
Daniel Vetter20e4d402012-08-08 23:35:39 +0200168 dev_priv->ips.r_t = dev_priv->mem_freq;
Daniel Vetterc921aba2012-04-26 23:28:17 +0200169
170 switch (csipll & 0x3ff) {
171 case 0x00c:
172 dev_priv->fsb_freq = 3200;
173 break;
174 case 0x00e:
175 dev_priv->fsb_freq = 3733;
176 break;
177 case 0x010:
178 dev_priv->fsb_freq = 4266;
179 break;
180 case 0x012:
181 dev_priv->fsb_freq = 4800;
182 break;
183 case 0x014:
184 dev_priv->fsb_freq = 5333;
185 break;
186 case 0x016:
187 dev_priv->fsb_freq = 5866;
188 break;
189 case 0x018:
190 dev_priv->fsb_freq = 6400;
191 break;
192 default:
193 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
194 csipll & 0x3ff);
195 dev_priv->fsb_freq = 0;
196 break;
197 }
198
199 if (dev_priv->fsb_freq == 3200) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200200 dev_priv->ips.c_m = 0;
Daniel Vetterc921aba2012-04-26 23:28:17 +0200201 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200202 dev_priv->ips.c_m = 1;
Daniel Vetterc921aba2012-04-26 23:28:17 +0200203 } else {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200204 dev_priv->ips.c_m = 2;
Daniel Vetterc921aba2012-04-26 23:28:17 +0200205 }
206}
207
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300208static const struct cxsr_latency cxsr_latency_table[] = {
209 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
210 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
211 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
212 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
213 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
214
215 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
216 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
217 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
218 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
219 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
220
221 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
222 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
223 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
224 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
225 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
226
227 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
228 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
229 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
230 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
231 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
232
233 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
234 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
235 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
236 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
237 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
238
239 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
240 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
241 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
242 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
243 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
244};
245
Daniel Vetter63c62272012-04-21 23:17:55 +0200246static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300247 int is_ddr3,
248 int fsb,
249 int mem)
250{
251 const struct cxsr_latency *latency;
252 int i;
253
254 if (fsb == 0 || mem == 0)
255 return NULL;
256
257 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
258 latency = &cxsr_latency_table[i];
259 if (is_desktop == latency->is_desktop &&
260 is_ddr3 == latency->is_ddr3 &&
261 fsb == latency->fsb_freq && mem == latency->mem_freq)
262 return latency;
263 }
264
265 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
266
267 return NULL;
268}
269
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +0200270static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
271{
272 u32 val;
273
274 mutex_lock(&dev_priv->rps.hw_lock);
275
276 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
277 if (enable)
278 val &= ~FORCE_DDR_HIGH_FREQ;
279 else
280 val |= FORCE_DDR_HIGH_FREQ;
281 val &= ~FORCE_DDR_LOW_FREQ;
282 val |= FORCE_DDR_FREQ_REQ_ACK;
283 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
284
285 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
286 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
287 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
288
289 mutex_unlock(&dev_priv->rps.hw_lock);
290}
291
Ville Syrjäläcfb41412015-03-05 21:19:51 +0200292static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
293{
294 u32 val;
295
296 mutex_lock(&dev_priv->rps.hw_lock);
297
298 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
299 if (enable)
300 val |= DSP_MAXFIFO_PM5_ENABLE;
301 else
302 val &= ~DSP_MAXFIFO_PM5_ENABLE;
303 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
304
305 mutex_unlock(&dev_priv->rps.hw_lock);
306}
307
Ville Syrjäläf4998962015-03-10 17:02:21 +0200308#define FW_WM(value, plane) \
309 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
310
Imre Deak5209b1f2014-07-01 12:36:17 +0300311void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300312{
Imre Deak5209b1f2014-07-01 12:36:17 +0300313 struct drm_device *dev = dev_priv->dev;
314 u32 val;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300315
Imre Deak5209b1f2014-07-01 12:36:17 +0300316 if (IS_VALLEYVIEW(dev)) {
317 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
Ville Syrjäläcfb41412015-03-05 21:19:51 +0200318 if (IS_CHERRYVIEW(dev))
319 chv_set_memory_pm5(dev_priv, enable);
Imre Deak5209b1f2014-07-01 12:36:17 +0300320 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
321 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
322 } else if (IS_PINEVIEW(dev)) {
323 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
324 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
325 I915_WRITE(DSPFW3, val);
326 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
327 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
328 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
329 I915_WRITE(FW_BLC_SELF, val);
330 } else if (IS_I915GM(dev)) {
331 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
332 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
333 I915_WRITE(INSTPM, val);
334 } else {
335 return;
336 }
337
338 DRM_DEBUG_KMS("memory self-refresh is %s\n",
339 enable ? "enabled" : "disabled");
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300340}
341
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +0200342
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300343/*
344 * Latency for FIFO fetches is dependent on several factors:
345 * - memory configuration (speed, channels)
346 * - chipset
347 * - current MCH state
348 * It can be fairly high in some situations, so here we assume a fairly
349 * pessimal value. It's a tradeoff between extra memory fetches (if we
350 * set this value too high, the FIFO will fetch frequently to stay full)
351 * and power consumption (set it too low to save power and we might see
352 * FIFO underruns and display "flicker").
353 *
354 * A value of 5us seems to be a good balance; safe for very low end
355 * platforms but not overly aggressive on lower latency configs.
356 */
Chris Wilson5aef6002014-09-03 11:56:07 +0100357static const int pessimal_latency_ns = 5000;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300358
Ville Syrjäläb5004722015-03-05 21:19:47 +0200359#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
360 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
361
362static int vlv_get_fifo_size(struct drm_device *dev,
363 enum pipe pipe, int plane)
364{
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 int sprite0_start, sprite1_start, size;
367
368 switch (pipe) {
369 uint32_t dsparb, dsparb2, dsparb3;
370 case PIPE_A:
371 dsparb = I915_READ(DSPARB);
372 dsparb2 = I915_READ(DSPARB2);
373 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
374 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
375 break;
376 case PIPE_B:
377 dsparb = I915_READ(DSPARB);
378 dsparb2 = I915_READ(DSPARB2);
379 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
380 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
381 break;
382 case PIPE_C:
383 dsparb2 = I915_READ(DSPARB2);
384 dsparb3 = I915_READ(DSPARB3);
385 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
386 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
387 break;
388 default:
389 return 0;
390 }
391
392 switch (plane) {
393 case 0:
394 size = sprite0_start;
395 break;
396 case 1:
397 size = sprite1_start - sprite0_start;
398 break;
399 case 2:
400 size = 512 - 1 - sprite1_start;
401 break;
402 default:
403 return 0;
404 }
405
406 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
407 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
408 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
409 size);
410
411 return size;
412}
413
Eugeni Dodonov1fa61102012-04-18 15:29:26 -0300414static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300415{
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 uint32_t dsparb = I915_READ(DSPARB);
418 int size;
419
420 size = dsparb & 0x7f;
421 if (plane)
422 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
423
424 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
425 plane ? "B" : "A", size);
426
427 return size;
428}
429
Daniel Vetterfeb56b92013-12-14 20:38:30 -0200430static int i830_get_fifo_size(struct drm_device *dev, int plane)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300431{
432 struct drm_i915_private *dev_priv = dev->dev_private;
433 uint32_t dsparb = I915_READ(DSPARB);
434 int size;
435
436 size = dsparb & 0x1ff;
437 if (plane)
438 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
439 size >>= 1; /* Convert to cachelines */
440
441 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
442 plane ? "B" : "A", size);
443
444 return size;
445}
446
Eugeni Dodonov1fa61102012-04-18 15:29:26 -0300447static int i845_get_fifo_size(struct drm_device *dev, int plane)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300448{
449 struct drm_i915_private *dev_priv = dev->dev_private;
450 uint32_t dsparb = I915_READ(DSPARB);
451 int size;
452
453 size = dsparb & 0x7f;
454 size >>= 2; /* Convert to cachelines */
455
456 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
457 plane ? "B" : "A",
458 size);
459
460 return size;
461}
462
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300463/* Pineview has different values for various configs */
464static const struct intel_watermark_params pineview_display_wm = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300465 .fifo_size = PINEVIEW_DISPLAY_FIFO,
466 .max_wm = PINEVIEW_MAX_WM,
467 .default_wm = PINEVIEW_DFT_WM,
468 .guard_size = PINEVIEW_GUARD_WM,
469 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300470};
471static const struct intel_watermark_params pineview_display_hplloff_wm = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300472 .fifo_size = PINEVIEW_DISPLAY_FIFO,
473 .max_wm = PINEVIEW_MAX_WM,
474 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
475 .guard_size = PINEVIEW_GUARD_WM,
476 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300477};
478static const struct intel_watermark_params pineview_cursor_wm = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300479 .fifo_size = PINEVIEW_CURSOR_FIFO,
480 .max_wm = PINEVIEW_CURSOR_MAX_WM,
481 .default_wm = PINEVIEW_CURSOR_DFT_WM,
482 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
483 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300484};
485static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300486 .fifo_size = PINEVIEW_CURSOR_FIFO,
487 .max_wm = PINEVIEW_CURSOR_MAX_WM,
488 .default_wm = PINEVIEW_CURSOR_DFT_WM,
489 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
490 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300491};
492static const struct intel_watermark_params g4x_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300493 .fifo_size = G4X_FIFO_SIZE,
494 .max_wm = G4X_MAX_WM,
495 .default_wm = G4X_MAX_WM,
496 .guard_size = 2,
497 .cacheline_size = G4X_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300498};
499static const struct intel_watermark_params g4x_cursor_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300500 .fifo_size = I965_CURSOR_FIFO,
501 .max_wm = I965_CURSOR_MAX_WM,
502 .default_wm = I965_CURSOR_DFT_WM,
503 .guard_size = 2,
504 .cacheline_size = G4X_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300505};
506static const struct intel_watermark_params valleyview_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300507 .fifo_size = VALLEYVIEW_FIFO_SIZE,
508 .max_wm = VALLEYVIEW_MAX_WM,
509 .default_wm = VALLEYVIEW_MAX_WM,
510 .guard_size = 2,
511 .cacheline_size = G4X_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300512};
513static const struct intel_watermark_params valleyview_cursor_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300514 .fifo_size = I965_CURSOR_FIFO,
515 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
516 .default_wm = I965_CURSOR_DFT_WM,
517 .guard_size = 2,
518 .cacheline_size = G4X_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300519};
520static const struct intel_watermark_params i965_cursor_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300521 .fifo_size = I965_CURSOR_FIFO,
522 .max_wm = I965_CURSOR_MAX_WM,
523 .default_wm = I965_CURSOR_DFT_WM,
524 .guard_size = 2,
525 .cacheline_size = I915_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300526};
527static const struct intel_watermark_params i945_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300528 .fifo_size = I945_FIFO_SIZE,
529 .max_wm = I915_MAX_WM,
530 .default_wm = 1,
531 .guard_size = 2,
532 .cacheline_size = I915_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300533};
534static const struct intel_watermark_params i915_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300535 .fifo_size = I915_FIFO_SIZE,
536 .max_wm = I915_MAX_WM,
537 .default_wm = 1,
538 .guard_size = 2,
539 .cacheline_size = I915_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300540};
Ville Syrjälä9d539102014-08-15 01:21:53 +0300541static const struct intel_watermark_params i830_a_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300542 .fifo_size = I855GM_FIFO_SIZE,
543 .max_wm = I915_MAX_WM,
544 .default_wm = 1,
545 .guard_size = 2,
546 .cacheline_size = I830_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300547};
Ville Syrjälä9d539102014-08-15 01:21:53 +0300548static const struct intel_watermark_params i830_bc_wm_info = {
549 .fifo_size = I855GM_FIFO_SIZE,
550 .max_wm = I915_MAX_WM/2,
551 .default_wm = 1,
552 .guard_size = 2,
553 .cacheline_size = I830_FIFO_LINE_SIZE,
554};
Daniel Vetterfeb56b92013-12-14 20:38:30 -0200555static const struct intel_watermark_params i845_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300556 .fifo_size = I830_FIFO_SIZE,
557 .max_wm = I915_MAX_WM,
558 .default_wm = 1,
559 .guard_size = 2,
560 .cacheline_size = I830_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300561};
562
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300563/**
564 * intel_calculate_wm - calculate watermark level
565 * @clock_in_khz: pixel clock
566 * @wm: chip FIFO params
567 * @pixel_size: display pixel size
568 * @latency_ns: memory latency for the platform
569 *
570 * Calculate the watermark level (the level at which the display plane will
571 * start fetching from memory again). Each chip has a different display
572 * FIFO size and allocation, so the caller needs to figure that out and pass
573 * in the correct intel_watermark_params structure.
574 *
575 * As the pixel clock runs, the FIFO will be drained at a rate that depends
576 * on the pixel size. When it reaches the watermark level, it'll start
577 * fetching FIFO line sized based chunks from memory until the FIFO fills
578 * past the watermark point. If the FIFO drains completely, a FIFO underrun
579 * will occur, and a display engine hang could result.
580 */
581static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
582 const struct intel_watermark_params *wm,
583 int fifo_size,
584 int pixel_size,
585 unsigned long latency_ns)
586{
587 long entries_required, wm_size;
588
589 /*
590 * Note: we need to make sure we don't overflow for various clock &
591 * latency values.
592 * clocks go from a few thousand to several hundred thousand.
593 * latency is usually a few thousand
594 */
595 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
596 1000;
597 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
598
599 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
600
601 wm_size = fifo_size - (entries_required + wm->guard_size);
602
603 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
604
605 /* Don't promote wm_size to unsigned... */
606 if (wm_size > (long)wm->max_wm)
607 wm_size = wm->max_wm;
608 if (wm_size <= 0)
609 wm_size = wm->default_wm;
Ville Syrjäläd6feb192014-09-05 21:54:13 +0300610
611 /*
612 * Bspec seems to indicate that the value shouldn't be lower than
613 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
614 * Lets go for 8 which is the burst size since certain platforms
615 * already use a hardcoded 8 (which is what the spec says should be
616 * done).
617 */
618 if (wm_size <= 8)
619 wm_size = 8;
620
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300621 return wm_size;
622}
623
624static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
625{
626 struct drm_crtc *crtc, *enabled = NULL;
627
Damien Lespiau70e1e0e2014-05-13 23:32:24 +0100628 for_each_crtc(dev, crtc) {
Chris Wilson3490ea52013-01-07 10:11:40 +0000629 if (intel_crtc_active(crtc)) {
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300630 if (enabled)
631 return NULL;
632 enabled = crtc;
633 }
634 }
635
636 return enabled;
637}
638
Ville Syrjälä46ba6142013-09-10 11:40:40 +0300639static void pineview_update_wm(struct drm_crtc *unused_crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300640{
Ville Syrjälä46ba6142013-09-10 11:40:40 +0300641 struct drm_device *dev = unused_crtc->dev;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300642 struct drm_i915_private *dev_priv = dev->dev_private;
643 struct drm_crtc *crtc;
644 const struct cxsr_latency *latency;
645 u32 reg;
646 unsigned long wm;
647
648 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
649 dev_priv->fsb_freq, dev_priv->mem_freq);
650 if (!latency) {
651 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
Imre Deak5209b1f2014-07-01 12:36:17 +0300652 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300653 return;
654 }
655
656 crtc = single_enabled_crtc(dev);
657 if (crtc) {
Damien Lespiau241bfc32013-09-25 16:45:37 +0100658 const struct drm_display_mode *adjusted_mode;
Matt Roper59bea882015-02-27 10:12:01 -0800659 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
Damien Lespiau241bfc32013-09-25 16:45:37 +0100660 int clock;
661
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200662 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +0100663 clock = adjusted_mode->crtc_clock;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300664
665 /* Display SR */
666 wm = intel_calculate_wm(clock, &pineview_display_wm,
667 pineview_display_wm.fifo_size,
668 pixel_size, latency->display_sr);
669 reg = I915_READ(DSPFW1);
670 reg &= ~DSPFW_SR_MASK;
Ville Syrjäläf4998962015-03-10 17:02:21 +0200671 reg |= FW_WM(wm, SR);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300672 I915_WRITE(DSPFW1, reg);
673 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
674
675 /* cursor SR */
676 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
677 pineview_display_wm.fifo_size,
678 pixel_size, latency->cursor_sr);
679 reg = I915_READ(DSPFW3);
680 reg &= ~DSPFW_CURSOR_SR_MASK;
Ville Syrjäläf4998962015-03-10 17:02:21 +0200681 reg |= FW_WM(wm, CURSOR_SR);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300682 I915_WRITE(DSPFW3, reg);
683
684 /* Display HPLL off SR */
685 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
686 pineview_display_hplloff_wm.fifo_size,
687 pixel_size, latency->display_hpll_disable);
688 reg = I915_READ(DSPFW3);
689 reg &= ~DSPFW_HPLL_SR_MASK;
Ville Syrjäläf4998962015-03-10 17:02:21 +0200690 reg |= FW_WM(wm, HPLL_SR);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300691 I915_WRITE(DSPFW3, reg);
692
693 /* cursor HPLL off SR */
694 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
695 pineview_display_hplloff_wm.fifo_size,
696 pixel_size, latency->cursor_hpll_disable);
697 reg = I915_READ(DSPFW3);
698 reg &= ~DSPFW_HPLL_CURSOR_MASK;
Ville Syrjäläf4998962015-03-10 17:02:21 +0200699 reg |= FW_WM(wm, HPLL_CURSOR);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300700 I915_WRITE(DSPFW3, reg);
701 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
702
Imre Deak5209b1f2014-07-01 12:36:17 +0300703 intel_set_memory_cxsr(dev_priv, true);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300704 } else {
Imre Deak5209b1f2014-07-01 12:36:17 +0300705 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300706 }
707}
708
709static bool g4x_compute_wm0(struct drm_device *dev,
710 int plane,
711 const struct intel_watermark_params *display,
712 int display_latency_ns,
713 const struct intel_watermark_params *cursor,
714 int cursor_latency_ns,
715 int *plane_wm,
716 int *cursor_wm)
717{
718 struct drm_crtc *crtc;
Ville Syrjälä4fe85902013-09-04 18:25:22 +0300719 const struct drm_display_mode *adjusted_mode;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300720 int htotal, hdisplay, clock, pixel_size;
721 int line_time_us, line_count;
722 int entries, tlb_miss;
723
724 crtc = intel_get_crtc_for_plane(dev, plane);
Chris Wilson3490ea52013-01-07 10:11:40 +0000725 if (!intel_crtc_active(crtc)) {
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300726 *cursor_wm = cursor->guard_size;
727 *plane_wm = display->guard_size;
728 return false;
729 }
730
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200731 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +0100732 clock = adjusted_mode->crtc_clock;
Jesse Barnesfec8cba2013-11-27 11:10:26 -0800733 htotal = adjusted_mode->crtc_htotal;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200734 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
Matt Roper59bea882015-02-27 10:12:01 -0800735 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300736
737 /* Use the small buffer method to calculate plane watermark */
738 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
739 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
740 if (tlb_miss > 0)
741 entries += tlb_miss;
742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
743 *plane_wm = entries + display->guard_size;
744 if (*plane_wm > (int)display->max_wm)
745 *plane_wm = display->max_wm;
746
747 /* Use the large buffer method to calculate cursor watermark */
Ville Syrjälä922044c2014-02-14 14:18:57 +0200748 line_time_us = max(htotal * 1000 / clock, 1);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300749 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
Matt Roper3dd512f2015-02-27 10:12:00 -0800750 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300751 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
752 if (tlb_miss > 0)
753 entries += tlb_miss;
754 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
755 *cursor_wm = entries + cursor->guard_size;
756 if (*cursor_wm > (int)cursor->max_wm)
757 *cursor_wm = (int)cursor->max_wm;
758
759 return true;
760}
761
762/*
763 * Check the wm result.
764 *
765 * If any calculated watermark values is larger than the maximum value that
766 * can be programmed into the associated watermark register, that watermark
767 * must be disabled.
768 */
769static bool g4x_check_srwm(struct drm_device *dev,
770 int display_wm, int cursor_wm,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor)
773{
774 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
775 display_wm, cursor_wm);
776
777 if (display_wm > display->max_wm) {
778 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
779 display_wm, display->max_wm);
780 return false;
781 }
782
783 if (cursor_wm > cursor->max_wm) {
784 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
785 cursor_wm, cursor->max_wm);
786 return false;
787 }
788
789 if (!(display_wm || cursor_wm)) {
790 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
791 return false;
792 }
793
794 return true;
795}
796
797static bool g4x_compute_srwm(struct drm_device *dev,
798 int plane,
799 int latency_ns,
800 const struct intel_watermark_params *display,
801 const struct intel_watermark_params *cursor,
802 int *display_wm, int *cursor_wm)
803{
804 struct drm_crtc *crtc;
Ville Syrjälä4fe85902013-09-04 18:25:22 +0300805 const struct drm_display_mode *adjusted_mode;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300806 int hdisplay, htotal, pixel_size, clock;
807 unsigned long line_time_us;
808 int line_count, line_size;
809 int small, large;
810 int entries;
811
812 if (!latency_ns) {
813 *display_wm = *cursor_wm = 0;
814 return false;
815 }
816
817 crtc = intel_get_crtc_for_plane(dev, plane);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200818 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +0100819 clock = adjusted_mode->crtc_clock;
Jesse Barnesfec8cba2013-11-27 11:10:26 -0800820 htotal = adjusted_mode->crtc_htotal;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200821 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
Matt Roper59bea882015-02-27 10:12:01 -0800822 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300823
Ville Syrjälä922044c2014-02-14 14:18:57 +0200824 line_time_us = max(htotal * 1000 / clock, 1);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300825 line_count = (latency_ns / line_time_us + 1000) / 1000;
826 line_size = hdisplay * pixel_size;
827
828 /* Use the minimum of the small and large buffer method for primary */
829 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
830 large = line_count * line_size;
831
832 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
833 *display_wm = entries + display->guard_size;
834
835 /* calculate the self-refresh watermark for display cursor */
Matt Roper3dd512f2015-02-27 10:12:00 -0800836 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300837 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
838 *cursor_wm = entries + cursor->guard_size;
839
840 return g4x_check_srwm(dev,
841 *display_wm, *cursor_wm,
842 display, cursor);
843}
844
Ville Syrjälä15665972015-03-10 16:16:28 +0200845#define FW_WM_VLV(value, plane) \
846 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
847
Ville Syrjälä0018fda2015-03-05 21:19:45 +0200848static void vlv_write_wm_values(struct intel_crtc *crtc,
849 const struct vlv_wm_values *wm)
850{
851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
852 enum pipe pipe = crtc->pipe;
853
854 I915_WRITE(VLV_DDL(pipe),
855 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
856 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
857 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
858 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
859
Ville Syrjäläae801522015-03-05 21:19:49 +0200860 I915_WRITE(DSPFW1,
Ville Syrjälä15665972015-03-10 16:16:28 +0200861 FW_WM(wm->sr.plane, SR) |
862 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
863 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
864 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
Ville Syrjäläae801522015-03-05 21:19:49 +0200865 I915_WRITE(DSPFW2,
Ville Syrjälä15665972015-03-10 16:16:28 +0200866 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
867 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
Ville Syrjäläae801522015-03-05 21:19:49 +0200869 I915_WRITE(DSPFW3,
Ville Syrjälä15665972015-03-10 16:16:28 +0200870 FW_WM(wm->sr.cursor, CURSOR_SR));
Ville Syrjäläae801522015-03-05 21:19:49 +0200871
872 if (IS_CHERRYVIEW(dev_priv)) {
873 I915_WRITE(DSPFW7_CHV,
Ville Syrjälä15665972015-03-10 16:16:28 +0200874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
Ville Syrjäläae801522015-03-05 21:19:49 +0200876 I915_WRITE(DSPFW8_CHV,
Ville Syrjälä15665972015-03-10 16:16:28 +0200877 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
878 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
Ville Syrjäläae801522015-03-05 21:19:49 +0200879 I915_WRITE(DSPFW9_CHV,
Ville Syrjälä15665972015-03-10 16:16:28 +0200880 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
881 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
Ville Syrjäläae801522015-03-05 21:19:49 +0200882 I915_WRITE(DSPHOWM,
Ville Syrjälä15665972015-03-10 16:16:28 +0200883 FW_WM(wm->sr.plane >> 9, SR_HI) |
884 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
885 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
886 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
887 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
888 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
890 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
891 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
892 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
Ville Syrjäläae801522015-03-05 21:19:49 +0200893 } else {
894 I915_WRITE(DSPFW7,
Ville Syrjälä15665972015-03-10 16:16:28 +0200895 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
896 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
Ville Syrjäläae801522015-03-05 21:19:49 +0200897 I915_WRITE(DSPHOWM,
Ville Syrjälä15665972015-03-10 16:16:28 +0200898 FW_WM(wm->sr.plane >> 9, SR_HI) |
899 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
900 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
901 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
902 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
903 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
904 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
Ville Syrjäläae801522015-03-05 21:19:49 +0200905 }
906
907 POSTING_READ(DSPFW1);
908
Ville Syrjälä0018fda2015-03-05 21:19:45 +0200909 dev_priv->wm.vlv = *wm;
910}
911
Ville Syrjälä15665972015-03-10 16:16:28 +0200912#undef FW_WM_VLV
913
Ville Syrjälä341c5262015-03-05 21:19:44 +0200914static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
Ville Syrjälä883a3d22015-03-05 21:19:46 +0200915 struct drm_plane *plane)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300916{
Rodrigo Vivi5e56ba42014-10-17 08:05:08 -0700917 struct drm_device *dev = crtc->dev;
Ville Syrjälä883a3d22015-03-05 21:19:46 +0200918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
919 int entries, prec_mult, drain_latency, pixel_size;
920 int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
Ville Syrjälä341c5262015-03-05 21:19:44 +0200921 const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300922
Ville Syrjälä883a3d22015-03-05 21:19:46 +0200923 /*
924 * FIXME the plane might have an fb
925 * but be invisible (eg. due to clipping)
926 */
927 if (!intel_crtc->active || !plane->state->fb)
928 return 0;
929
Gajanan Bhat0948c262014-08-07 01:58:24 +0530930 if (WARN(clock == 0, "Pixel clock is zero!\n"))
Ville Syrjälä341c5262015-03-05 21:19:44 +0200931 return 0;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300932
Ville Syrjälä883a3d22015-03-05 21:19:46 +0200933 pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
934
Gajanan Bhat0948c262014-08-07 01:58:24 +0530935 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
Ville Syrjälä341c5262015-03-05 21:19:44 +0200936 return 0;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300937
Gajanan Bhata398e9c2014-08-05 23:15:54 +0530938 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
Ville Syrjäläabfc00b2015-03-05 21:19:43 +0200939
Ville Syrjälä341c5262015-03-05 21:19:44 +0200940 prec_mult = high_precision;
941 drain_latency = 64 * prec_mult * 4 / entries;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300942
Ville Syrjälä341c5262015-03-05 21:19:44 +0200943 if (drain_latency > DRAIN_LATENCY_MASK) {
944 prec_mult /= 2;
945 drain_latency = 64 * prec_mult * 4 / entries;
Ville Syrjäläabfc00b2015-03-05 21:19:43 +0200946 }
947
Ville Syrjälä341c5262015-03-05 21:19:44 +0200948 if (drain_latency > DRAIN_LATENCY_MASK)
949 drain_latency = DRAIN_LATENCY_MASK;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300950
Ville Syrjälä341c5262015-03-05 21:19:44 +0200951 return drain_latency | (prec_mult == high_precision ?
952 DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300953}
954
Ville Syrjäläae801522015-03-05 21:19:49 +0200955static int vlv_compute_wm(struct intel_crtc *crtc,
956 struct intel_plane *plane,
957 int fifo_size)
958{
959 int clock, entries, pixel_size;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300960
Ville Syrjäläae801522015-03-05 21:19:49 +0200961 /*
962 * FIXME the plane might have an fb
963 * but be invisible (eg. due to clipping)
964 */
965 if (!crtc->active || !plane->base.state->fb)
966 return 0;
967
968 pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);
969 clock = crtc->config->base.adjusted_mode.crtc_clock;
970
971 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
972
973 /*
974 * Set up the watermark such that we don't start issuing memory
975 * requests until we are within PND's max deadline value (256us).
976 * Idea being to be idle as long as possible while still taking
977 * advatange of PND's deadline scheduling. The limit of 8
978 * cachelines (used when the FIFO will anyway drain in less time
979 * than 256us) should match what we would be done if trickle
980 * feed were enabled.
981 */
982 return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);
983}
984
985static bool vlv_compute_sr_wm(struct drm_device *dev,
986 struct vlv_wm_values *wm)
987{
988 struct drm_i915_private *dev_priv = to_i915(dev);
989 struct drm_crtc *crtc;
990 enum pipe pipe = INVALID_PIPE;
991 int num_planes = 0;
992 int fifo_size = 0;
993 struct intel_plane *plane;
994
995 wm->sr.cursor = wm->sr.plane = 0;
996
997 crtc = single_enabled_crtc(dev);
998 /* maxfifo not supported on pipe C */
999 if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {
1000 pipe = to_intel_crtc(crtc)->pipe;
1001 num_planes = !!wm->pipe[pipe].primary +
1002 !!wm->pipe[pipe].sprite[0] +
1003 !!wm->pipe[pipe].sprite[1];
1004 fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1005 }
1006
1007 if (fifo_size == 0 || num_planes > 1)
1008 return false;
1009
1010 wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
1011 to_intel_plane(crtc->cursor), 0x3f);
1012
1013 list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
1014 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1015 continue;
1016
1017 if (plane->pipe != pipe)
1018 continue;
1019
1020 wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
1021 plane, fifo_size);
1022 if (wm->sr.plane != 0)
1023 break;
1024 }
1025
1026 return true;
1027}
1028
1029static void valleyview_update_wm(struct drm_crtc *crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001030{
Rodrigo Vivi5e56ba42014-10-17 08:05:08 -07001031 struct drm_device *dev = crtc->dev;
1032 struct drm_i915_private *dev_priv = dev->dev_private;
Gajanan Bhat0948c262014-08-07 01:58:24 +05301033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Gajanan Bhat0948c262014-08-07 01:58:24 +05301034 enum pipe pipe = intel_crtc->pipe;
Ville Syrjäläae801522015-03-05 21:19:49 +02001035 bool cxsr_enabled;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001036 struct vlv_wm_values wm = dev_priv->wm.vlv;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001037
Ville Syrjälä883a3d22015-03-05 21:19:46 +02001038 wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
Ville Syrjäläae801522015-03-05 21:19:49 +02001039 wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,
1040 to_intel_plane(crtc->primary),
1041 vlv_get_fifo_size(dev, pipe, 0));
1042
Ville Syrjälä883a3d22015-03-05 21:19:46 +02001043 wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
Ville Syrjäläae801522015-03-05 21:19:49 +02001044 wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,
1045 to_intel_plane(crtc->cursor),
1046 0x3f);
1047
1048 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1049
1050 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1051 return;
1052
1053 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1054 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1055 wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1056 wm.sr.plane, wm.sr.cursor);
1057
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +02001058 /*
1059 * FIXME DDR DVFS introduces massive memory latencies which
1060 * are not known to system agent so any deadline specified
1061 * by the display may not be respected. To support DDR DVFS
1062 * the watermark code needs to be rewritten to essentially
1063 * bypass deadline mechanism and rely solely on the
1064 * watermarks. For now disable DDR DVFS.
1065 */
1066 if (IS_CHERRYVIEW(dev_priv))
1067 chv_set_memory_dvfs(dev_priv, false);
1068
Ville Syrjäläae801522015-03-05 21:19:49 +02001069 if (!cxsr_enabled)
1070 intel_set_memory_cxsr(dev_priv, false);
Gajanan Bhat0948c262014-08-07 01:58:24 +05301071
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001072 vlv_write_wm_values(intel_crtc, &wm);
Ville Syrjälä3c2777f2014-06-26 17:03:06 +03001073
1074 if (cxsr_enabled)
1075 intel_set_memory_cxsr(dev_priv, true);
1076}
1077
Gajanan Bhat01e184c2014-08-07 17:03:30 +05301078static void valleyview_update_sprite_wm(struct drm_plane *plane,
1079 struct drm_crtc *crtc,
1080 uint32_t sprite_width,
1081 uint32_t sprite_height,
1082 int pixel_size,
1083 bool enabled, bool scaled)
1084{
1085 struct drm_device *dev = crtc->dev;
1086 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1088 enum pipe pipe = intel_crtc->pipe;
Gajanan Bhat01e184c2014-08-07 17:03:30 +05301089 int sprite = to_intel_plane(plane)->plane;
Ville Syrjäläae801522015-03-05 21:19:49 +02001090 bool cxsr_enabled;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001091 struct vlv_wm_values wm = dev_priv->wm.vlv;
Gajanan Bhat01e184c2014-08-07 17:03:30 +05301092
Ville Syrjäläae801522015-03-05 21:19:49 +02001093 if (enabled) {
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001094 wm.ddl[pipe].sprite[sprite] =
Ville Syrjälä883a3d22015-03-05 21:19:46 +02001095 vlv_compute_drain_latency(crtc, plane);
Ville Syrjäläae801522015-03-05 21:19:49 +02001096
1097 wm.pipe[pipe].sprite[sprite] =
1098 vlv_compute_wm(intel_crtc,
1099 to_intel_plane(plane),
1100 vlv_get_fifo_size(dev, pipe, sprite+1));
1101 } else {
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001102 wm.ddl[pipe].sprite[sprite] = 0;
Ville Syrjäläae801522015-03-05 21:19:49 +02001103 wm.pipe[pipe].sprite[sprite] = 0;
1104 }
1105
1106 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1107
1108 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1109 return;
1110
1111 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, "
1112 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1113 sprite_name(pipe, sprite),
1114 wm.pipe[pipe].sprite[sprite],
1115 wm.sr.plane, wm.sr.cursor);
1116
1117 if (!cxsr_enabled)
1118 intel_set_memory_cxsr(dev_priv, false);
Gajanan Bhat01e184c2014-08-07 17:03:30 +05301119
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001120 vlv_write_wm_values(intel_crtc, &wm);
Ville Syrjäläae801522015-03-05 21:19:49 +02001121
1122 if (cxsr_enabled)
1123 intel_set_memory_cxsr(dev_priv, true);
Gajanan Bhat01e184c2014-08-07 17:03:30 +05301124}
1125
Ville Syrjäläae801522015-03-05 21:19:49 +02001126#define single_plane_enabled(mask) is_power_of_2(mask)
1127
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001128static void g4x_update_wm(struct drm_crtc *crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001129{
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001130 struct drm_device *dev = crtc->dev;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001131 static const int sr_latency_ns = 12000;
1132 struct drm_i915_private *dev_priv = dev->dev_private;
1133 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1134 int plane_sr, cursor_sr;
1135 unsigned int enabled = 0;
Imre Deak98584252014-06-13 14:54:20 +03001136 bool cxsr_enabled;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001137
Ville Syrjälä51cea1f2013-03-21 13:10:44 +02001138 if (g4x_compute_wm0(dev, PIPE_A,
Chris Wilson5aef6002014-09-03 11:56:07 +01001139 &g4x_wm_info, pessimal_latency_ns,
1140 &g4x_cursor_wm_info, pessimal_latency_ns,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001141 &planea_wm, &cursora_wm))
Ville Syrjälä51cea1f2013-03-21 13:10:44 +02001142 enabled |= 1 << PIPE_A;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001143
Ville Syrjälä51cea1f2013-03-21 13:10:44 +02001144 if (g4x_compute_wm0(dev, PIPE_B,
Chris Wilson5aef6002014-09-03 11:56:07 +01001145 &g4x_wm_info, pessimal_latency_ns,
1146 &g4x_cursor_wm_info, pessimal_latency_ns,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001147 &planeb_wm, &cursorb_wm))
Ville Syrjälä51cea1f2013-03-21 13:10:44 +02001148 enabled |= 1 << PIPE_B;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001149
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001150 if (single_plane_enabled(enabled) &&
1151 g4x_compute_srwm(dev, ffs(enabled) - 1,
1152 sr_latency_ns,
1153 &g4x_wm_info,
1154 &g4x_cursor_wm_info,
Chris Wilson52bd02d2012-12-07 10:43:24 +00001155 &plane_sr, &cursor_sr)) {
Imre Deak98584252014-06-13 14:54:20 +03001156 cxsr_enabled = true;
Chris Wilson52bd02d2012-12-07 10:43:24 +00001157 } else {
Imre Deak98584252014-06-13 14:54:20 +03001158 cxsr_enabled = false;
Imre Deak5209b1f2014-07-01 12:36:17 +03001159 intel_set_memory_cxsr(dev_priv, false);
Chris Wilson52bd02d2012-12-07 10:43:24 +00001160 plane_sr = cursor_sr = 0;
1161 }
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001162
Ville Syrjäläa5043452014-06-28 02:04:18 +03001163 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1164 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001165 planea_wm, cursora_wm,
1166 planeb_wm, cursorb_wm,
1167 plane_sr, cursor_sr);
1168
1169 I915_WRITE(DSPFW1,
Ville Syrjäläf4998962015-03-10 17:02:21 +02001170 FW_WM(plane_sr, SR) |
1171 FW_WM(cursorb_wm, CURSORB) |
1172 FW_WM(planeb_wm, PLANEB) |
1173 FW_WM(planea_wm, PLANEA));
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001174 I915_WRITE(DSPFW2,
Chris Wilson8c919b22012-12-04 16:33:19 +00001175 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
Ville Syrjäläf4998962015-03-10 17:02:21 +02001176 FW_WM(cursora_wm, CURSORA));
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001177 /* HPLL off in SR has some issues on G4x... disable it */
1178 I915_WRITE(DSPFW3,
Chris Wilson8c919b22012-12-04 16:33:19 +00001179 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
Ville Syrjäläf4998962015-03-10 17:02:21 +02001180 FW_WM(cursor_sr, CURSOR_SR));
Imre Deak98584252014-06-13 14:54:20 +03001181
1182 if (cxsr_enabled)
1183 intel_set_memory_cxsr(dev_priv, true);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001184}
1185
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001186static void i965_update_wm(struct drm_crtc *unused_crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001187{
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001188 struct drm_device *dev = unused_crtc->dev;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001189 struct drm_i915_private *dev_priv = dev->dev_private;
1190 struct drm_crtc *crtc;
1191 int srwm = 1;
1192 int cursor_sr = 16;
Imre Deak98584252014-06-13 14:54:20 +03001193 bool cxsr_enabled;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001194
1195 /* Calc sr entries for one plane configs */
1196 crtc = single_enabled_crtc(dev);
1197 if (crtc) {
1198 /* self-refresh has much higher latency */
1199 static const int sr_latency_ns = 12000;
Ville Syrjälä4fe85902013-09-04 18:25:22 +03001200 const struct drm_display_mode *adjusted_mode =
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001201 &to_intel_crtc(crtc)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +01001202 int clock = adjusted_mode->crtc_clock;
Jesse Barnesfec8cba2013-11-27 11:10:26 -08001203 int htotal = adjusted_mode->crtc_htotal;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001204 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
Matt Roper59bea882015-02-27 10:12:01 -08001205 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001206 unsigned long line_time_us;
1207 int entries;
1208
Ville Syrjälä922044c2014-02-14 14:18:57 +02001209 line_time_us = max(htotal * 1000 / clock, 1);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001210
1211 /* Use ns/us then divide to preserve precision */
1212 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1213 pixel_size * hdisplay;
1214 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1215 srwm = I965_FIFO_SIZE - entries;
1216 if (srwm < 0)
1217 srwm = 1;
1218 srwm &= 0x1ff;
1219 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1220 entries, srwm);
1221
1222 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
Matt Roper3dd512f2015-02-27 10:12:00 -08001223 pixel_size * crtc->cursor->state->crtc_w;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001224 entries = DIV_ROUND_UP(entries,
1225 i965_cursor_wm_info.cacheline_size);
1226 cursor_sr = i965_cursor_wm_info.fifo_size -
1227 (entries + i965_cursor_wm_info.guard_size);
1228
1229 if (cursor_sr > i965_cursor_wm_info.max_wm)
1230 cursor_sr = i965_cursor_wm_info.max_wm;
1231
1232 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1233 "cursor %d\n", srwm, cursor_sr);
1234
Imre Deak98584252014-06-13 14:54:20 +03001235 cxsr_enabled = true;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001236 } else {
Imre Deak98584252014-06-13 14:54:20 +03001237 cxsr_enabled = false;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001238 /* Turn off self refresh if both pipes are enabled */
Imre Deak5209b1f2014-07-01 12:36:17 +03001239 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001240 }
1241
1242 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1243 srwm);
1244
1245 /* 965 has limitations... */
Ville Syrjäläf4998962015-03-10 17:02:21 +02001246 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1247 FW_WM(8, CURSORB) |
1248 FW_WM(8, PLANEB) |
1249 FW_WM(8, PLANEA));
1250 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1251 FW_WM(8, PLANEC_OLD));
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001252 /* update cursor SR watermark */
Ville Syrjäläf4998962015-03-10 17:02:21 +02001253 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
Imre Deak98584252014-06-13 14:54:20 +03001254
1255 if (cxsr_enabled)
1256 intel_set_memory_cxsr(dev_priv, true);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001257}
1258
Ville Syrjäläf4998962015-03-10 17:02:21 +02001259#undef FW_WM
1260
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001261static void i9xx_update_wm(struct drm_crtc *unused_crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001262{
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001263 struct drm_device *dev = unused_crtc->dev;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001264 struct drm_i915_private *dev_priv = dev->dev_private;
1265 const struct intel_watermark_params *wm_info;
1266 uint32_t fwater_lo;
1267 uint32_t fwater_hi;
1268 int cwm, srwm = 1;
1269 int fifo_size;
1270 int planea_wm, planeb_wm;
1271 struct drm_crtc *crtc, *enabled = NULL;
1272
1273 if (IS_I945GM(dev))
1274 wm_info = &i945_wm_info;
1275 else if (!IS_GEN2(dev))
1276 wm_info = &i915_wm_info;
1277 else
Ville Syrjälä9d539102014-08-15 01:21:53 +03001278 wm_info = &i830_a_wm_info;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001279
1280 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1281 crtc = intel_get_crtc_for_plane(dev, 0);
Chris Wilson3490ea52013-01-07 10:11:40 +00001282 if (intel_crtc_active(crtc)) {
Damien Lespiau241bfc32013-09-25 16:45:37 +01001283 const struct drm_display_mode *adjusted_mode;
Matt Roper59bea882015-02-27 10:12:01 -08001284 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01001285 if (IS_GEN2(dev))
1286 cpp = 4;
1287
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001288 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +01001289 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01001290 wm_info, fifo_size, cpp,
Chris Wilson5aef6002014-09-03 11:56:07 +01001291 pessimal_latency_ns);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001292 enabled = crtc;
Ville Syrjälä9d539102014-08-15 01:21:53 +03001293 } else {
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001294 planea_wm = fifo_size - wm_info->guard_size;
Ville Syrjälä9d539102014-08-15 01:21:53 +03001295 if (planea_wm > (long)wm_info->max_wm)
1296 planea_wm = wm_info->max_wm;
1297 }
1298
1299 if (IS_GEN2(dev))
1300 wm_info = &i830_bc_wm_info;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001301
1302 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1303 crtc = intel_get_crtc_for_plane(dev, 1);
Chris Wilson3490ea52013-01-07 10:11:40 +00001304 if (intel_crtc_active(crtc)) {
Damien Lespiau241bfc32013-09-25 16:45:37 +01001305 const struct drm_display_mode *adjusted_mode;
Matt Roper59bea882015-02-27 10:12:01 -08001306 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01001307 if (IS_GEN2(dev))
1308 cpp = 4;
1309
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001310 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +01001311 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01001312 wm_info, fifo_size, cpp,
Chris Wilson5aef6002014-09-03 11:56:07 +01001313 pessimal_latency_ns);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001314 if (enabled == NULL)
1315 enabled = crtc;
1316 else
1317 enabled = NULL;
Ville Syrjälä9d539102014-08-15 01:21:53 +03001318 } else {
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001319 planeb_wm = fifo_size - wm_info->guard_size;
Ville Syrjälä9d539102014-08-15 01:21:53 +03001320 if (planeb_wm > (long)wm_info->max_wm)
1321 planeb_wm = wm_info->max_wm;
1322 }
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001323
1324 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1325
Daniel Vetter2ab1bc92014-04-07 08:54:21 +02001326 if (IS_I915GM(dev) && enabled) {
Matt Roper2ff8fde2014-07-08 07:50:07 -07001327 struct drm_i915_gem_object *obj;
Daniel Vetter2ab1bc92014-04-07 08:54:21 +02001328
Matt Roper59bea882015-02-27 10:12:01 -08001329 obj = intel_fb_obj(enabled->primary->state->fb);
Daniel Vetter2ab1bc92014-04-07 08:54:21 +02001330
1331 /* self-refresh seems busted with untiled */
Matt Roper2ff8fde2014-07-08 07:50:07 -07001332 if (obj->tiling_mode == I915_TILING_NONE)
Daniel Vetter2ab1bc92014-04-07 08:54:21 +02001333 enabled = NULL;
1334 }
1335
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001336 /*
1337 * Overlay gets an aggressive default since video jitter is bad.
1338 */
1339 cwm = 2;
1340
1341 /* Play safe and disable self-refresh before adjusting watermarks. */
Imre Deak5209b1f2014-07-01 12:36:17 +03001342 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001343
1344 /* Calc sr entries for one plane configs */
1345 if (HAS_FW_BLC(dev) && enabled) {
1346 /* self-refresh has much higher latency */
1347 static const int sr_latency_ns = 6000;
Ville Syrjälä4fe85902013-09-04 18:25:22 +03001348 const struct drm_display_mode *adjusted_mode =
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001349 &to_intel_crtc(enabled)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +01001350 int clock = adjusted_mode->crtc_clock;
Jesse Barnesfec8cba2013-11-27 11:10:26 -08001351 int htotal = adjusted_mode->crtc_htotal;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001352 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
Matt Roper59bea882015-02-27 10:12:01 -08001353 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001354 unsigned long line_time_us;
1355 int entries;
1356
Ville Syrjälä922044c2014-02-14 14:18:57 +02001357 line_time_us = max(htotal * 1000 / clock, 1);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001358
1359 /* Use ns/us then divide to preserve precision */
1360 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1361 pixel_size * hdisplay;
1362 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1363 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1364 srwm = wm_info->fifo_size - entries;
1365 if (srwm < 0)
1366 srwm = 1;
1367
1368 if (IS_I945G(dev) || IS_I945GM(dev))
1369 I915_WRITE(FW_BLC_SELF,
1370 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1371 else if (IS_I915GM(dev))
1372 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1373 }
1374
1375 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1376 planea_wm, planeb_wm, cwm, srwm);
1377
1378 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1379 fwater_hi = (cwm & 0x1f);
1380
1381 /* Set request length to 8 cachelines per fetch */
1382 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1383 fwater_hi = fwater_hi | (1 << 8);
1384
1385 I915_WRITE(FW_BLC, fwater_lo);
1386 I915_WRITE(FW_BLC2, fwater_hi);
1387
Imre Deak5209b1f2014-07-01 12:36:17 +03001388 if (enabled)
1389 intel_set_memory_cxsr(dev_priv, true);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001390}
1391
Daniel Vetterfeb56b92013-12-14 20:38:30 -02001392static void i845_update_wm(struct drm_crtc *unused_crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001393{
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001394 struct drm_device *dev = unused_crtc->dev;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 struct drm_crtc *crtc;
Damien Lespiau241bfc32013-09-25 16:45:37 +01001397 const struct drm_display_mode *adjusted_mode;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001398 uint32_t fwater_lo;
1399 int planea_wm;
1400
1401 crtc = single_enabled_crtc(dev);
1402 if (crtc == NULL)
1403 return;
1404
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001405 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +01001406 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
Daniel Vetterfeb56b92013-12-14 20:38:30 -02001407 &i845_wm_info,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001408 dev_priv->display.get_fifo_size(dev, 0),
Chris Wilson5aef6002014-09-03 11:56:07 +01001409 4, pessimal_latency_ns);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001410 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1411 fwater_lo |= (3<<8) | planea_wm;
1412
1413 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1414
1415 I915_WRITE(FW_BLC, fwater_lo);
1416}
1417
Ville Syrjälä36587292013-07-05 11:57:16 +03001418static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1419 struct drm_crtc *crtc)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001420{
1421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilsonfd4daa92013-08-27 17:04:17 +01001422 uint32_t pixel_rate;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001423
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001424 pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001425
1426 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1427 * adjust the pixel_rate here. */
1428
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001429 if (intel_crtc->config->pch_pfit.enabled) {
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001430 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001431 uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001432
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001433 pipe_w = intel_crtc->config->pipe_src_w;
1434 pipe_h = intel_crtc->config->pipe_src_h;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001435 pfit_w = (pfit_size >> 16) & 0xFFFF;
1436 pfit_h = pfit_size & 0xFFFF;
1437 if (pipe_w < pfit_w)
1438 pipe_w = pfit_w;
1439 if (pipe_h < pfit_h)
1440 pipe_h = pfit_h;
1441
1442 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1443 pfit_w * pfit_h);
1444 }
1445
1446 return pixel_rate;
1447}
1448
Ville Syrjälä37126462013-08-01 16:18:55 +03001449/* latency must be in 0.1us units. */
Ville Syrjälä23297042013-07-05 11:57:17 +03001450static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001451 uint32_t latency)
1452{
1453 uint64_t ret;
1454
Ville Syrjälä3312ba62013-08-01 16:18:53 +03001455 if (WARN(latency == 0, "Latency value missing\n"))
1456 return UINT_MAX;
1457
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001458 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1459 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1460
1461 return ret;
1462}
1463
Ville Syrjälä37126462013-08-01 16:18:55 +03001464/* latency must be in 0.1us units. */
Ville Syrjälä23297042013-07-05 11:57:17 +03001465static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001466 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1467 uint32_t latency)
1468{
1469 uint32_t ret;
1470
Ville Syrjälä3312ba62013-08-01 16:18:53 +03001471 if (WARN(latency == 0, "Latency value missing\n"))
1472 return UINT_MAX;
1473
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001474 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1475 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1476 ret = DIV_ROUND_UP(ret, 64) + 2;
1477 return ret;
1478}
1479
Ville Syrjälä23297042013-07-05 11:57:17 +03001480static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
Paulo Zanonicca32e92013-05-31 11:45:06 -03001481 uint8_t bytes_per_pixel)
1482{
1483 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1484}
1485
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001486struct skl_pipe_wm_parameters {
1487 bool active;
1488 uint32_t pipe_htotal;
1489 uint32_t pixel_rate; /* in KHz */
1490 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1491 struct intel_plane_wm_parameters cursor;
1492};
1493
Imre Deak820c1982013-12-17 14:46:36 +02001494struct ilk_pipe_wm_parameters {
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001495 bool active;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001496 uint32_t pipe_htotal;
1497 uint32_t pixel_rate;
Ville Syrjäläc35426d2013-08-07 13:29:50 +03001498 struct intel_plane_wm_parameters pri;
1499 struct intel_plane_wm_parameters spr;
1500 struct intel_plane_wm_parameters cur;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001501};
1502
Imre Deak820c1982013-12-17 14:46:36 +02001503struct ilk_wm_maximums {
Paulo Zanonicca32e92013-05-31 11:45:06 -03001504 uint16_t pri;
1505 uint16_t spr;
1506 uint16_t cur;
1507 uint16_t fbc;
1508};
1509
Ville Syrjälä240264f2013-08-07 13:29:12 +03001510/* used in computing the new watermarks state */
1511struct intel_wm_config {
1512 unsigned int num_pipes_active;
1513 bool sprites_enabled;
1514 bool sprites_scaled;
Ville Syrjälä240264f2013-08-07 13:29:12 +03001515};
1516
Ville Syrjälä37126462013-08-01 16:18:55 +03001517/*
1518 * For both WM_PIPE and WM_LP.
1519 * mem_value must be in 0.1us units.
1520 */
Imre Deak820c1982013-12-17 14:46:36 +02001521static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
Paulo Zanonicca32e92013-05-31 11:45:06 -03001522 uint32_t mem_value,
1523 bool is_lp)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001524{
Paulo Zanonicca32e92013-05-31 11:45:06 -03001525 uint32_t method1, method2;
1526
Ville Syrjäläc35426d2013-08-07 13:29:50 +03001527 if (!params->active || !params->pri.enabled)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001528 return 0;
1529
Ville Syrjälä23297042013-07-05 11:57:17 +03001530 method1 = ilk_wm_method1(params->pixel_rate,
Ville Syrjäläc35426d2013-08-07 13:29:50 +03001531 params->pri.bytes_per_pixel,
Paulo Zanonicca32e92013-05-31 11:45:06 -03001532 mem_value);
1533
1534 if (!is_lp)
1535 return method1;
1536
Ville Syrjälä23297042013-07-05 11:57:17 +03001537 method2 = ilk_wm_method2(params->pixel_rate,
Paulo Zanonicca32e92013-05-31 11:45:06 -03001538 params->pipe_htotal,
Ville Syrjäläc35426d2013-08-07 13:29:50 +03001539 params->pri.horiz_pixels,
1540 params->pri.bytes_per_pixel,
Paulo Zanonicca32e92013-05-31 11:45:06 -03001541 mem_value);
1542
1543 return min(method1, method2);
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001544}
1545
Ville Syrjälä37126462013-08-01 16:18:55 +03001546/*
1547 * For both WM_PIPE and WM_LP.
1548 * mem_value must be in 0.1us units.
1549 */
Imre Deak820c1982013-12-17 14:46:36 +02001550static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001551 uint32_t mem_value)
1552{
1553 uint32_t method1, method2;
1554
Ville Syrjäläc35426d2013-08-07 13:29:50 +03001555 if (!params->active || !params->spr.enabled)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001556 return 0;
1557
Ville Syrjälä23297042013-07-05 11:57:17 +03001558 method1 = ilk_wm_method1(params->pixel_rate,
Ville Syrjäläc35426d2013-08-07 13:29:50 +03001559 params->spr.bytes_per_pixel,
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001560 mem_value);
Ville Syrjälä23297042013-07-05 11:57:17 +03001561 method2 = ilk_wm_method2(params->pixel_rate,
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001562 params->pipe_htotal,
Ville Syrjäläc35426d2013-08-07 13:29:50 +03001563 params->spr.horiz_pixels,
1564 params->spr.bytes_per_pixel,
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001565 mem_value);
1566 return min(method1, method2);
1567}
1568
Ville Syrjälä37126462013-08-01 16:18:55 +03001569/*
1570 * For both WM_PIPE and WM_LP.
1571 * mem_value must be in 0.1us units.
1572 */
Imre Deak820c1982013-12-17 14:46:36 +02001573static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001574 uint32_t mem_value)
1575{
Ville Syrjäläc35426d2013-08-07 13:29:50 +03001576 if (!params->active || !params->cur.enabled)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001577 return 0;
1578
Ville Syrjälä23297042013-07-05 11:57:17 +03001579 return ilk_wm_method2(params->pixel_rate,
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001580 params->pipe_htotal,
Ville Syrjäläc35426d2013-08-07 13:29:50 +03001581 params->cur.horiz_pixels,
1582 params->cur.bytes_per_pixel,
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001583 mem_value);
1584}
1585
Paulo Zanonicca32e92013-05-31 11:45:06 -03001586/* Only for WM_LP. */
Imre Deak820c1982013-12-17 14:46:36 +02001587static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
Ville Syrjälä1fda9882013-07-05 11:57:19 +03001588 uint32_t pri_val)
Paulo Zanonicca32e92013-05-31 11:45:06 -03001589{
Ville Syrjäläc35426d2013-08-07 13:29:50 +03001590 if (!params->active || !params->pri.enabled)
Paulo Zanonicca32e92013-05-31 11:45:06 -03001591 return 0;
1592
Ville Syrjälä23297042013-07-05 11:57:17 +03001593 return ilk_wm_fbc(pri_val,
Ville Syrjäläc35426d2013-08-07 13:29:50 +03001594 params->pri.horiz_pixels,
1595 params->pri.bytes_per_pixel);
Paulo Zanonicca32e92013-05-31 11:45:06 -03001596}
1597
Ville Syrjälä158ae642013-08-07 13:28:19 +03001598static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1599{
Ville Syrjälä416f4722013-11-02 21:07:46 -07001600 if (INTEL_INFO(dev)->gen >= 8)
1601 return 3072;
1602 else if (INTEL_INFO(dev)->gen >= 7)
Ville Syrjälä158ae642013-08-07 13:28:19 +03001603 return 768;
1604 else
1605 return 512;
1606}
1607
Ville Syrjälä4e975082014-03-07 18:32:11 +02001608static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1609 int level, bool is_sprite)
1610{
1611 if (INTEL_INFO(dev)->gen >= 8)
1612 /* BDW primary/sprite plane watermarks */
1613 return level == 0 ? 255 : 2047;
1614 else if (INTEL_INFO(dev)->gen >= 7)
1615 /* IVB/HSW primary/sprite plane watermarks */
1616 return level == 0 ? 127 : 1023;
1617 else if (!is_sprite)
1618 /* ILK/SNB primary plane watermarks */
1619 return level == 0 ? 127 : 511;
1620 else
1621 /* ILK/SNB sprite plane watermarks */
1622 return level == 0 ? 63 : 255;
1623}
1624
1625static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1626 int level)
1627{
1628 if (INTEL_INFO(dev)->gen >= 7)
1629 return level == 0 ? 63 : 255;
1630 else
1631 return level == 0 ? 31 : 63;
1632}
1633
1634static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1635{
1636 if (INTEL_INFO(dev)->gen >= 8)
1637 return 31;
1638 else
1639 return 15;
1640}
1641
Ville Syrjälä158ae642013-08-07 13:28:19 +03001642/* Calculate the maximum primary/sprite plane watermark */
1643static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1644 int level,
Ville Syrjälä240264f2013-08-07 13:29:12 +03001645 const struct intel_wm_config *config,
Ville Syrjälä158ae642013-08-07 13:28:19 +03001646 enum intel_ddb_partitioning ddb_partitioning,
1647 bool is_sprite)
1648{
1649 unsigned int fifo_size = ilk_display_fifo_size(dev);
Ville Syrjälä158ae642013-08-07 13:28:19 +03001650
1651 /* if sprites aren't enabled, sprites get nothing */
Ville Syrjälä240264f2013-08-07 13:29:12 +03001652 if (is_sprite && !config->sprites_enabled)
Ville Syrjälä158ae642013-08-07 13:28:19 +03001653 return 0;
1654
1655 /* HSW allows LP1+ watermarks even with multiple pipes */
Ville Syrjälä240264f2013-08-07 13:29:12 +03001656 if (level == 0 || config->num_pipes_active > 1) {
Ville Syrjälä158ae642013-08-07 13:28:19 +03001657 fifo_size /= INTEL_INFO(dev)->num_pipes;
1658
1659 /*
1660 * For some reason the non self refresh
1661 * FIFO size is only half of the self
1662 * refresh FIFO size on ILK/SNB.
1663 */
1664 if (INTEL_INFO(dev)->gen <= 6)
1665 fifo_size /= 2;
1666 }
1667
Ville Syrjälä240264f2013-08-07 13:29:12 +03001668 if (config->sprites_enabled) {
Ville Syrjälä158ae642013-08-07 13:28:19 +03001669 /* level 0 is always calculated with 1:1 split */
1670 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1671 if (is_sprite)
1672 fifo_size *= 5;
1673 fifo_size /= 6;
1674 } else {
1675 fifo_size /= 2;
1676 }
1677 }
1678
1679 /* clamp to max that the registers can hold */
Ville Syrjälä4e975082014-03-07 18:32:11 +02001680 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
Ville Syrjälä158ae642013-08-07 13:28:19 +03001681}
1682
1683/* Calculate the maximum cursor plane watermark */
1684static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
Ville Syrjälä240264f2013-08-07 13:29:12 +03001685 int level,
1686 const struct intel_wm_config *config)
Ville Syrjälä158ae642013-08-07 13:28:19 +03001687{
1688 /* HSW LP1+ watermarks w/ multiple pipes */
Ville Syrjälä240264f2013-08-07 13:29:12 +03001689 if (level > 0 && config->num_pipes_active > 1)
Ville Syrjälä158ae642013-08-07 13:28:19 +03001690 return 64;
1691
1692 /* otherwise just report max that registers can hold */
Ville Syrjälä4e975082014-03-07 18:32:11 +02001693 return ilk_cursor_wm_reg_max(dev, level);
Ville Syrjälä158ae642013-08-07 13:28:19 +03001694}
1695
Damien Lespiaud34ff9c2014-01-06 19:17:23 +00001696static void ilk_compute_wm_maximums(const struct drm_device *dev,
Ville Syrjälä34982fe2013-10-09 19:18:09 +03001697 int level,
1698 const struct intel_wm_config *config,
1699 enum intel_ddb_partitioning ddb_partitioning,
Imre Deak820c1982013-12-17 14:46:36 +02001700 struct ilk_wm_maximums *max)
Ville Syrjälä158ae642013-08-07 13:28:19 +03001701{
Ville Syrjälä240264f2013-08-07 13:29:12 +03001702 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1703 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1704 max->cur = ilk_cursor_wm_max(dev, level, config);
Ville Syrjälä4e975082014-03-07 18:32:11 +02001705 max->fbc = ilk_fbc_wm_reg_max(dev);
Ville Syrjälä158ae642013-08-07 13:28:19 +03001706}
1707
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03001708static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1709 int level,
1710 struct ilk_wm_maximums *max)
1711{
1712 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1713 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1714 max->cur = ilk_cursor_wm_reg_max(dev, level);
1715 max->fbc = ilk_fbc_wm_reg_max(dev);
1716}
1717
Ville Syrjäläd9395652013-10-09 19:18:10 +03001718static bool ilk_validate_wm_level(int level,
Imre Deak820c1982013-12-17 14:46:36 +02001719 const struct ilk_wm_maximums *max,
Ville Syrjäläd9395652013-10-09 19:18:10 +03001720 struct intel_wm_level *result)
Ville Syrjäläa9786a12013-08-07 13:24:47 +03001721{
1722 bool ret;
1723
1724 /* already determined to be invalid? */
1725 if (!result->enable)
1726 return false;
1727
1728 result->enable = result->pri_val <= max->pri &&
1729 result->spr_val <= max->spr &&
1730 result->cur_val <= max->cur;
1731
1732 ret = result->enable;
1733
1734 /*
1735 * HACK until we can pre-compute everything,
1736 * and thus fail gracefully if LP0 watermarks
1737 * are exceeded...
1738 */
1739 if (level == 0 && !result->enable) {
1740 if (result->pri_val > max->pri)
1741 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1742 level, result->pri_val, max->pri);
1743 if (result->spr_val > max->spr)
1744 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1745 level, result->spr_val, max->spr);
1746 if (result->cur_val > max->cur)
1747 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1748 level, result->cur_val, max->cur);
1749
1750 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1751 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1752 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1753 result->enable = true;
1754 }
1755
Ville Syrjäläa9786a12013-08-07 13:24:47 +03001756 return ret;
1757}
1758
Damien Lespiaud34ff9c2014-01-06 19:17:23 +00001759static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
Ville Syrjälä6f5ddd12013-08-06 22:24:02 +03001760 int level,
Imre Deak820c1982013-12-17 14:46:36 +02001761 const struct ilk_pipe_wm_parameters *p,
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03001762 struct intel_wm_level *result)
Ville Syrjälä6f5ddd12013-08-06 22:24:02 +03001763{
1764 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1765 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1766 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1767
1768 /* WM1+ latency values stored in 0.5us units */
1769 if (level > 0) {
1770 pri_latency *= 5;
1771 spr_latency *= 5;
1772 cur_latency *= 5;
1773 }
1774
1775 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1776 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1777 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1778 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1779 result->enable = true;
1780}
1781
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001782static uint32_t
1783hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03001784{
1785 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03001786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001787 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
Paulo Zanoni85a02de2013-05-03 17:23:43 -03001788 u32 linetime, ips_linetime;
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03001789
Matt Roper3ef00282015-03-09 10:19:24 -07001790 if (!intel_crtc->active)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001791 return 0;
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03001792
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03001793 /* The WM are computed with base on how long it takes to fill a single
1794 * row at the given clock rate, multiplied by 8.
1795 * */
Jesse Barnesfec8cba2013-11-27 11:10:26 -08001796 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1797 mode->crtc_clock);
1798 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
Ville Syrjälä1652d192015-03-31 14:12:01 +03001799 dev_priv->display.get_display_clock_speed(dev_priv->dev));
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03001800
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001801 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1802 PIPE_WM_LINETIME_TIME(linetime);
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03001803}
1804
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001805static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
Ville Syrjälä12b134d2013-07-05 11:57:21 +03001806{
1807 struct drm_i915_private *dev_priv = dev->dev_private;
1808
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001809 if (IS_GEN9(dev)) {
1810 uint32_t val;
Vandana Kannan4f947382014-11-04 17:06:47 +00001811 int ret, i;
Vandana Kannan367294b2014-11-04 17:06:46 +00001812 int level, max_level = ilk_wm_max_level(dev);
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001813
1814 /* read the first set of memory latencies[0:3] */
1815 val = 0; /* data0 to be programmed to 0 for first set */
1816 mutex_lock(&dev_priv->rps.hw_lock);
1817 ret = sandybridge_pcode_read(dev_priv,
1818 GEN9_PCODE_READ_MEM_LATENCY,
1819 &val);
1820 mutex_unlock(&dev_priv->rps.hw_lock);
1821
1822 if (ret) {
1823 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1824 return;
1825 }
1826
1827 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1828 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1829 GEN9_MEM_LATENCY_LEVEL_MASK;
1830 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1831 GEN9_MEM_LATENCY_LEVEL_MASK;
1832 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1833 GEN9_MEM_LATENCY_LEVEL_MASK;
1834
1835 /* read the second set of memory latencies[4:7] */
1836 val = 1; /* data0 to be programmed to 1 for second set */
1837 mutex_lock(&dev_priv->rps.hw_lock);
1838 ret = sandybridge_pcode_read(dev_priv,
1839 GEN9_PCODE_READ_MEM_LATENCY,
1840 &val);
1841 mutex_unlock(&dev_priv->rps.hw_lock);
1842 if (ret) {
1843 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1844 return;
1845 }
1846
1847 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1848 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1849 GEN9_MEM_LATENCY_LEVEL_MASK;
1850 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1851 GEN9_MEM_LATENCY_LEVEL_MASK;
1852 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1853 GEN9_MEM_LATENCY_LEVEL_MASK;
1854
Vandana Kannan367294b2014-11-04 17:06:46 +00001855 /*
Damien Lespiau6f972352015-02-09 19:33:07 +00001856 * WaWmMemoryReadLatency:skl
1857 *
Vandana Kannan367294b2014-11-04 17:06:46 +00001858 * punit doesn't take into account the read latency so we need
1859 * to add 2us to the various latency levels we retrieve from
1860 * the punit.
1861 * - W0 is a bit special in that it's the only level that
1862 * can't be disabled if we want to have display working, so
1863 * we always add 2us there.
1864 * - For levels >=1, punit returns 0us latency when they are
1865 * disabled, so we respect that and don't add 2us then
Vandana Kannan4f947382014-11-04 17:06:47 +00001866 *
1867 * Additionally, if a level n (n > 1) has a 0us latency, all
1868 * levels m (m >= n) need to be disabled. We make sure to
1869 * sanitize the values out of the punit to satisfy this
1870 * requirement.
Vandana Kannan367294b2014-11-04 17:06:46 +00001871 */
1872 wm[0] += 2;
1873 for (level = 1; level <= max_level; level++)
1874 if (wm[level] != 0)
1875 wm[level] += 2;
Vandana Kannan4f947382014-11-04 17:06:47 +00001876 else {
1877 for (i = level + 1; i <= max_level; i++)
1878 wm[i] = 0;
Vandana Kannan367294b2014-11-04 17:06:46 +00001879
Vandana Kannan4f947382014-11-04 17:06:47 +00001880 break;
1881 }
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001882 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Ville Syrjälä12b134d2013-07-05 11:57:21 +03001883 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1884
1885 wm[0] = (sskpd >> 56) & 0xFF;
1886 if (wm[0] == 0)
1887 wm[0] = sskpd & 0xF;
Ville Syrjäläe5d50192013-07-05 11:57:22 +03001888 wm[1] = (sskpd >> 4) & 0xFF;
1889 wm[2] = (sskpd >> 12) & 0xFF;
1890 wm[3] = (sskpd >> 20) & 0x1FF;
1891 wm[4] = (sskpd >> 32) & 0x1FF;
Ville Syrjälä63cf9a12013-07-05 11:57:23 +03001892 } else if (INTEL_INFO(dev)->gen >= 6) {
1893 uint32_t sskpd = I915_READ(MCH_SSKPD);
1894
1895 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1896 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1897 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1898 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
Ville Syrjälä3a88d0a2013-08-01 16:18:49 +03001899 } else if (INTEL_INFO(dev)->gen >= 5) {
1900 uint32_t mltr = I915_READ(MLTR_ILK);
1901
1902 /* ILK primary LP0 latency is 700 ns */
1903 wm[0] = 7;
1904 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1905 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
Ville Syrjälä12b134d2013-07-05 11:57:21 +03001906 }
1907}
1908
Ville Syrjälä53615a52013-08-01 16:18:50 +03001909static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1910{
1911 /* ILK sprite LP0 latency is 1300 ns */
1912 if (INTEL_INFO(dev)->gen == 5)
1913 wm[0] = 13;
1914}
1915
1916static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1917{
1918 /* ILK cursor LP0 latency is 1300 ns */
1919 if (INTEL_INFO(dev)->gen == 5)
1920 wm[0] = 13;
1921
1922 /* WaDoubleCursorLP3Latency:ivb */
1923 if (IS_IVYBRIDGE(dev))
1924 wm[3] *= 2;
1925}
1926
Damien Lespiau546c81f2014-05-13 15:30:26 +01001927int ilk_wm_max_level(const struct drm_device *dev)
Ville Syrjäläad0d6dc2013-08-30 14:30:25 +03001928{
1929 /* how many WM levels are we expecting */
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001930 if (IS_GEN9(dev))
1931 return 7;
1932 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Ville Syrjäläad0d6dc2013-08-30 14:30:25 +03001933 return 4;
1934 else if (INTEL_INFO(dev)->gen >= 6)
1935 return 3;
1936 else
1937 return 2;
1938}
Daniel Vetter7526ed72014-09-29 15:07:19 +02001939
Ville Syrjälä26ec9712013-08-01 16:18:52 +03001940static void intel_print_wm_latency(struct drm_device *dev,
1941 const char *name,
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001942 const uint16_t wm[8])
Ville Syrjälä26ec9712013-08-01 16:18:52 +03001943{
Ville Syrjäläad0d6dc2013-08-30 14:30:25 +03001944 int level, max_level = ilk_wm_max_level(dev);
Ville Syrjälä26ec9712013-08-01 16:18:52 +03001945
1946 for (level = 0; level <= max_level; level++) {
1947 unsigned int latency = wm[level];
1948
1949 if (latency == 0) {
1950 DRM_ERROR("%s WM%d latency not provided\n",
1951 name, level);
1952 continue;
1953 }
1954
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001955 /*
1956 * - latencies are in us on gen9.
1957 * - before then, WM1+ latency values are in 0.5us units
1958 */
1959 if (IS_GEN9(dev))
1960 latency *= 10;
1961 else if (level > 0)
Ville Syrjälä26ec9712013-08-01 16:18:52 +03001962 latency *= 5;
1963
1964 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1965 name, level, wm[level],
1966 latency / 10, latency % 10);
1967 }
1968}
1969
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03001970static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1971 uint16_t wm[5], uint16_t min)
1972{
1973 int level, max_level = ilk_wm_max_level(dev_priv->dev);
1974
1975 if (wm[0] >= min)
1976 return false;
1977
1978 wm[0] = max(wm[0], min);
1979 for (level = 1; level <= max_level; level++)
1980 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
1981
1982 return true;
1983}
1984
1985static void snb_wm_latency_quirk(struct drm_device *dev)
1986{
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 bool changed;
1989
1990 /*
1991 * The BIOS provided WM memory latency values are often
1992 * inadequate for high resolution displays. Adjust them.
1993 */
1994 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
1995 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
1996 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
1997
1998 if (!changed)
1999 return;
2000
2001 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2002 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2003 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2004 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2005}
2006
Damien Lespiaufa50ad62014-03-17 18:01:16 +00002007static void ilk_setup_wm_latency(struct drm_device *dev)
Ville Syrjälä53615a52013-08-01 16:18:50 +03002008{
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010
2011 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2012
2013 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2014 sizeof(dev_priv->wm.pri_latency));
2015 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2016 sizeof(dev_priv->wm.pri_latency));
2017
2018 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2019 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
Ville Syrjälä26ec9712013-08-01 16:18:52 +03002020
2021 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2022 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2023 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03002024
2025 if (IS_GEN6(dev))
2026 snb_wm_latency_quirk(dev);
Ville Syrjälä53615a52013-08-01 16:18:50 +03002027}
2028
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002029static void skl_setup_wm_latency(struct drm_device *dev)
2030{
2031 struct drm_i915_private *dev_priv = dev->dev_private;
2032
2033 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2034 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2035}
2036
Imre Deak820c1982013-12-17 14:46:36 +02002037static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
Ville Syrjälä2a44b762014-03-07 18:32:09 +02002038 struct ilk_pipe_wm_parameters *p)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002039{
Ville Syrjälä7c4a3952013-10-09 19:17:56 +03002040 struct drm_device *dev = crtc->dev;
2041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2042 enum pipe pipe = intel_crtc->pipe;
Ville Syrjälä7c4a3952013-10-09 19:17:56 +03002043 struct drm_plane *plane;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002044
Matt Roper3ef00282015-03-09 10:19:24 -07002045 if (!intel_crtc->active)
Ville Syrjälä2a44b762014-03-07 18:32:09 +02002046 return;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002047
Ville Syrjälä2a44b762014-03-07 18:32:09 +02002048 p->active = true;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002049 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
Ville Syrjälä2a44b762014-03-07 18:32:09 +02002050 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
Matt Roperc9f038a2015-03-09 11:06:02 -07002051
2052 if (crtc->primary->state->fb) {
2053 p->pri.enabled = true;
2054 p->pri.bytes_per_pixel =
2055 crtc->primary->state->fb->bits_per_pixel / 8;
2056 } else {
2057 p->pri.enabled = false;
2058 p->pri.bytes_per_pixel = 0;
2059 }
2060
2061 if (crtc->cursor->state->fb) {
2062 p->cur.enabled = true;
2063 p->cur.bytes_per_pixel = 4;
2064 } else {
2065 p->cur.enabled = false;
2066 p->cur.bytes_per_pixel = 0;
2067 }
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002068 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
Matt Roper3dd512f2015-02-27 10:12:00 -08002069 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
Ville Syrjälä7c4a3952013-10-09 19:17:56 +03002070
Matt Roperaf2b6532014-04-01 15:22:32 -07002071 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002072 struct intel_plane *intel_plane = to_intel_plane(plane);
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002073
Ville Syrjälä2a44b762014-03-07 18:32:09 +02002074 if (intel_plane->pipe == pipe) {
Ville Syrjälä7c4a3952013-10-09 19:17:56 +03002075 p->spr = intel_plane->wm;
Ville Syrjälä2a44b762014-03-07 18:32:09 +02002076 break;
2077 }
2078 }
2079}
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002080
Ville Syrjälä2a44b762014-03-07 18:32:09 +02002081static void ilk_compute_wm_config(struct drm_device *dev,
2082 struct intel_wm_config *config)
2083{
2084 struct intel_crtc *intel_crtc;
2085
2086 /* Compute the currently _active_ config */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01002087 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä2a44b762014-03-07 18:32:09 +02002088 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2089
2090 if (!wm->pipe_enabled)
2091 continue;
2092
2093 config->sprites_enabled |= wm->sprites_enabled;
2094 config->sprites_scaled |= wm->sprites_scaled;
2095 config->num_pipes_active++;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002096 }
2097}
2098
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002099/* Compute new watermarks for the pipe */
2100static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
Imre Deak820c1982013-12-17 14:46:36 +02002101 const struct ilk_pipe_wm_parameters *params,
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002102 struct intel_pipe_wm *pipe_wm)
2103{
2104 struct drm_device *dev = crtc->dev;
Damien Lespiaud34ff9c2014-01-06 19:17:23 +00002105 const struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002106 int level, max_level = ilk_wm_max_level(dev);
2107 /* LP0 watermark maximums depend on this pipe alone */
2108 struct intel_wm_config config = {
2109 .num_pipes_active = 1,
2110 .sprites_enabled = params->spr.enabled,
2111 .sprites_scaled = params->spr.scaled,
2112 };
Imre Deak820c1982013-12-17 14:46:36 +02002113 struct ilk_wm_maximums max;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002114
Ville Syrjälä2a44b762014-03-07 18:32:09 +02002115 pipe_wm->pipe_enabled = params->active;
2116 pipe_wm->sprites_enabled = params->spr.enabled;
2117 pipe_wm->sprites_scaled = params->spr.scaled;
2118
Ville Syrjälä7b39a0b2013-12-05 15:51:30 +02002119 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2120 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2121 max_level = 1;
2122
2123 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2124 if (params->spr.scaled)
2125 max_level = 0;
2126
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03002127 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002128
Ville Syrjäläa42a5712014-01-07 16:14:08 +02002129 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Ville Syrjäläce0e0712013-12-05 15:51:36 +02002130 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002131
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03002132 /* LP0 watermarks always use 1/2 DDB partitioning */
2133 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2134
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002135 /* At least LP0 must be valid */
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03002136 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2137 return false;
2138
2139 ilk_compute_wm_reg_maximums(dev, 1, &max);
2140
2141 for (level = 1; level <= max_level; level++) {
2142 struct intel_wm_level wm = {};
2143
2144 ilk_compute_wm_level(dev_priv, level, params, &wm);
2145
2146 /*
2147 * Disable any watermark level that exceeds the
2148 * register maximums since such watermarks are
2149 * always invalid.
2150 */
2151 if (!ilk_validate_wm_level(level, &max, &wm))
2152 break;
2153
2154 pipe_wm->wm[level] = wm;
2155 }
2156
2157 return true;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002158}
2159
2160/*
2161 * Merge the watermarks from all active pipes for a specific level.
2162 */
2163static void ilk_merge_wm_level(struct drm_device *dev,
2164 int level,
2165 struct intel_wm_level *ret_wm)
2166{
2167 const struct intel_crtc *intel_crtc;
2168
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002169 ret_wm->enable = true;
2170
Damien Lespiaud3fcc802014-05-13 23:32:22 +01002171 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjäläfe392ef2014-03-07 18:32:10 +02002172 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2173 const struct intel_wm_level *wm = &active->wm[level];
2174
2175 if (!active->pipe_enabled)
2176 continue;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002177
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002178 /*
2179 * The watermark values may have been used in the past,
2180 * so we must maintain them in the registers for some
2181 * time even if the level is now disabled.
2182 */
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002183 if (!wm->enable)
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002184 ret_wm->enable = false;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002185
2186 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2187 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2188 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2189 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2190 }
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002191}
2192
2193/*
2194 * Merge all low power watermarks for all active pipes.
2195 */
2196static void ilk_wm_merge(struct drm_device *dev,
Ville Syrjälä0ba22e22013-12-05 15:51:34 +02002197 const struct intel_wm_config *config,
Imre Deak820c1982013-12-17 14:46:36 +02002198 const struct ilk_wm_maximums *max,
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002199 struct intel_pipe_wm *merged)
2200{
2201 int level, max_level = ilk_wm_max_level(dev);
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002202 int last_enabled_level = max_level;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002203
Ville Syrjälä0ba22e22013-12-05 15:51:34 +02002204 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2205 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2206 config->num_pipes_active > 1)
2207 return;
2208
Ville Syrjälä6c8b6c22013-12-05 15:51:35 +02002209 /* ILK: FBC WM must be disabled always */
2210 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002211
2212 /* merge each WM1+ level */
2213 for (level = 1; level <= max_level; level++) {
2214 struct intel_wm_level *wm = &merged->wm[level];
2215
2216 ilk_merge_wm_level(dev, level, wm);
2217
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002218 if (level > last_enabled_level)
2219 wm->enable = false;
2220 else if (!ilk_validate_wm_level(level, max, wm))
2221 /* make sure all following levels get disabled */
2222 last_enabled_level = level - 1;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002223
2224 /*
2225 * The spec says it is preferred to disable
2226 * FBC WMs instead of disabling a WM level.
2227 */
2228 if (wm->fbc_val > max->fbc) {
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002229 if (wm->enable)
2230 merged->fbc_wm_enabled = false;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002231 wm->fbc_val = 0;
2232 }
2233 }
Ville Syrjälä6c8b6c22013-12-05 15:51:35 +02002234
2235 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2236 /*
2237 * FIXME this is racy. FBC might get enabled later.
2238 * What we should check here is whether FBC can be
2239 * enabled sometime later.
2240 */
2241 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2242 for (level = 2; level <= max_level; level++) {
2243 struct intel_wm_level *wm = &merged->wm[level];
2244
2245 wm->enable = false;
2246 }
2247 }
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002248}
2249
Ville Syrjäläb380ca32013-10-09 19:18:01 +03002250static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2251{
2252 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2253 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2254}
2255
Ville Syrjäläa68d68e2013-12-05 15:51:29 +02002256/* The value we need to program into the WM_LPx latency field */
2257static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2258{
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260
Ville Syrjäläa42a5712014-01-07 16:14:08 +02002261 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Ville Syrjäläa68d68e2013-12-05 15:51:29 +02002262 return 2 * level;
2263 else
2264 return dev_priv->wm.pri_latency[level];
2265}
2266
Imre Deak820c1982013-12-17 14:46:36 +02002267static void ilk_compute_wm_results(struct drm_device *dev,
Ville Syrjälä0362c782013-10-09 19:17:57 +03002268 const struct intel_pipe_wm *merged,
Ville Syrjälä609cede2013-10-09 19:18:03 +03002269 enum intel_ddb_partitioning partitioning,
Imre Deak820c1982013-12-17 14:46:36 +02002270 struct ilk_wm_values *results)
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03002271{
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002272 struct intel_crtc *intel_crtc;
2273 int level, wm_lp;
Paulo Zanonicca32e92013-05-31 11:45:06 -03002274
Ville Syrjälä0362c782013-10-09 19:17:57 +03002275 results->enable_fbc_wm = merged->fbc_wm_enabled;
Ville Syrjälä609cede2013-10-09 19:18:03 +03002276 results->partitioning = partitioning;
Paulo Zanonicca32e92013-05-31 11:45:06 -03002277
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002278 /* LP1+ register values */
Paulo Zanonicca32e92013-05-31 11:45:06 -03002279 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03002280 const struct intel_wm_level *r;
Paulo Zanonicca32e92013-05-31 11:45:06 -03002281
Ville Syrjäläb380ca32013-10-09 19:18:01 +03002282 level = ilk_wm_lp_to_level(wm_lp, merged);
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002283
Ville Syrjälä0362c782013-10-09 19:17:57 +03002284 r = &merged->wm[level];
Paulo Zanonicca32e92013-05-31 11:45:06 -03002285
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002286 /*
2287 * Maintain the watermark values even if the level is
2288 * disabled. Doing otherwise could cause underruns.
2289 */
2290 results->wm_lp[wm_lp - 1] =
Ville Syrjäläa68d68e2013-12-05 15:51:29 +02002291 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
Ville Syrjälä416f4722013-11-02 21:07:46 -07002292 (r->pri_val << WM1_LP_SR_SHIFT) |
2293 r->cur_val;
2294
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002295 if (r->enable)
2296 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2297
Ville Syrjälä416f4722013-11-02 21:07:46 -07002298 if (INTEL_INFO(dev)->gen >= 8)
2299 results->wm_lp[wm_lp - 1] |=
2300 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2301 else
2302 results->wm_lp[wm_lp - 1] |=
2303 r->fbc_val << WM1_LP_FBC_SHIFT;
2304
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002305 /*
2306 * Always set WM1S_LP_EN when spr_val != 0, even if the
2307 * level is disabled. Doing otherwise could cause underruns.
2308 */
Ville Syrjälä6cef2b8a2013-12-05 15:51:32 +02002309 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2310 WARN_ON(wm_lp != 1);
2311 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2312 } else
2313 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
Paulo Zanonicca32e92013-05-31 11:45:06 -03002314 }
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002315
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002316 /* LP0 register values */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01002317 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002318 enum pipe pipe = intel_crtc->pipe;
2319 const struct intel_wm_level *r =
2320 &intel_crtc->wm.active.wm[0];
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03002321
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002322 if (WARN_ON(!r->enable))
2323 continue;
2324
2325 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2326
2327 results->wm_pipe[pipe] =
2328 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2329 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2330 r->cur_val;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002331 }
2332}
2333
Paulo Zanoni861f3382013-05-31 10:19:21 -03002334/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2335 * case both are at the same level. Prefer r1 in case they're the same. */
Imre Deak820c1982013-12-17 14:46:36 +02002336static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
Ville Syrjälä198a1e92013-10-09 19:17:58 +03002337 struct intel_pipe_wm *r1,
2338 struct intel_pipe_wm *r2)
Paulo Zanoni861f3382013-05-31 10:19:21 -03002339{
Ville Syrjälä198a1e92013-10-09 19:17:58 +03002340 int level, max_level = ilk_wm_max_level(dev);
2341 int level1 = 0, level2 = 0;
Paulo Zanoni861f3382013-05-31 10:19:21 -03002342
Ville Syrjälä198a1e92013-10-09 19:17:58 +03002343 for (level = 1; level <= max_level; level++) {
2344 if (r1->wm[level].enable)
2345 level1 = level;
2346 if (r2->wm[level].enable)
2347 level2 = level;
Paulo Zanoni861f3382013-05-31 10:19:21 -03002348 }
2349
Ville Syrjälä198a1e92013-10-09 19:17:58 +03002350 if (level1 == level2) {
2351 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
Paulo Zanoni861f3382013-05-31 10:19:21 -03002352 return r2;
2353 else
2354 return r1;
Ville Syrjälä198a1e92013-10-09 19:17:58 +03002355 } else if (level1 > level2) {
Paulo Zanoni861f3382013-05-31 10:19:21 -03002356 return r1;
2357 } else {
2358 return r2;
2359 }
2360}
2361
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002362/* dirty bits used to track which watermarks need changes */
2363#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2364#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2365#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2366#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2367#define WM_DIRTY_FBC (1 << 24)
2368#define WM_DIRTY_DDB (1 << 25)
2369
Damien Lespiau055e3932014-08-18 13:49:10 +01002370static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
Imre Deak820c1982013-12-17 14:46:36 +02002371 const struct ilk_wm_values *old,
2372 const struct ilk_wm_values *new)
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002373{
2374 unsigned int dirty = 0;
2375 enum pipe pipe;
2376 int wm_lp;
2377
Damien Lespiau055e3932014-08-18 13:49:10 +01002378 for_each_pipe(dev_priv, pipe) {
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002379 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2380 dirty |= WM_DIRTY_LINETIME(pipe);
2381 /* Must disable LP1+ watermarks too */
2382 dirty |= WM_DIRTY_LP_ALL;
2383 }
2384
2385 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2386 dirty |= WM_DIRTY_PIPE(pipe);
2387 /* Must disable LP1+ watermarks too */
2388 dirty |= WM_DIRTY_LP_ALL;
2389 }
2390 }
2391
2392 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2393 dirty |= WM_DIRTY_FBC;
2394 /* Must disable LP1+ watermarks too */
2395 dirty |= WM_DIRTY_LP_ALL;
2396 }
2397
2398 if (old->partitioning != new->partitioning) {
2399 dirty |= WM_DIRTY_DDB;
2400 /* Must disable LP1+ watermarks too */
2401 dirty |= WM_DIRTY_LP_ALL;
2402 }
2403
2404 /* LP1+ watermarks already deemed dirty, no need to continue */
2405 if (dirty & WM_DIRTY_LP_ALL)
2406 return dirty;
2407
2408 /* Find the lowest numbered LP1+ watermark in need of an update... */
2409 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2410 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2411 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2412 break;
2413 }
2414
2415 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2416 for (; wm_lp <= 3; wm_lp++)
2417 dirty |= WM_DIRTY_LP(wm_lp);
2418
2419 return dirty;
2420}
2421
Ville Syrjälä8553c182013-12-05 15:51:39 +02002422static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2423 unsigned int dirty)
2424{
Imre Deak820c1982013-12-17 14:46:36 +02002425 struct ilk_wm_values *previous = &dev_priv->wm.hw;
Ville Syrjälä8553c182013-12-05 15:51:39 +02002426 bool changed = false;
2427
2428 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2429 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2430 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2431 changed = true;
2432 }
2433 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2434 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2435 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2436 changed = true;
2437 }
2438 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2439 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2440 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2441 changed = true;
2442 }
2443
2444 /*
2445 * Don't touch WM1S_LP_EN here.
2446 * Doing so could cause underruns.
2447 */
2448
2449 return changed;
2450}
2451
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002452/*
2453 * The spec says we shouldn't write when we don't need, because every write
2454 * causes WMs to be re-evaluated, expending some power.
2455 */
Imre Deak820c1982013-12-17 14:46:36 +02002456static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2457 struct ilk_wm_values *results)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002458{
Ville Syrjäläac9545f2013-12-05 15:51:28 +02002459 struct drm_device *dev = dev_priv->dev;
Imre Deak820c1982013-12-17 14:46:36 +02002460 struct ilk_wm_values *previous = &dev_priv->wm.hw;
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002461 unsigned int dirty;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002462 uint32_t val;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002463
Damien Lespiau055e3932014-08-18 13:49:10 +01002464 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002465 if (!dirty)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002466 return;
2467
Ville Syrjälä8553c182013-12-05 15:51:39 +02002468 _ilk_disable_lp_wm(dev_priv, dirty);
Ville Syrjälä6cef2b8a2013-12-05 15:51:32 +02002469
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002470 if (dirty & WM_DIRTY_PIPE(PIPE_A))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002471 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002472 if (dirty & WM_DIRTY_PIPE(PIPE_B))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002473 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002474 if (dirty & WM_DIRTY_PIPE(PIPE_C))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002475 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2476
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002477 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002478 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002479 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002480 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002481 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002482 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2483
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002484 if (dirty & WM_DIRTY_DDB) {
Ville Syrjäläa42a5712014-01-07 16:14:08 +02002485 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Ville Syrjäläac9545f2013-12-05 15:51:28 +02002486 val = I915_READ(WM_MISC);
2487 if (results->partitioning == INTEL_DDB_PART_1_2)
2488 val &= ~WM_MISC_DATA_PARTITION_5_6;
2489 else
2490 val |= WM_MISC_DATA_PARTITION_5_6;
2491 I915_WRITE(WM_MISC, val);
2492 } else {
2493 val = I915_READ(DISP_ARB_CTL2);
2494 if (results->partitioning == INTEL_DDB_PART_1_2)
2495 val &= ~DISP_DATA_PARTITION_5_6;
2496 else
2497 val |= DISP_DATA_PARTITION_5_6;
2498 I915_WRITE(DISP_ARB_CTL2, val);
2499 }
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03002500 }
2501
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002502 if (dirty & WM_DIRTY_FBC) {
Paulo Zanonicca32e92013-05-31 11:45:06 -03002503 val = I915_READ(DISP_ARB_CTL);
2504 if (results->enable_fbc_wm)
2505 val &= ~DISP_FBC_WM_DIS;
2506 else
2507 val |= DISP_FBC_WM_DIS;
2508 I915_WRITE(DISP_ARB_CTL, val);
2509 }
2510
Imre Deak954911e2013-12-17 14:46:34 +02002511 if (dirty & WM_DIRTY_LP(1) &&
2512 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2513 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2514
2515 if (INTEL_INFO(dev)->gen >= 7) {
Ville Syrjälä6cef2b8a2013-12-05 15:51:32 +02002516 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2517 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2518 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2519 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2520 }
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002521
Ville Syrjäläfacd6192013-12-05 15:51:33 +02002522 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002523 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
Ville Syrjäläfacd6192013-12-05 15:51:33 +02002524 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002525 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
Ville Syrjäläfacd6192013-12-05 15:51:33 +02002526 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002527 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
Ville Syrjälä609cede2013-10-09 19:18:03 +03002528
2529 dev_priv->wm.hw = *results;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002530}
2531
Ville Syrjälä8553c182013-12-05 15:51:39 +02002532static bool ilk_disable_lp_wm(struct drm_device *dev)
2533{
2534 struct drm_i915_private *dev_priv = dev->dev_private;
2535
2536 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2537}
2538
Damien Lespiaub9cec072014-11-04 17:06:43 +00002539/*
2540 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2541 * different active planes.
2542 */
2543
2544#define SKL_DDB_SIZE 896 /* in blocks */
2545
2546static void
2547skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2548 struct drm_crtc *for_crtc,
2549 const struct intel_wm_config *config,
2550 const struct skl_pipe_wm_parameters *params,
2551 struct skl_ddb_entry *alloc /* out */)
2552{
2553 struct drm_crtc *crtc;
2554 unsigned int pipe_size, ddb_size;
2555 int nth_active_pipe;
2556
2557 if (!params->active) {
2558 alloc->start = 0;
2559 alloc->end = 0;
2560 return;
2561 }
2562
2563 ddb_size = SKL_DDB_SIZE;
2564
2565 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2566
2567 nth_active_pipe = 0;
2568 for_each_crtc(dev, crtc) {
Matt Roper3ef00282015-03-09 10:19:24 -07002569 if (!to_intel_crtc(crtc)->active)
Damien Lespiaub9cec072014-11-04 17:06:43 +00002570 continue;
2571
2572 if (crtc == for_crtc)
2573 break;
2574
2575 nth_active_pipe++;
2576 }
2577
2578 pipe_size = ddb_size / config->num_pipes_active;
2579 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
Damien Lespiau16160e32014-11-04 17:06:53 +00002580 alloc->end = alloc->start + pipe_size;
Damien Lespiaub9cec072014-11-04 17:06:43 +00002581}
2582
2583static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2584{
2585 if (config->num_pipes_active == 1)
2586 return 32;
2587
2588 return 8;
2589}
2590
Damien Lespiaua269c582014-11-04 17:06:49 +00002591static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2592{
2593 entry->start = reg & 0x3ff;
2594 entry->end = (reg >> 16) & 0x3ff;
Damien Lespiau16160e32014-11-04 17:06:53 +00002595 if (entry->end)
2596 entry->end += 1;
Damien Lespiaua269c582014-11-04 17:06:49 +00002597}
2598
Damien Lespiau08db6652014-11-04 17:06:52 +00002599void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2600 struct skl_ddb_allocation *ddb /* out */)
Damien Lespiaua269c582014-11-04 17:06:49 +00002601{
Damien Lespiaua269c582014-11-04 17:06:49 +00002602 enum pipe pipe;
2603 int plane;
2604 u32 val;
2605
2606 for_each_pipe(dev_priv, pipe) {
Damien Lespiaudd740782015-02-28 14:54:08 +00002607 for_each_plane(dev_priv, pipe, plane) {
Damien Lespiaua269c582014-11-04 17:06:49 +00002608 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2609 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2610 val);
2611 }
2612
2613 val = I915_READ(CUR_BUF_CFG(pipe));
2614 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2615 }
2616}
2617
Damien Lespiaub9cec072014-11-04 17:06:43 +00002618static unsigned int
2619skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p)
2620{
2621 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2622}
2623
2624/*
2625 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2626 * a 8192x4096@32bpp framebuffer:
2627 * 3 * 4096 * 8192 * 4 < 2^32
2628 */
2629static unsigned int
2630skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2631 const struct skl_pipe_wm_parameters *params)
2632{
2633 unsigned int total_data_rate = 0;
2634 int plane;
2635
2636 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2637 const struct intel_plane_wm_parameters *p;
2638
2639 p = &params->plane[plane];
2640 if (!p->enabled)
2641 continue;
2642
2643 total_data_rate += skl_plane_relative_data_rate(p);
2644 }
2645
2646 return total_data_rate;
2647}
2648
2649static void
2650skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2651 const struct intel_wm_config *config,
2652 const struct skl_pipe_wm_parameters *params,
2653 struct skl_ddb_allocation *ddb /* out */)
2654{
2655 struct drm_device *dev = crtc->dev;
Damien Lespiaudd740782015-02-28 14:54:08 +00002656 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiaub9cec072014-11-04 17:06:43 +00002657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2658 enum pipe pipe = intel_crtc->pipe;
Damien Lespiau34bb56a2014-11-04 17:07:01 +00002659 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
Damien Lespiaub9cec072014-11-04 17:06:43 +00002660 uint16_t alloc_size, start, cursor_blocks;
Damien Lespiau80958152015-02-09 13:35:10 +00002661 uint16_t minimum[I915_MAX_PLANES];
Damien Lespiaub9cec072014-11-04 17:06:43 +00002662 unsigned int total_data_rate;
2663 int plane;
2664
Damien Lespiau34bb56a2014-11-04 17:07:01 +00002665 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2666 alloc_size = skl_ddb_entry_size(alloc);
Damien Lespiaub9cec072014-11-04 17:06:43 +00002667 if (alloc_size == 0) {
2668 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2669 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2670 return;
2671 }
2672
2673 cursor_blocks = skl_cursor_allocation(config);
Damien Lespiau34bb56a2014-11-04 17:07:01 +00002674 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2675 ddb->cursor[pipe].end = alloc->end;
Damien Lespiaub9cec072014-11-04 17:06:43 +00002676
2677 alloc_size -= cursor_blocks;
Damien Lespiau34bb56a2014-11-04 17:07:01 +00002678 alloc->end -= cursor_blocks;
Damien Lespiaub9cec072014-11-04 17:06:43 +00002679
Damien Lespiau80958152015-02-09 13:35:10 +00002680 /* 1. Allocate the mininum required blocks for each active plane */
Damien Lespiaudd740782015-02-28 14:54:08 +00002681 for_each_plane(dev_priv, pipe, plane) {
Damien Lespiau80958152015-02-09 13:35:10 +00002682 const struct intel_plane_wm_parameters *p;
2683
2684 p = &params->plane[plane];
2685 if (!p->enabled)
2686 continue;
2687
2688 minimum[plane] = 8;
2689 alloc_size -= minimum[plane];
2690 }
2691
Damien Lespiaub9cec072014-11-04 17:06:43 +00002692 /*
Damien Lespiau80958152015-02-09 13:35:10 +00002693 * 2. Distribute the remaining space in proportion to the amount of
2694 * data each plane needs to fetch from memory.
Damien Lespiaub9cec072014-11-04 17:06:43 +00002695 *
2696 * FIXME: we may not allocate every single block here.
2697 */
2698 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2699
Damien Lespiau34bb56a2014-11-04 17:07:01 +00002700 start = alloc->start;
Damien Lespiaub9cec072014-11-04 17:06:43 +00002701 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2702 const struct intel_plane_wm_parameters *p;
2703 unsigned int data_rate;
2704 uint16_t plane_blocks;
2705
2706 p = &params->plane[plane];
2707 if (!p->enabled)
2708 continue;
2709
2710 data_rate = skl_plane_relative_data_rate(p);
2711
2712 /*
2713 * promote the expression to 64 bits to avoid overflowing, the
2714 * result is < available as data_rate / total_data_rate < 1
2715 */
Damien Lespiau80958152015-02-09 13:35:10 +00002716 plane_blocks = minimum[plane];
2717 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2718 total_data_rate);
Damien Lespiaub9cec072014-11-04 17:06:43 +00002719
2720 ddb->plane[pipe][plane].start = start;
Damien Lespiau16160e32014-11-04 17:06:53 +00002721 ddb->plane[pipe][plane].end = start + plane_blocks;
Damien Lespiaub9cec072014-11-04 17:06:43 +00002722
2723 start += plane_blocks;
2724 }
2725
2726}
2727
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02002728static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002729{
2730 /* TODO: Take into account the scalers once we support them */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02002731 return config->base.adjusted_mode.crtc_clock;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002732}
2733
2734/*
2735 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2736 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2737 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2738 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2739*/
2740static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2741 uint32_t latency)
2742{
2743 uint32_t wm_intermediate_val, ret;
2744
2745 if (latency == 0)
2746 return UINT_MAX;
2747
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002748 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002749 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2750
2751 return ret;
2752}
2753
2754static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2755 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00002756 uint64_t tiling, uint32_t latency)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002757{
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002758 uint32_t ret;
2759 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2760 uint32_t wm_intermediate_val;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002761
2762 if (latency == 0)
2763 return UINT_MAX;
2764
2765 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00002766
2767 if (tiling == I915_FORMAT_MOD_Y_TILED ||
2768 tiling == I915_FORMAT_MOD_Yf_TILED) {
2769 plane_bytes_per_line *= 4;
2770 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2771 plane_blocks_per_line /= 4;
2772 } else {
2773 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2774 }
2775
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002776 wm_intermediate_val = latency * pixel_rate;
2777 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002778 plane_blocks_per_line;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002779
2780 return ret;
2781}
2782
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002783static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2784 const struct intel_crtc *intel_crtc)
2785{
2786 struct drm_device *dev = intel_crtc->base.dev;
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2789 enum pipe pipe = intel_crtc->pipe;
2790
2791 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2792 sizeof(new_ddb->plane[pipe])))
2793 return true;
2794
2795 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2796 sizeof(new_ddb->cursor[pipe])))
2797 return true;
2798
2799 return false;
2800}
2801
2802static void skl_compute_wm_global_parameters(struct drm_device *dev,
2803 struct intel_wm_config *config)
2804{
2805 struct drm_crtc *crtc;
2806 struct drm_plane *plane;
2807
2808 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
Matt Roper3ef00282015-03-09 10:19:24 -07002809 config->num_pipes_active += to_intel_crtc(crtc)->active;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002810
2811 /* FIXME: I don't think we need those two global parameters on SKL */
2812 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2813 struct intel_plane *intel_plane = to_intel_plane(plane);
2814
2815 config->sprites_enabled |= intel_plane->wm.enabled;
2816 config->sprites_scaled |= intel_plane->wm.scaled;
2817 }
2818}
2819
2820static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2821 struct skl_pipe_wm_parameters *p)
2822{
2823 struct drm_device *dev = crtc->dev;
2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825 enum pipe pipe = intel_crtc->pipe;
2826 struct drm_plane *plane;
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00002827 struct drm_framebuffer *fb;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002828 int i = 1; /* Index for sprite planes start */
2829
Matt Roper3ef00282015-03-09 10:19:24 -07002830 p->active = intel_crtc->active;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002831 if (p->active) {
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002832 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2833 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002834
Matt Roperc9f038a2015-03-09 11:06:02 -07002835 fb = crtc->primary->state->fb;
2836 if (fb) {
2837 p->plane[0].enabled = true;
2838 p->plane[0].bytes_per_pixel = fb->bits_per_pixel / 8;
2839 p->plane[0].tiling = fb->modifier[0];
2840 } else {
2841 p->plane[0].enabled = false;
2842 p->plane[0].bytes_per_pixel = 0;
2843 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
2844 }
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002845 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2846 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
Tvrtko Ursulin1fc0a8f2015-03-23 11:10:38 +00002847 p->plane[0].rotation = crtc->primary->state->rotation;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002848
Matt Roperc9f038a2015-03-09 11:06:02 -07002849 fb = crtc->cursor->state->fb;
2850 if (fb) {
2851 p->cursor.enabled = true;
2852 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
2853 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
2854 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
2855 } else {
2856 p->cursor.enabled = false;
2857 p->cursor.bytes_per_pixel = 0;
2858 p->cursor.horiz_pixels = 64;
2859 p->cursor.vert_pixels = 64;
2860 }
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002861 }
2862
2863 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2864 struct intel_plane *intel_plane = to_intel_plane(plane);
2865
Sonika Jindala712f8e2014-12-09 10:59:15 +05302866 if (intel_plane->pipe == pipe &&
2867 plane->type == DRM_PLANE_TYPE_OVERLAY)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002868 p->plane[i++] = intel_plane->wm;
2869 }
2870}
2871
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002872static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
2873 struct skl_pipe_wm_parameters *p,
Damien Lespiauafb024a2014-11-04 17:06:59 +00002874 struct intel_plane_wm_parameters *p_params,
2875 uint16_t ddb_allocation,
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002876 int level,
Damien Lespiauafb024a2014-11-04 17:06:59 +00002877 uint16_t *out_blocks, /* out */
2878 uint8_t *out_lines /* out */)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002879{
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002880 uint32_t latency = dev_priv->wm.skl_latency[level];
2881 uint32_t method1, method2;
2882 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2883 uint32_t res_blocks, res_lines;
2884 uint32_t selected_result;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002885
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002886 if (latency == 0 || !p->active || !p_params->enabled)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002887 return false;
2888
2889 method1 = skl_wm_method1(p->pixel_rate,
2890 p_params->bytes_per_pixel,
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002891 latency);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002892 method2 = skl_wm_method2(p->pixel_rate,
2893 p->pipe_htotal,
2894 p_params->horiz_pixels,
2895 p_params->bytes_per_pixel,
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00002896 p_params->tiling,
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002897 latency);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002898
2899 plane_bytes_per_line = p_params->horiz_pixels *
2900 p_params->bytes_per_pixel;
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002901 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002902
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00002903 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2904 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
Tvrtko Ursulin1fc0a8f2015-03-23 11:10:38 +00002905 uint32_t min_scanlines = 4;
2906 uint32_t y_tile_minimum;
2907 if (intel_rotation_90_or_270(p_params->rotation)) {
2908 switch (p_params->bytes_per_pixel) {
2909 case 1:
2910 min_scanlines = 16;
2911 break;
2912 case 2:
2913 min_scanlines = 8;
2914 break;
2915 case 8:
2916 WARN(1, "Unsupported pixel depth for rotation");
kbuild test robot2f0b5792015-03-26 22:30:21 +08002917 }
Tvrtko Ursulin1fc0a8f2015-03-23 11:10:38 +00002918 }
2919 y_tile_minimum = plane_blocks_per_line * min_scanlines;
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00002920 selected_result = max(method2, y_tile_minimum);
2921 } else {
2922 if ((ddb_allocation / plane_blocks_per_line) >= 1)
2923 selected_result = min(method1, method2);
2924 else
2925 selected_result = method1;
2926 }
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002927
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002928 res_blocks = selected_result + 1;
2929 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
Damien Lespiaue6d66172014-11-04 17:06:55 +00002930
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00002931 if (level >= 1 && level <= 7) {
2932 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2933 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
2934 res_lines += 4;
2935 else
2936 res_blocks++;
2937 }
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002938
2939 if (res_blocks >= ddb_allocation || res_lines > 31)
Damien Lespiaue6d66172014-11-04 17:06:55 +00002940 return false;
2941
2942 *out_blocks = res_blocks;
2943 *out_lines = res_lines;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002944
2945 return true;
2946}
2947
2948static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
2949 struct skl_ddb_allocation *ddb,
2950 struct skl_pipe_wm_parameters *p,
2951 enum pipe pipe,
2952 int level,
2953 int num_planes,
2954 struct skl_wm_level *result)
2955{
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002956 uint16_t ddb_blocks;
2957 int i;
2958
2959 for (i = 0; i < num_planes; i++) {
2960 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2961
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002962 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
2963 p, &p->plane[i],
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002964 ddb_blocks,
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002965 level,
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002966 &result->plane_res_b[i],
2967 &result->plane_res_l[i]);
2968 }
2969
2970 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00002971 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
2972 ddb_blocks, level,
2973 &result->cursor_res_b,
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002974 &result->cursor_res_l);
2975}
2976
Damien Lespiau407b50f2014-11-04 17:06:57 +00002977static uint32_t
2978skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
2979{
Matt Roper3ef00282015-03-09 10:19:24 -07002980 if (!to_intel_crtc(crtc)->active)
Damien Lespiau407b50f2014-11-04 17:06:57 +00002981 return 0;
2982
2983 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
2984
2985}
2986
2987static void skl_compute_transition_wm(struct drm_crtc *crtc,
2988 struct skl_pipe_wm_parameters *params,
Damien Lespiau9414f562014-11-04 17:06:58 +00002989 struct skl_wm_level *trans_wm /* out */)
Damien Lespiau407b50f2014-11-04 17:06:57 +00002990{
Damien Lespiau9414f562014-11-04 17:06:58 +00002991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2992 int i;
2993
Damien Lespiau407b50f2014-11-04 17:06:57 +00002994 if (!params->active)
2995 return;
Damien Lespiau9414f562014-11-04 17:06:58 +00002996
2997 /* Until we know more, just disable transition WMs */
2998 for (i = 0; i < intel_num_planes(intel_crtc); i++)
2999 trans_wm->plane_en[i] = false;
3000 trans_wm->cursor_en = false;
Damien Lespiau407b50f2014-11-04 17:06:57 +00003001}
3002
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003003static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3004 struct skl_ddb_allocation *ddb,
3005 struct skl_pipe_wm_parameters *params,
3006 struct skl_pipe_wm *pipe_wm)
3007{
3008 struct drm_device *dev = crtc->dev;
3009 const struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3011 int level, max_level = ilk_wm_max_level(dev);
3012
3013 for (level = 0; level <= max_level; level++) {
3014 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3015 level, intel_num_planes(intel_crtc),
3016 &pipe_wm->wm[level]);
3017 }
3018 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3019
Damien Lespiau9414f562014-11-04 17:06:58 +00003020 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003021}
3022
3023static void skl_compute_wm_results(struct drm_device *dev,
3024 struct skl_pipe_wm_parameters *p,
3025 struct skl_pipe_wm *p_wm,
3026 struct skl_wm_values *r,
3027 struct intel_crtc *intel_crtc)
3028{
3029 int level, max_level = ilk_wm_max_level(dev);
3030 enum pipe pipe = intel_crtc->pipe;
Damien Lespiau9414f562014-11-04 17:06:58 +00003031 uint32_t temp;
3032 int i;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003033
3034 for (level = 0; level <= max_level; level++) {
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003035 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3036 temp = 0;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003037
3038 temp |= p_wm->wm[level].plane_res_l[i] <<
3039 PLANE_WM_LINES_SHIFT;
3040 temp |= p_wm->wm[level].plane_res_b[i];
3041 if (p_wm->wm[level].plane_en[i])
3042 temp |= PLANE_WM_EN;
3043
3044 r->plane[pipe][i][level] = temp;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003045 }
3046
3047 temp = 0;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003048
3049 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3050 temp |= p_wm->wm[level].cursor_res_b;
3051
3052 if (p_wm->wm[level].cursor_en)
3053 temp |= PLANE_WM_EN;
3054
3055 r->cursor[pipe][level] = temp;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003056
3057 }
3058
Damien Lespiau9414f562014-11-04 17:06:58 +00003059 /* transition WMs */
3060 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3061 temp = 0;
3062 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3063 temp |= p_wm->trans_wm.plane_res_b[i];
3064 if (p_wm->trans_wm.plane_en[i])
3065 temp |= PLANE_WM_EN;
3066
3067 r->plane_trans[pipe][i] = temp;
3068 }
3069
3070 temp = 0;
3071 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3072 temp |= p_wm->trans_wm.cursor_res_b;
3073 if (p_wm->trans_wm.cursor_en)
3074 temp |= PLANE_WM_EN;
3075
3076 r->cursor_trans[pipe] = temp;
3077
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003078 r->wm_linetime[pipe] = p_wm->linetime;
3079}
3080
Damien Lespiau16160e32014-11-04 17:06:53 +00003081static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3082 const struct skl_ddb_entry *entry)
3083{
3084 if (entry->end)
3085 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3086 else
3087 I915_WRITE(reg, 0);
3088}
3089
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003090static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3091 const struct skl_wm_values *new)
3092{
3093 struct drm_device *dev = dev_priv->dev;
3094 struct intel_crtc *crtc;
3095
3096 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3097 int i, level, max_level = ilk_wm_max_level(dev);
3098 enum pipe pipe = crtc->pipe;
3099
Damien Lespiau5d374d92014-11-04 17:07:00 +00003100 if (!new->dirty[pipe])
3101 continue;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003102
Damien Lespiau5d374d92014-11-04 17:07:00 +00003103 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3104
3105 for (level = 0; level <= max_level; level++) {
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003106 for (i = 0; i < intel_num_planes(crtc); i++)
Damien Lespiau5d374d92014-11-04 17:07:00 +00003107 I915_WRITE(PLANE_WM(pipe, i, level),
3108 new->plane[pipe][i][level]);
3109 I915_WRITE(CUR_WM(pipe, level),
3110 new->cursor[pipe][level]);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003111 }
Damien Lespiau5d374d92014-11-04 17:07:00 +00003112 for (i = 0; i < intel_num_planes(crtc); i++)
3113 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3114 new->plane_trans[pipe][i]);
3115 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3116
3117 for (i = 0; i < intel_num_planes(crtc); i++)
3118 skl_ddb_entry_write(dev_priv,
3119 PLANE_BUF_CFG(pipe, i),
3120 &new->ddb.plane[pipe][i]);
3121
3122 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3123 &new->ddb.cursor[pipe]);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003124 }
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003125}
3126
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003127/*
3128 * When setting up a new DDB allocation arrangement, we need to correctly
3129 * sequence the times at which the new allocations for the pipes are taken into
3130 * account or we'll have pipes fetching from space previously allocated to
3131 * another pipe.
3132 *
3133 * Roughly the sequence looks like:
3134 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3135 * overlapping with a previous light-up pipe (another way to put it is:
3136 * pipes with their new allocation strickly included into their old ones).
3137 * 2. re-allocate the other pipes that get their allocation reduced
3138 * 3. allocate the pipes having their allocation increased
3139 *
3140 * Steps 1. and 2. are here to take care of the following case:
3141 * - Initially DDB looks like this:
3142 * | B | C |
3143 * - enable pipe A.
3144 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3145 * allocation
3146 * | A | B | C |
3147 *
3148 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3149 */
3150
Damien Lespiaud21b7952014-11-04 17:07:03 +00003151static void
3152skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003153{
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003154 int plane;
3155
Damien Lespiaud21b7952014-11-04 17:07:03 +00003156 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3157
Damien Lespiaudd740782015-02-28 14:54:08 +00003158 for_each_plane(dev_priv, pipe, plane) {
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003159 I915_WRITE(PLANE_SURF(pipe, plane),
3160 I915_READ(PLANE_SURF(pipe, plane)));
3161 }
3162 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3163}
3164
3165static bool
3166skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3167 const struct skl_ddb_allocation *new,
3168 enum pipe pipe)
3169{
3170 uint16_t old_size, new_size;
3171
3172 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3173 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3174
3175 return old_size != new_size &&
3176 new->pipe[pipe].start >= old->pipe[pipe].start &&
3177 new->pipe[pipe].end <= old->pipe[pipe].end;
3178}
3179
3180static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3181 struct skl_wm_values *new_values)
3182{
3183 struct drm_device *dev = dev_priv->dev;
3184 struct skl_ddb_allocation *cur_ddb, *new_ddb;
Ville Syrjäläc929cb42015-04-02 18:28:07 +03003185 bool reallocated[I915_MAX_PIPES] = {};
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003186 struct intel_crtc *crtc;
3187 enum pipe pipe;
3188
3189 new_ddb = &new_values->ddb;
3190 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3191
3192 /*
3193 * First pass: flush the pipes with the new allocation contained into
3194 * the old space.
3195 *
3196 * We'll wait for the vblank on those pipes to ensure we can safely
3197 * re-allocate the freed space without this pipe fetching from it.
3198 */
3199 for_each_intel_crtc(dev, crtc) {
3200 if (!crtc->active)
3201 continue;
3202
3203 pipe = crtc->pipe;
3204
3205 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3206 continue;
3207
Damien Lespiaud21b7952014-11-04 17:07:03 +00003208 skl_wm_flush_pipe(dev_priv, pipe, 1);
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003209 intel_wait_for_vblank(dev, pipe);
3210
3211 reallocated[pipe] = true;
3212 }
3213
3214
3215 /*
3216 * Second pass: flush the pipes that are having their allocation
3217 * reduced, but overlapping with a previous allocation.
3218 *
3219 * Here as well we need to wait for the vblank to make sure the freed
3220 * space is not used anymore.
3221 */
3222 for_each_intel_crtc(dev, crtc) {
3223 if (!crtc->active)
3224 continue;
3225
3226 pipe = crtc->pipe;
3227
3228 if (reallocated[pipe])
3229 continue;
3230
3231 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3232 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
Damien Lespiaud21b7952014-11-04 17:07:03 +00003233 skl_wm_flush_pipe(dev_priv, pipe, 2);
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003234 intel_wait_for_vblank(dev, pipe);
Sonika Jindald9d8e6b2014-12-11 17:58:15 +05303235 reallocated[pipe] = true;
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003236 }
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003237 }
3238
3239 /*
3240 * Third pass: flush the pipes that got more space allocated.
3241 *
3242 * We don't need to actively wait for the update here, next vblank
3243 * will just get more DDB space with the correct WM values.
3244 */
3245 for_each_intel_crtc(dev, crtc) {
3246 if (!crtc->active)
3247 continue;
3248
3249 pipe = crtc->pipe;
3250
3251 /*
3252 * At this point, only the pipes more space than before are
3253 * left to re-allocate.
3254 */
3255 if (reallocated[pipe])
3256 continue;
3257
Damien Lespiaud21b7952014-11-04 17:07:03 +00003258 skl_wm_flush_pipe(dev_priv, pipe, 3);
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003259 }
3260}
3261
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003262static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3263 struct skl_pipe_wm_parameters *params,
3264 struct intel_wm_config *config,
3265 struct skl_ddb_allocation *ddb, /* out */
3266 struct skl_pipe_wm *pipe_wm /* out */)
3267{
3268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3269
3270 skl_compute_wm_pipe_parameters(crtc, params);
Damien Lespiaub9cec072014-11-04 17:06:43 +00003271 skl_allocate_pipe_ddb(crtc, config, params, ddb);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003272 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3273
3274 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3275 return false;
3276
3277 intel_crtc->wm.skl_active = *pipe_wm;
3278 return true;
3279}
3280
3281static void skl_update_other_pipe_wm(struct drm_device *dev,
3282 struct drm_crtc *crtc,
3283 struct intel_wm_config *config,
3284 struct skl_wm_values *r)
3285{
3286 struct intel_crtc *intel_crtc;
3287 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3288
3289 /*
3290 * If the WM update hasn't changed the allocation for this_crtc (the
3291 * crtc we are currently computing the new WM values for), other
3292 * enabled crtcs will keep the same allocation and we don't need to
3293 * recompute anything for them.
3294 */
3295 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3296 return;
3297
3298 /*
3299 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3300 * other active pipes need new DDB allocation and WM values.
3301 */
3302 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3303 base.head) {
3304 struct skl_pipe_wm_parameters params = {};
3305 struct skl_pipe_wm pipe_wm = {};
3306 bool wm_changed;
3307
3308 if (this_crtc->pipe == intel_crtc->pipe)
3309 continue;
3310
3311 if (!intel_crtc->active)
3312 continue;
3313
3314 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3315 &params, config,
3316 &r->ddb, &pipe_wm);
3317
3318 /*
3319 * If we end up re-computing the other pipe WM values, it's
3320 * because it was really needed, so we expect the WM values to
3321 * be different.
3322 */
3323 WARN_ON(!wm_changed);
3324
3325 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3326 r->dirty[intel_crtc->pipe] = true;
3327 }
3328}
3329
3330static void skl_update_wm(struct drm_crtc *crtc)
3331{
3332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3333 struct drm_device *dev = crtc->dev;
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3335 struct skl_pipe_wm_parameters params = {};
3336 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3337 struct skl_pipe_wm pipe_wm = {};
3338 struct intel_wm_config config = {};
3339
3340 memset(results, 0, sizeof(*results));
3341
3342 skl_compute_wm_global_parameters(dev, &config);
3343
3344 if (!skl_update_pipe_wm(crtc, &params, &config,
3345 &results->ddb, &pipe_wm))
3346 return;
3347
3348 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3349 results->dirty[intel_crtc->pipe] = true;
3350
3351 skl_update_other_pipe_wm(dev, crtc, &config, results);
3352 skl_write_wm_values(dev_priv, results);
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003353 skl_flush_wm_values(dev_priv, results);
Damien Lespiau53b0deb2014-11-04 17:06:48 +00003354
3355 /* store the new configuration */
3356 dev_priv->wm.skl_hw = *results;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003357}
3358
3359static void
3360skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3361 uint32_t sprite_width, uint32_t sprite_height,
3362 int pixel_size, bool enabled, bool scaled)
3363{
3364 struct intel_plane *intel_plane = to_intel_plane(plane);
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00003365 struct drm_framebuffer *fb = plane->state->fb;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003366
3367 intel_plane->wm.enabled = enabled;
3368 intel_plane->wm.scaled = scaled;
3369 intel_plane->wm.horiz_pixels = sprite_width;
3370 intel_plane->wm.vert_pixels = sprite_height;
3371 intel_plane->wm.bytes_per_pixel = pixel_size;
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00003372 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3373 /*
3374 * Framebuffer can be NULL on plane disable, but it does not
3375 * matter for watermarks if we assume no tiling in that case.
3376 */
3377 if (fb)
3378 intel_plane->wm.tiling = fb->modifier[0];
Tvrtko Ursulin1fc0a8f2015-03-23 11:10:38 +00003379 intel_plane->wm.rotation = plane->state->rotation;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003380
3381 skl_update_wm(crtc);
3382}
3383
Imre Deak820c1982013-12-17 14:46:36 +02003384static void ilk_update_wm(struct drm_crtc *crtc)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003385{
Ville Syrjälä7c4a3952013-10-09 19:17:56 +03003386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä46ba6142013-09-10 11:40:40 +03003387 struct drm_device *dev = crtc->dev;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003388 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak820c1982013-12-17 14:46:36 +02003389 struct ilk_wm_maximums max;
3390 struct ilk_pipe_wm_parameters params = {};
3391 struct ilk_wm_values results = {};
Ville Syrjälä77c122b2013-08-06 22:24:04 +03003392 enum intel_ddb_partitioning partitioning;
Ville Syrjälä7c4a3952013-10-09 19:17:56 +03003393 struct intel_pipe_wm pipe_wm = {};
Ville Syrjälä198a1e92013-10-09 19:17:58 +03003394 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
Ville Syrjäläa485bfb2013-10-09 19:17:59 +03003395 struct intel_wm_config config = {};
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003396
Ville Syrjälä2a44b762014-03-07 18:32:09 +02003397 ilk_compute_wm_parameters(crtc, &params);
Paulo Zanoni861f3382013-05-31 10:19:21 -03003398
Ville Syrjälä7c4a3952013-10-09 19:17:56 +03003399 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3400
3401 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3402 return;
3403
3404 intel_crtc->wm.active = pipe_wm;
3405
Ville Syrjälä2a44b762014-03-07 18:32:09 +02003406 ilk_compute_wm_config(dev, &config);
3407
Ville Syrjälä34982fe2013-10-09 19:18:09 +03003408 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
Ville Syrjälä0ba22e22013-12-05 15:51:34 +02003409 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
Ville Syrjälä0362c782013-10-09 19:17:57 +03003410
Ville Syrjäläa485bfb2013-10-09 19:17:59 +03003411 /* 5/6 split only in single pipe config on IVB+ */
Ville Syrjäläec98c8d2013-10-11 15:26:26 +03003412 if (INTEL_INFO(dev)->gen >= 7 &&
3413 config.num_pipes_active == 1 && config.sprites_enabled) {
Ville Syrjälä34982fe2013-10-09 19:18:09 +03003414 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
Ville Syrjälä0ba22e22013-12-05 15:51:34 +02003415 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
Ville Syrjäläa485bfb2013-10-09 19:17:59 +03003416
Imre Deak820c1982013-12-17 14:46:36 +02003417 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
Paulo Zanoni861f3382013-05-31 10:19:21 -03003418 } else {
Ville Syrjälä198a1e92013-10-09 19:17:58 +03003419 best_lp_wm = &lp_wm_1_2;
Paulo Zanoni861f3382013-05-31 10:19:21 -03003420 }
3421
Ville Syrjälä198a1e92013-10-09 19:17:58 +03003422 partitioning = (best_lp_wm == &lp_wm_1_2) ?
Ville Syrjälä77c122b2013-08-06 22:24:04 +03003423 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
Paulo Zanoni861f3382013-05-31 10:19:21 -03003424
Imre Deak820c1982013-12-17 14:46:36 +02003425 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
Ville Syrjälä609cede2013-10-09 19:18:03 +03003426
Imre Deak820c1982013-12-17 14:46:36 +02003427 ilk_write_wm_values(dev_priv, &results);
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03003428}
3429
Damien Lespiaued57cb82014-07-15 09:21:24 +02003430static void
3431ilk_update_sprite_wm(struct drm_plane *plane,
3432 struct drm_crtc *crtc,
3433 uint32_t sprite_width, uint32_t sprite_height,
3434 int pixel_size, bool enabled, bool scaled)
Paulo Zanoni526682e2013-05-24 11:59:18 -03003435{
Ville Syrjälä8553c182013-12-05 15:51:39 +02003436 struct drm_device *dev = plane->dev;
Ville Syrjäläadf3d352013-08-06 22:24:11 +03003437 struct intel_plane *intel_plane = to_intel_plane(plane);
Paulo Zanoni526682e2013-05-24 11:59:18 -03003438
Ville Syrjäläadf3d352013-08-06 22:24:11 +03003439 intel_plane->wm.enabled = enabled;
3440 intel_plane->wm.scaled = scaled;
3441 intel_plane->wm.horiz_pixels = sprite_width;
Damien Lespiaued57cb82014-07-15 09:21:24 +02003442 intel_plane->wm.vert_pixels = sprite_width;
Ville Syrjäläadf3d352013-08-06 22:24:11 +03003443 intel_plane->wm.bytes_per_pixel = pixel_size;
Paulo Zanoni526682e2013-05-24 11:59:18 -03003444
Ville Syrjälä8553c182013-12-05 15:51:39 +02003445 /*
3446 * IVB workaround: must disable low power watermarks for at least
3447 * one frame before enabling scaling. LP watermarks can be re-enabled
3448 * when scaling is disabled.
3449 *
3450 * WaCxSRDisabledForSpriteScaling:ivb
3451 */
3452 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3453 intel_wait_for_vblank(dev, intel_plane->pipe);
3454
Imre Deak820c1982013-12-17 14:46:36 +02003455 ilk_update_wm(crtc);
Paulo Zanoni526682e2013-05-24 11:59:18 -03003456}
3457
Pradeep Bhat30789992014-11-04 17:06:45 +00003458static void skl_pipe_wm_active_state(uint32_t val,
3459 struct skl_pipe_wm *active,
3460 bool is_transwm,
3461 bool is_cursor,
3462 int i,
3463 int level)
3464{
3465 bool is_enabled = (val & PLANE_WM_EN) != 0;
3466
3467 if (!is_transwm) {
3468 if (!is_cursor) {
3469 active->wm[level].plane_en[i] = is_enabled;
3470 active->wm[level].plane_res_b[i] =
3471 val & PLANE_WM_BLOCKS_MASK;
3472 active->wm[level].plane_res_l[i] =
3473 (val >> PLANE_WM_LINES_SHIFT) &
3474 PLANE_WM_LINES_MASK;
3475 } else {
3476 active->wm[level].cursor_en = is_enabled;
3477 active->wm[level].cursor_res_b =
3478 val & PLANE_WM_BLOCKS_MASK;
3479 active->wm[level].cursor_res_l =
3480 (val >> PLANE_WM_LINES_SHIFT) &
3481 PLANE_WM_LINES_MASK;
3482 }
3483 } else {
3484 if (!is_cursor) {
3485 active->trans_wm.plane_en[i] = is_enabled;
3486 active->trans_wm.plane_res_b[i] =
3487 val & PLANE_WM_BLOCKS_MASK;
3488 active->trans_wm.plane_res_l[i] =
3489 (val >> PLANE_WM_LINES_SHIFT) &
3490 PLANE_WM_LINES_MASK;
3491 } else {
3492 active->trans_wm.cursor_en = is_enabled;
3493 active->trans_wm.cursor_res_b =
3494 val & PLANE_WM_BLOCKS_MASK;
3495 active->trans_wm.cursor_res_l =
3496 (val >> PLANE_WM_LINES_SHIFT) &
3497 PLANE_WM_LINES_MASK;
3498 }
3499 }
3500}
3501
3502static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3503{
3504 struct drm_device *dev = crtc->dev;
3505 struct drm_i915_private *dev_priv = dev->dev_private;
3506 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3508 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3509 enum pipe pipe = intel_crtc->pipe;
3510 int level, i, max_level;
3511 uint32_t temp;
3512
3513 max_level = ilk_wm_max_level(dev);
3514
3515 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3516
3517 for (level = 0; level <= max_level; level++) {
3518 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3519 hw->plane[pipe][i][level] =
3520 I915_READ(PLANE_WM(pipe, i, level));
3521 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3522 }
3523
3524 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3525 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3526 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3527
Matt Roper3ef00282015-03-09 10:19:24 -07003528 if (!intel_crtc->active)
Pradeep Bhat30789992014-11-04 17:06:45 +00003529 return;
3530
3531 hw->dirty[pipe] = true;
3532
3533 active->linetime = hw->wm_linetime[pipe];
3534
3535 for (level = 0; level <= max_level; level++) {
3536 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3537 temp = hw->plane[pipe][i][level];
3538 skl_pipe_wm_active_state(temp, active, false,
3539 false, i, level);
3540 }
3541 temp = hw->cursor[pipe][level];
3542 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3543 }
3544
3545 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3546 temp = hw->plane_trans[pipe][i];
3547 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3548 }
3549
3550 temp = hw->cursor_trans[pipe];
3551 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3552}
3553
3554void skl_wm_get_hw_state(struct drm_device *dev)
3555{
Damien Lespiaua269c582014-11-04 17:06:49 +00003556 struct drm_i915_private *dev_priv = dev->dev_private;
3557 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
Pradeep Bhat30789992014-11-04 17:06:45 +00003558 struct drm_crtc *crtc;
3559
Damien Lespiaua269c582014-11-04 17:06:49 +00003560 skl_ddb_get_hw_state(dev_priv, ddb);
Pradeep Bhat30789992014-11-04 17:06:45 +00003561 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3562 skl_pipe_wm_get_hw_state(crtc);
3563}
3564
Ville Syrjälä243e6a42013-10-14 14:55:24 +03003565static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3566{
3567 struct drm_device *dev = crtc->dev;
3568 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak820c1982013-12-17 14:46:36 +02003569 struct ilk_wm_values *hw = &dev_priv->wm.hw;
Ville Syrjälä243e6a42013-10-14 14:55:24 +03003570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3572 enum pipe pipe = intel_crtc->pipe;
3573 static const unsigned int wm0_pipe_reg[] = {
3574 [PIPE_A] = WM0_PIPEA_ILK,
3575 [PIPE_B] = WM0_PIPEB_ILK,
3576 [PIPE_C] = WM0_PIPEC_IVB,
3577 };
3578
3579 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
Ville Syrjäläa42a5712014-01-07 16:14:08 +02003580 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Ville Syrjäläce0e0712013-12-05 15:51:36 +02003581 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
Ville Syrjälä243e6a42013-10-14 14:55:24 +03003582
Matt Roper3ef00282015-03-09 10:19:24 -07003583 active->pipe_enabled = intel_crtc->active;
Ville Syrjälä2a44b762014-03-07 18:32:09 +02003584
3585 if (active->pipe_enabled) {
Ville Syrjälä243e6a42013-10-14 14:55:24 +03003586 u32 tmp = hw->wm_pipe[pipe];
3587
3588 /*
3589 * For active pipes LP0 watermark is marked as
3590 * enabled, and LP1+ watermaks as disabled since
3591 * we can't really reverse compute them in case
3592 * multiple pipes are active.
3593 */
3594 active->wm[0].enable = true;
3595 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3596 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3597 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3598 active->linetime = hw->wm_linetime[pipe];
3599 } else {
3600 int level, max_level = ilk_wm_max_level(dev);
3601
3602 /*
3603 * For inactive pipes, all watermark levels
3604 * should be marked as enabled but zeroed,
3605 * which is what we'd compute them to.
3606 */
3607 for (level = 0; level <= max_level; level++)
3608 active->wm[level].enable = true;
3609 }
3610}
3611
3612void ilk_wm_get_hw_state(struct drm_device *dev)
3613{
3614 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak820c1982013-12-17 14:46:36 +02003615 struct ilk_wm_values *hw = &dev_priv->wm.hw;
Ville Syrjälä243e6a42013-10-14 14:55:24 +03003616 struct drm_crtc *crtc;
3617
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01003618 for_each_crtc(dev, crtc)
Ville Syrjälä243e6a42013-10-14 14:55:24 +03003619 ilk_pipe_wm_get_hw_state(crtc);
3620
3621 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3622 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3623 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3624
3625 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
Ville Syrjäläcfa76982014-03-07 18:32:08 +02003626 if (INTEL_INFO(dev)->gen >= 7) {
3627 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3628 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3629 }
Ville Syrjälä243e6a42013-10-14 14:55:24 +03003630
Ville Syrjäläa42a5712014-01-07 16:14:08 +02003631 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Ville Syrjäläac9545f2013-12-05 15:51:28 +02003632 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3633 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3634 else if (IS_IVYBRIDGE(dev))
3635 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3636 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
Ville Syrjälä243e6a42013-10-14 14:55:24 +03003637
3638 hw->enable_fbc_wm =
3639 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3640}
3641
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03003642/**
3643 * intel_update_watermarks - update FIFO watermark values based on current modes
3644 *
3645 * Calculate watermark values for the various WM regs based on current mode
3646 * and plane configuration.
3647 *
3648 * There are several cases to deal with here:
3649 * - normal (i.e. non-self-refresh)
3650 * - self-refresh (SR) mode
3651 * - lines are large relative to FIFO size (buffer can hold up to 2)
3652 * - lines are small relative to FIFO size (buffer can hold more than 2
3653 * lines), so need to account for TLB latency
3654 *
3655 * The normal calculation is:
3656 * watermark = dotclock * bytes per pixel * latency
3657 * where latency is platform & configuration dependent (we assume pessimal
3658 * values here).
3659 *
3660 * The SR calculation is:
3661 * watermark = (trunc(latency/line time)+1) * surface width *
3662 * bytes per pixel
3663 * where
3664 * line time = htotal / dotclock
3665 * surface width = hdisplay for normal plane and 64 for cursor
3666 * and latency is assumed to be high, as above.
3667 *
3668 * The final value programmed to the register should always be rounded up,
3669 * and include an extra 2 entries to account for clock crossings.
3670 *
3671 * We don't use the sprite, so we can ignore that. And on Crestline we have
3672 * to set the non-SR watermarks to 8.
3673 */
Ville Syrjälä46ba6142013-09-10 11:40:40 +03003674void intel_update_watermarks(struct drm_crtc *crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03003675{
Ville Syrjälä46ba6142013-09-10 11:40:40 +03003676 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03003677
3678 if (dev_priv->display.update_wm)
Ville Syrjälä46ba6142013-09-10 11:40:40 +03003679 dev_priv->display.update_wm(crtc);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03003680}
3681
Ville Syrjäläadf3d352013-08-06 22:24:11 +03003682void intel_update_sprite_watermarks(struct drm_plane *plane,
3683 struct drm_crtc *crtc,
Damien Lespiaued57cb82014-07-15 09:21:24 +02003684 uint32_t sprite_width,
3685 uint32_t sprite_height,
3686 int pixel_size,
Ville Syrjälä39db4a42013-08-06 22:24:00 +03003687 bool enabled, bool scaled)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03003688{
Ville Syrjäläadf3d352013-08-06 22:24:11 +03003689 struct drm_i915_private *dev_priv = plane->dev->dev_private;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03003690
3691 if (dev_priv->display.update_sprite_wm)
Damien Lespiaued57cb82014-07-15 09:21:24 +02003692 dev_priv->display.update_sprite_wm(plane, crtc,
3693 sprite_width, sprite_height,
Ville Syrjälä39db4a42013-08-06 22:24:00 +03003694 pixel_size, enabled, scaled);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03003695}
3696
Daniel Vetter92703882012-08-09 16:46:01 +02003697/**
3698 * Lock protecting IPS related data structures
Daniel Vetter92703882012-08-09 16:46:01 +02003699 */
3700DEFINE_SPINLOCK(mchdev_lock);
3701
3702/* Global for IPS driver to get at the current i915 device. Protected by
3703 * mchdev_lock. */
3704static struct drm_i915_private *i915_mch_dev;
3705
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003706bool ironlake_set_drps(struct drm_device *dev, u8 val)
3707{
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709 u16 rgvswctl;
3710
Daniel Vetter92703882012-08-09 16:46:01 +02003711 assert_spin_locked(&mchdev_lock);
3712
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003713 rgvswctl = I915_READ16(MEMSWCTL);
3714 if (rgvswctl & MEMCTL_CMD_STS) {
3715 DRM_DEBUG("gpu busy, RCS change rejected\n");
3716 return false; /* still busy with another command */
3717 }
3718
3719 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3720 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3721 I915_WRITE16(MEMSWCTL, rgvswctl);
3722 POSTING_READ16(MEMSWCTL);
3723
3724 rgvswctl |= MEMCTL_CMD_STS;
3725 I915_WRITE16(MEMSWCTL, rgvswctl);
3726
3727 return true;
3728}
3729
Daniel Vetter8090c6b2012-06-24 16:42:32 +02003730static void ironlake_enable_drps(struct drm_device *dev)
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003731{
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 u32 rgvmodectl = I915_READ(MEMMODECTL);
3734 u8 fmax, fmin, fstart, vstart;
3735
Daniel Vetter92703882012-08-09 16:46:01 +02003736 spin_lock_irq(&mchdev_lock);
3737
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003738 /* Enable temp reporting */
3739 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3740 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3741
3742 /* 100ms RC evaluation intervals */
3743 I915_WRITE(RCUPEI, 100000);
3744 I915_WRITE(RCDNEI, 100000);
3745
3746 /* Set max/min thresholds to 90ms and 80ms respectively */
3747 I915_WRITE(RCBMAXAVG, 90000);
3748 I915_WRITE(RCBMINAVG, 80000);
3749
3750 I915_WRITE(MEMIHYST, 1);
3751
3752 /* Set up min, max, and cur for interrupt handling */
3753 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3754 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3755 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3756 MEMMODE_FSTART_SHIFT;
3757
3758 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3759 PXVFREQ_PX_SHIFT;
3760
Daniel Vetter20e4d402012-08-08 23:35:39 +02003761 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3762 dev_priv->ips.fstart = fstart;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003763
Daniel Vetter20e4d402012-08-08 23:35:39 +02003764 dev_priv->ips.max_delay = fstart;
3765 dev_priv->ips.min_delay = fmin;
3766 dev_priv->ips.cur_delay = fstart;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003767
3768 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3769 fmax, fmin, fstart);
3770
3771 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3772
3773 /*
3774 * Interrupts will be enabled in ironlake_irq_postinstall
3775 */
3776
3777 I915_WRITE(VIDSTART, vstart);
3778 POSTING_READ(VIDSTART);
3779
3780 rgvmodectl |= MEMMODE_SWMODE_EN;
3781 I915_WRITE(MEMMODECTL, rgvmodectl);
3782
Daniel Vetter92703882012-08-09 16:46:01 +02003783 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003784 DRM_ERROR("stuck trying to change perf mode\n");
Daniel Vetter92703882012-08-09 16:46:01 +02003785 mdelay(1);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003786
3787 ironlake_set_drps(dev, fstart);
3788
Daniel Vetter20e4d402012-08-08 23:35:39 +02003789 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003790 I915_READ(0x112e0);
Daniel Vetter20e4d402012-08-08 23:35:39 +02003791 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3792 dev_priv->ips.last_count2 = I915_READ(0x112f4);
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00003793 dev_priv->ips.last_time2 = ktime_get_raw_ns();
Daniel Vetter92703882012-08-09 16:46:01 +02003794
3795 spin_unlock_irq(&mchdev_lock);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003796}
3797
Daniel Vetter8090c6b2012-06-24 16:42:32 +02003798static void ironlake_disable_drps(struct drm_device *dev)
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003799{
3800 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter92703882012-08-09 16:46:01 +02003801 u16 rgvswctl;
3802
3803 spin_lock_irq(&mchdev_lock);
3804
3805 rgvswctl = I915_READ16(MEMSWCTL);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003806
3807 /* Ack interrupts, disable EFC interrupt */
3808 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3809 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3810 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3811 I915_WRITE(DEIIR, DE_PCU_EVENT);
3812 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3813
3814 /* Go back to the starting frequency */
Daniel Vetter20e4d402012-08-08 23:35:39 +02003815 ironlake_set_drps(dev, dev_priv->ips.fstart);
Daniel Vetter92703882012-08-09 16:46:01 +02003816 mdelay(1);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003817 rgvswctl |= MEMCTL_CMD_STS;
3818 I915_WRITE(MEMSWCTL, rgvswctl);
Daniel Vetter92703882012-08-09 16:46:01 +02003819 mdelay(1);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003820
Daniel Vetter92703882012-08-09 16:46:01 +02003821 spin_unlock_irq(&mchdev_lock);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003822}
3823
Daniel Vetteracbe9472012-07-26 11:50:05 +02003824/* There's a funny hw issue where the hw returns all 0 when reading from
3825 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3826 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3827 * all limits and the gpu stuck at whatever frequency it is at atm).
3828 */
Akash Goel74ef1172015-03-06 11:07:19 +05303829static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003830{
Chris Wilson7b9e0ae2012-04-28 08:56:39 +01003831 u32 limits;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003832
Daniel Vetter20b46e52012-07-26 11:16:14 +02003833 /* Only set the down limit when we've reached the lowest level to avoid
3834 * getting more interrupts, otherwise leave this clear. This prevents a
3835 * race in the hw when coming out of rc6: There's a tiny window where
3836 * the hw runs at the minimal clock before selecting the desired
3837 * frequency, if the down threshold expires in that window we will not
3838 * receive a down interrupt. */
Akash Goel74ef1172015-03-06 11:07:19 +05303839 if (IS_GEN9(dev_priv->dev)) {
3840 limits = (dev_priv->rps.max_freq_softlimit) << 23;
3841 if (val <= dev_priv->rps.min_freq_softlimit)
3842 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
3843 } else {
3844 limits = dev_priv->rps.max_freq_softlimit << 24;
3845 if (val <= dev_priv->rps.min_freq_softlimit)
3846 limits |= dev_priv->rps.min_freq_softlimit << 16;
3847 }
Daniel Vetter20b46e52012-07-26 11:16:14 +02003848
3849 return limits;
3850}
3851
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003852static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3853{
3854 int new_power;
Akash Goel8a586432015-03-06 11:07:18 +05303855 u32 threshold_up = 0, threshold_down = 0; /* in % */
3856 u32 ei_up = 0, ei_down = 0;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003857
3858 new_power = dev_priv->rps.power;
3859 switch (dev_priv->rps.power) {
3860 case LOW_POWER:
Ben Widawskyb39fb292014-03-19 18:31:11 -07003861 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003862 new_power = BETWEEN;
3863 break;
3864
3865 case BETWEEN:
Ben Widawskyb39fb292014-03-19 18:31:11 -07003866 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003867 new_power = LOW_POWER;
Ben Widawskyb39fb292014-03-19 18:31:11 -07003868 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003869 new_power = HIGH_POWER;
3870 break;
3871
3872 case HIGH_POWER:
Ben Widawskyb39fb292014-03-19 18:31:11 -07003873 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003874 new_power = BETWEEN;
3875 break;
3876 }
3877 /* Max/min bins are special */
Chris Wilsonaed242f2015-03-18 09:48:21 +00003878 if (val <= dev_priv->rps.min_freq_softlimit)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003879 new_power = LOW_POWER;
Chris Wilsonaed242f2015-03-18 09:48:21 +00003880 if (val >= dev_priv->rps.max_freq_softlimit)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003881 new_power = HIGH_POWER;
3882 if (new_power == dev_priv->rps.power)
3883 return;
3884
3885 /* Note the units here are not exactly 1us, but 1280ns. */
3886 switch (new_power) {
3887 case LOW_POWER:
3888 /* Upclock if more than 95% busy over 16ms */
Akash Goel8a586432015-03-06 11:07:18 +05303889 ei_up = 16000;
3890 threshold_up = 95;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003891
3892 /* Downclock if less than 85% busy over 32ms */
Akash Goel8a586432015-03-06 11:07:18 +05303893 ei_down = 32000;
3894 threshold_down = 85;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003895 break;
3896
3897 case BETWEEN:
3898 /* Upclock if more than 90% busy over 13ms */
Akash Goel8a586432015-03-06 11:07:18 +05303899 ei_up = 13000;
3900 threshold_up = 90;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003901
3902 /* Downclock if less than 75% busy over 32ms */
Akash Goel8a586432015-03-06 11:07:18 +05303903 ei_down = 32000;
3904 threshold_down = 75;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003905 break;
3906
3907 case HIGH_POWER:
3908 /* Upclock if more than 85% busy over 10ms */
Akash Goel8a586432015-03-06 11:07:18 +05303909 ei_up = 10000;
3910 threshold_up = 85;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003911
3912 /* Downclock if less than 60% busy over 32ms */
Akash Goel8a586432015-03-06 11:07:18 +05303913 ei_down = 32000;
3914 threshold_down = 60;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003915 break;
3916 }
3917
Akash Goel8a586432015-03-06 11:07:18 +05303918 I915_WRITE(GEN6_RP_UP_EI,
3919 GT_INTERVAL_FROM_US(dev_priv, ei_up));
3920 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3921 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
3922
3923 I915_WRITE(GEN6_RP_DOWN_EI,
3924 GT_INTERVAL_FROM_US(dev_priv, ei_down));
3925 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
3926 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
3927
3928 I915_WRITE(GEN6_RP_CONTROL,
3929 GEN6_RP_MEDIA_TURBO |
3930 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3931 GEN6_RP_MEDIA_IS_GFX |
3932 GEN6_RP_ENABLE |
3933 GEN6_RP_UP_BUSY_AVG |
3934 GEN6_RP_DOWN_IDLE_AVG);
3935
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003936 dev_priv->rps.power = new_power;
Chris Wilson8fb55192015-04-07 16:20:28 +01003937 dev_priv->rps.up_threshold = threshold_up;
3938 dev_priv->rps.down_threshold = threshold_down;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01003939 dev_priv->rps.last_adj = 0;
3940}
3941
Chris Wilson2876ce72014-03-28 08:03:34 +00003942static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3943{
3944 u32 mask = 0;
3945
3946 if (val > dev_priv->rps.min_freq_softlimit)
Chris Wilson6f4b12f82015-03-18 09:48:23 +00003947 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
Chris Wilson2876ce72014-03-28 08:03:34 +00003948 if (val < dev_priv->rps.max_freq_softlimit)
Chris Wilson6f4b12f82015-03-18 09:48:23 +00003949 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
Chris Wilson2876ce72014-03-28 08:03:34 +00003950
Chris Wilson7b3c29f2014-07-10 20:31:19 +01003951 mask &= dev_priv->pm_rps_events;
3952
Imre Deak59d02a12014-12-19 19:33:26 +02003953 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
Chris Wilson2876ce72014-03-28 08:03:34 +00003954}
3955
Jeff McGeeb8a5ff82014-02-04 11:37:01 -06003956/* gen6_set_rps is called to update the frequency request, but should also be
3957 * called when the range (min_delay and max_delay) is modified so that we can
3958 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
Ville Syrjäläffe02b42015-02-02 19:09:50 +02003959static void gen6_set_rps(struct drm_device *dev, u8 val)
Daniel Vetter20b46e52012-07-26 11:16:14 +02003960{
3961 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson7b9e0ae2012-04-28 08:56:39 +01003962
Jesse Barnes4fc688c2012-11-02 11:14:01 -07003963 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
Chris Wilsonaed242f2015-03-18 09:48:21 +00003964 WARN_ON(val > dev_priv->rps.max_freq);
3965 WARN_ON(val < dev_priv->rps.min_freq);
Daniel Vetter004777c2012-08-09 15:07:01 +02003966
Chris Wilsoneb64cad2014-03-27 08:24:20 +00003967 /* min/max delay may still have been modified so be sure to
3968 * write the limits value.
3969 */
3970 if (val != dev_priv->rps.cur_freq) {
3971 gen6_set_rps_thresholds(dev_priv, val);
Jeff McGeeb8a5ff82014-02-04 11:37:01 -06003972
Akash Goel57041952015-03-06 11:07:17 +05303973 if (IS_GEN9(dev))
3974 I915_WRITE(GEN6_RPNSWREQ,
3975 GEN9_FREQUENCY(val));
3976 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Chris Wilsoneb64cad2014-03-27 08:24:20 +00003977 I915_WRITE(GEN6_RPNSWREQ,
3978 HSW_FREQUENCY(val));
3979 else
3980 I915_WRITE(GEN6_RPNSWREQ,
3981 GEN6_FREQUENCY(val) |
3982 GEN6_OFFSET(0) |
3983 GEN6_AGGRESSIVE_TURBO);
Jeff McGeeb8a5ff82014-02-04 11:37:01 -06003984 }
Chris Wilson7b9e0ae2012-04-28 08:56:39 +01003985
Chris Wilson7b9e0ae2012-04-28 08:56:39 +01003986 /* Make sure we continue to get interrupts
3987 * until we hit the minimum or maximum frequencies.
3988 */
Akash Goel74ef1172015-03-06 11:07:19 +05303989 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
Chris Wilson2876ce72014-03-28 08:03:34 +00003990 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
Chris Wilson7b9e0ae2012-04-28 08:56:39 +01003991
Ben Widawskyd5570a72012-09-07 19:43:41 -07003992 POSTING_READ(GEN6_RPNSWREQ);
3993
Ben Widawskyb39fb292014-03-19 18:31:11 -07003994 dev_priv->rps.cur_freq = val;
Daniel Vetterbe2cde92012-08-30 13:26:48 +02003995 trace_intel_gpu_freq_change(val * 50);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03003996}
3997
Ville Syrjäläffe02b42015-02-02 19:09:50 +02003998static void valleyview_set_rps(struct drm_device *dev, u8 val)
3999{
4000 struct drm_i915_private *dev_priv = dev->dev_private;
4001
4002 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
Chris Wilsonaed242f2015-03-18 09:48:21 +00004003 WARN_ON(val > dev_priv->rps.max_freq);
4004 WARN_ON(val < dev_priv->rps.min_freq);
Ville Syrjäläffe02b42015-02-02 19:09:50 +02004005
4006 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4007 "Odd GPU freq value\n"))
4008 val &= ~1;
4009
Chris Wilson8fb55192015-04-07 16:20:28 +01004010 if (val != dev_priv->rps.cur_freq) {
Ville Syrjäläffe02b42015-02-02 19:09:50 +02004011 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
Chris Wilson8fb55192015-04-07 16:20:28 +01004012 if (!IS_CHERRYVIEW(dev_priv))
4013 gen6_set_rps_thresholds(dev_priv, val);
4014 }
Ville Syrjäläffe02b42015-02-02 19:09:50 +02004015
4016 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4017
4018 dev_priv->rps.cur_freq = val;
4019 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4020}
4021
Deepak S76c3552f2014-01-30 23:08:16 +05304022/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
4023 *
4024 * * If Gfx is Idle, then
4025 * 1. Mask Turbo interrupts
4026 * 2. Bring up Gfx clock
4027 * 3. Change the freq to Rpn and wait till P-Unit updates freq
4028 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
4029 * 5. Unmask Turbo interrupts
4030*/
4031static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4032{
Deepak S5549d252014-06-28 11:26:11 +05304033 struct drm_device *dev = dev_priv->dev;
Chris Wilsonaed242f2015-03-18 09:48:21 +00004034 u32 val = dev_priv->rps.idle_freq;
Deepak S5549d252014-06-28 11:26:11 +05304035
Ville Syrjälä21a11ff2015-01-27 16:36:15 +02004036 /* CHV and latest VLV don't need to force the gfx clock */
4037 if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) {
Chris Wilsonaed242f2015-03-18 09:48:21 +00004038 valleyview_set_rps(dev_priv->dev, val);
Deepak S5549d252014-06-28 11:26:11 +05304039 return;
4040 }
4041
Deepak S76c3552f2014-01-30 23:08:16 +05304042 /*
4043 * When we are idle. Drop to min voltage state.
4044 */
4045
Chris Wilsonaed242f2015-03-18 09:48:21 +00004046 if (dev_priv->rps.cur_freq <= val)
Deepak S76c3552f2014-01-30 23:08:16 +05304047 return;
4048
4049 /* Mask turbo interrupt so that they will not come in between */
Imre Deakf24eeb12014-12-19 19:33:27 +02004050 I915_WRITE(GEN6_PMINTRMSK,
4051 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
Deepak S76c3552f2014-01-30 23:08:16 +05304052
Imre Deak650ad972014-04-18 16:35:02 +03004053 vlv_force_gfx_clock(dev_priv, true);
Deepak S76c3552f2014-01-30 23:08:16 +05304054
Chris Wilsonaed242f2015-03-18 09:48:21 +00004055 dev_priv->rps.cur_freq = val;
Deepak S76c3552f2014-01-30 23:08:16 +05304056
Chris Wilsonaed242f2015-03-18 09:48:21 +00004057 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
Deepak S76c3552f2014-01-30 23:08:16 +05304058
4059 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
Imre Deak2837ac42014-11-19 16:25:38 +02004060 & GENFREQSTATUS) == 0, 100))
Deepak S76c3552f2014-01-30 23:08:16 +05304061 DRM_ERROR("timed out waiting for Punit\n");
4062
Chris Wilson8fb55192015-04-07 16:20:28 +01004063 gen6_set_rps_thresholds(dev_priv, val);
Imre Deak650ad972014-04-18 16:35:02 +03004064 vlv_force_gfx_clock(dev_priv, false);
Deepak S76c3552f2014-01-30 23:08:16 +05304065
Chris Wilsonaed242f2015-03-18 09:48:21 +00004066 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
Deepak S76c3552f2014-01-30 23:08:16 +05304067}
4068
Chris Wilson43cf3bf2015-03-18 09:48:22 +00004069void gen6_rps_busy(struct drm_i915_private *dev_priv)
4070{
4071 mutex_lock(&dev_priv->rps.hw_lock);
4072 if (dev_priv->rps.enabled) {
4073 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4074 gen6_rps_reset_ei(dev_priv);
4075 I915_WRITE(GEN6_PMINTRMSK,
4076 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4077 }
4078 mutex_unlock(&dev_priv->rps.hw_lock);
4079}
4080
Chris Wilsonb29c19b2013-09-25 17:34:56 +01004081void gen6_rps_idle(struct drm_i915_private *dev_priv)
4082{
Damien Lespiau691bb712013-12-12 14:36:36 +00004083 struct drm_device *dev = dev_priv->dev;
4084
Chris Wilsonb29c19b2013-09-25 17:34:56 +01004085 mutex_lock(&dev_priv->rps.hw_lock);
Chris Wilsonc0951f02013-10-10 21:58:50 +01004086 if (dev_priv->rps.enabled) {
Ville Syrjälä21a11ff2015-01-27 16:36:15 +02004087 if (IS_VALLEYVIEW(dev))
Deepak S76c3552f2014-01-30 23:08:16 +05304088 vlv_set_rps_idle(dev_priv);
Daniel Vetter7526ed72014-09-29 15:07:19 +02004089 else
Chris Wilsonaed242f2015-03-18 09:48:21 +00004090 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
Chris Wilsonc0951f02013-10-10 21:58:50 +01004091 dev_priv->rps.last_adj = 0;
Chris Wilson43cf3bf2015-03-18 09:48:22 +00004092 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
Chris Wilsonc0951f02013-10-10 21:58:50 +01004093 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01004094 mutex_unlock(&dev_priv->rps.hw_lock);
4095}
4096
4097void gen6_rps_boost(struct drm_i915_private *dev_priv)
4098{
Chris Wilson43cf3bf2015-03-18 09:48:22 +00004099 u32 val;
4100
Chris Wilsonb29c19b2013-09-25 17:34:56 +01004101 mutex_lock(&dev_priv->rps.hw_lock);
Chris Wilson43cf3bf2015-03-18 09:48:22 +00004102 val = dev_priv->rps.max_freq_softlimit;
4103 if (dev_priv->rps.enabled &&
4104 dev_priv->mm.busy &&
4105 dev_priv->rps.cur_freq < val) {
4106 intel_set_rps(dev_priv->dev, val);
Chris Wilsonc0951f02013-10-10 21:58:50 +01004107 dev_priv->rps.last_adj = 0;
4108 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01004109 mutex_unlock(&dev_priv->rps.hw_lock);
4110}
4111
Ville Syrjäläffe02b42015-02-02 19:09:50 +02004112void intel_set_rps(struct drm_device *dev, u8 val)
Jesse Barnes0a073b82013-04-17 15:54:58 -07004113{
Ville Syrjäläffe02b42015-02-02 19:09:50 +02004114 if (IS_VALLEYVIEW(dev))
4115 valleyview_set_rps(dev, val);
4116 else
4117 gen6_set_rps(dev, val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07004118}
4119
Zhe Wang20e49362014-11-04 17:07:05 +00004120static void gen9_disable_rps(struct drm_device *dev)
4121{
4122 struct drm_i915_private *dev_priv = dev->dev_private;
4123
4124 I915_WRITE(GEN6_RC_CONTROL, 0);
Zhe Wang38c23522015-01-20 12:23:04 +00004125 I915_WRITE(GEN9_PG_ENABLE, 0);
Zhe Wang20e49362014-11-04 17:07:05 +00004126}
4127
Daniel Vetter44fc7d52013-07-12 22:43:27 +02004128static void gen6_disable_rps(struct drm_device *dev)
4129{
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4131
4132 I915_WRITE(GEN6_RC_CONTROL, 0);
4133 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
Daniel Vetter44fc7d52013-07-12 22:43:27 +02004134}
4135
Deepak S38807742014-05-23 21:00:15 +05304136static void cherryview_disable_rps(struct drm_device *dev)
4137{
4138 struct drm_i915_private *dev_priv = dev->dev_private;
4139
4140 I915_WRITE(GEN6_RC_CONTROL, 0);
4141}
4142
Jesse Barnesd20d4f02013-04-23 10:09:28 -07004143static void valleyview_disable_rps(struct drm_device *dev)
4144{
4145 struct drm_i915_private *dev_priv = dev->dev_private;
4146
Deepak S98a2e5f2014-08-18 10:35:27 -07004147 /* we're doing forcewake before Disabling RC6,
4148 * This what the BIOS expects when going into suspend */
Mika Kuoppala59bad942015-01-16 11:34:40 +02004149 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Deepak S98a2e5f2014-08-18 10:35:27 -07004150
Jesse Barnesd20d4f02013-04-23 10:09:28 -07004151 I915_WRITE(GEN6_RC_CONTROL, 0);
Jesse Barnesd20d4f02013-04-23 10:09:28 -07004152
Mika Kuoppala59bad942015-01-16 11:34:40 +02004153 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Jesse Barnesd20d4f02013-04-23 10:09:28 -07004154}
4155
Ben Widawskydc39fff2013-10-18 12:32:07 -07004156static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4157{
Imre Deak91ca6892014-04-14 20:24:25 +03004158 if (IS_VALLEYVIEW(dev)) {
4159 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4160 mode = GEN6_RC_CTL_RC6_ENABLE;
4161 else
4162 mode = 0;
4163 }
Rodrigo Vivi58abf1d2014-10-07 07:06:50 -07004164 if (HAS_RC6p(dev))
4165 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4166 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4167 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4168 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4169
4170 else
4171 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4172 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
Ben Widawskydc39fff2013-10-18 12:32:07 -07004173}
4174
Imre Deake6069ca2014-04-18 16:01:02 +03004175static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004176{
Damien Lespiaueb4926e2013-06-07 17:41:14 +01004177 /* No RC6 before Ironlake */
4178 if (INTEL_INFO(dev)->gen < 5)
4179 return 0;
4180
Imre Deake6069ca2014-04-18 16:01:02 +03004181 /* RC6 is only on Ironlake mobile not on desktop */
4182 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
4183 return 0;
4184
Daniel Vetter456470e2012-08-08 23:35:40 +02004185 /* Respect the kernel parameter if it is set */
Imre Deake6069ca2014-04-18 16:01:02 +03004186 if (enable_rc6 >= 0) {
4187 int mask;
4188
Rodrigo Vivi58abf1d2014-10-07 07:06:50 -07004189 if (HAS_RC6p(dev))
Imre Deake6069ca2014-04-18 16:01:02 +03004190 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4191 INTEL_RC6pp_ENABLE;
4192 else
4193 mask = INTEL_RC6_ENABLE;
4194
4195 if ((enable_rc6 & mask) != enable_rc6)
Daniel Vetter8dfd1f02014-08-04 11:15:56 +02004196 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4197 enable_rc6 & mask, enable_rc6, mask);
Imre Deake6069ca2014-04-18 16:01:02 +03004198
4199 return enable_rc6 & mask;
4200 }
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004201
Chris Wilson6567d742012-11-10 10:00:06 +00004202 /* Disable RC6 on Ironlake */
4203 if (INTEL_INFO(dev)->gen == 5)
4204 return 0;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004205
Ben Widawsky8bade1a2014-01-28 20:25:39 -08004206 if (IS_IVYBRIDGE(dev))
Ben Widawskycca84a12014-01-28 20:25:38 -08004207 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
Ben Widawsky8bade1a2014-01-28 20:25:39 -08004208
4209 return INTEL_RC6_ENABLE;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004210}
4211
Imre Deake6069ca2014-04-18 16:01:02 +03004212int intel_enable_rc6(const struct drm_device *dev)
4213{
4214 return i915.enable_rc6;
4215}
4216
Tom O'Rourke93ee2922014-11-19 14:21:52 -08004217static void gen6_init_rps_frequencies(struct drm_device *dev)
Ben Widawsky3280e8b2014-03-31 17:16:42 -07004218{
Tom O'Rourke93ee2922014-11-19 14:21:52 -08004219 struct drm_i915_private *dev_priv = dev->dev_private;
4220 uint32_t rp_state_cap;
4221 u32 ddcc_status = 0;
4222 int ret;
4223
4224 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
Ben Widawsky3280e8b2014-03-31 17:16:42 -07004225 /* All of these values are in units of 50MHz */
4226 dev_priv->rps.cur_freq = 0;
Tom O'Rourke93ee2922014-11-19 14:21:52 -08004227 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
Ben Widawsky3280e8b2014-03-31 17:16:42 -07004228 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
Tom O'Rourke93ee2922014-11-19 14:21:52 -08004229 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
Ben Widawsky3280e8b2014-03-31 17:16:42 -07004230 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
Akash Goelcee991c2015-03-06 11:07:16 +05304231 if (IS_SKYLAKE(dev)) {
4232 /* Store the frequency values in 16.66 MHZ units, which is
4233 the natural hardware unit for SKL */
4234 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4235 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4236 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4237 }
Ben Widawsky3280e8b2014-03-31 17:16:42 -07004238 /* hw_max = RP0 until we check for overclocking */
4239 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4240
Tom O'Rourke93ee2922014-11-19 14:21:52 -08004241 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4242 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4243 ret = sandybridge_pcode_read(dev_priv,
4244 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4245 &ddcc_status);
4246 if (0 == ret)
4247 dev_priv->rps.efficient_freq =
Tom O'Rourke46efa4a2015-02-10 23:06:46 -08004248 clamp_t(u8,
4249 ((ddcc_status >> 8) & 0xff),
4250 dev_priv->rps.min_freq,
4251 dev_priv->rps.max_freq);
Tom O'Rourke93ee2922014-11-19 14:21:52 -08004252 }
4253
Chris Wilsonaed242f2015-03-18 09:48:21 +00004254 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4255
Ben Widawsky3280e8b2014-03-31 17:16:42 -07004256 /* Preserve min/max settings in case of re-init */
4257 if (dev_priv->rps.max_freq_softlimit == 0)
4258 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4259
Tom O'Rourke93ee2922014-11-19 14:21:52 -08004260 if (dev_priv->rps.min_freq_softlimit == 0) {
4261 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4262 dev_priv->rps.min_freq_softlimit =
Tom O'Rourkef4ab4082014-11-19 14:21:53 -08004263 /* max(RPe, 450 MHz) */
4264 max(dev_priv->rps.efficient_freq, (u8) 9);
Tom O'Rourke93ee2922014-11-19 14:21:52 -08004265 else
4266 dev_priv->rps.min_freq_softlimit =
4267 dev_priv->rps.min_freq;
4268 }
Ben Widawsky3280e8b2014-03-31 17:16:42 -07004269}
4270
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00004271/* See the Gen9_GT_PM_Programming_Guide doc for the below */
Zhe Wang20e49362014-11-04 17:07:05 +00004272static void gen9_enable_rps(struct drm_device *dev)
4273{
4274 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00004275
4276 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4277
Damien Lespiauba1c5542015-01-16 18:07:26 +00004278 gen6_init_rps_frequencies(dev);
4279
Akash Goel0beb0592015-03-06 11:07:20 +05304280 /* Program defaults and thresholds for RPS*/
4281 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4282 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00004283
Akash Goel0beb0592015-03-06 11:07:20 +05304284 /* 1 second timeout*/
4285 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4286 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4287
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00004288 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00004289
Akash Goel0beb0592015-03-06 11:07:20 +05304290 /* Leaning on the below call to gen6_set_rps to program/setup the
4291 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4292 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4293 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4294 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00004295
4296 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4297}
4298
4299static void gen9_enable_rc6(struct drm_device *dev)
4300{
4301 struct drm_i915_private *dev_priv = dev->dev_private;
Zhe Wang20e49362014-11-04 17:07:05 +00004302 struct intel_engine_cs *ring;
4303 uint32_t rc6_mask = 0;
4304 int unused;
4305
4306 /* 1a: Software RC state - RC0 */
4307 I915_WRITE(GEN6_RC_STATE, 0);
4308
4309 /* 1b: Get forcewake during program sequence. Although the driver
4310 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
Mika Kuoppala59bad942015-01-16 11:34:40 +02004311 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Zhe Wang20e49362014-11-04 17:07:05 +00004312
4313 /* 2a: Disable RC states. */
4314 I915_WRITE(GEN6_RC_CONTROL, 0);
4315
4316 /* 2b: Program RC6 thresholds.*/
4317 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4318 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4319 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4320 for_each_ring(ring, dev_priv, unused)
4321 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4322 I915_WRITE(GEN6_RC_SLEEP, 0);
4323 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4324
Zhe Wang38c23522015-01-20 12:23:04 +00004325 /* 2c: Program Coarse Power Gating Policies. */
4326 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4327 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4328
Zhe Wang20e49362014-11-04 17:07:05 +00004329 /* 3a: Enable RC6 */
4330 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4331 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4332 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4333 "on" : "off");
4334 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4335 GEN6_RC_CTL_EI_MODE(1) |
4336 rc6_mask);
4337
Zhe Wang38c23522015-01-20 12:23:04 +00004338 /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
4339 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
4340
Mika Kuoppala59bad942015-01-16 11:34:40 +02004341 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Zhe Wang20e49362014-11-04 17:07:05 +00004342
4343}
4344
Ben Widawsky6edee7f2013-11-02 21:07:52 -07004345static void gen8_enable_rps(struct drm_device *dev)
4346{
4347 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01004348 struct intel_engine_cs *ring;
Tom O'Rourke93ee2922014-11-19 14:21:52 -08004349 uint32_t rc6_mask = 0;
Ben Widawsky6edee7f2013-11-02 21:07:52 -07004350 int unused;
4351
4352 /* 1a: Software RC state - RC0 */
4353 I915_WRITE(GEN6_RC_STATE, 0);
4354
4355 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4356 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
Mika Kuoppala59bad942015-01-16 11:34:40 +02004357 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07004358
4359 /* 2a: Disable RC states. */
4360 I915_WRITE(GEN6_RC_CONTROL, 0);
4361
Tom O'Rourke93ee2922014-11-19 14:21:52 -08004362 /* Initialize rps frequencies */
4363 gen6_init_rps_frequencies(dev);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07004364
4365 /* 2b: Program RC6 thresholds.*/
4366 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4367 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4368 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4369 for_each_ring(ring, dev_priv, unused)
4370 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4371 I915_WRITE(GEN6_RC_SLEEP, 0);
Tom O'Rourke0d68b252014-04-09 11:44:06 -07004372 if (IS_BROADWELL(dev))
4373 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4374 else
4375 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
Ben Widawsky6edee7f2013-11-02 21:07:52 -07004376
4377 /* 3: Enable RC6 */
4378 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4379 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
Ben Widawskyabbf9d22014-01-28 20:25:41 -08004380 intel_print_rc6_info(dev, rc6_mask);
Tom O'Rourke0d68b252014-04-09 11:44:06 -07004381 if (IS_BROADWELL(dev))
4382 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4383 GEN7_RC_CTL_TO_MODE |
4384 rc6_mask);
4385 else
4386 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4387 GEN6_RC_CTL_EI_MODE(1) |
4388 rc6_mask);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07004389
4390 /* 4 Program defaults and thresholds for RPS*/
Ben Widawskyf9bdc582014-03-31 17:16:41 -07004391 I915_WRITE(GEN6_RPNSWREQ,
4392 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4393 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4394 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
Daniel Vetter7526ed72014-09-29 15:07:19 +02004395 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4396 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
Ben Widawsky6edee7f2013-11-02 21:07:52 -07004397
Daniel Vetter7526ed72014-09-29 15:07:19 +02004398 /* Docs recommend 900MHz, and 300 MHz respectively */
4399 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4400 dev_priv->rps.max_freq_softlimit << 24 |
4401 dev_priv->rps.min_freq_softlimit << 16);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07004402
Daniel Vetter7526ed72014-09-29 15:07:19 +02004403 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4404 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4405 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4406 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
Ben Widawsky6edee7f2013-11-02 21:07:52 -07004407
Daniel Vetter7526ed72014-09-29 15:07:19 +02004408 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07004409
4410 /* 5: Enable RPS */
Daniel Vetter7526ed72014-09-29 15:07:19 +02004411 I915_WRITE(GEN6_RP_CONTROL,
4412 GEN6_RP_MEDIA_TURBO |
4413 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4414 GEN6_RP_MEDIA_IS_GFX |
4415 GEN6_RP_ENABLE |
4416 GEN6_RP_UP_BUSY_AVG |
4417 GEN6_RP_DOWN_IDLE_AVG);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07004418
Daniel Vetter7526ed72014-09-29 15:07:19 +02004419 /* 6: Ring frequency + overclocking (our driver does this later */
Ben Widawsky6edee7f2013-11-02 21:07:52 -07004420
Tom O'Rourkec7f31532014-11-19 14:21:54 -08004421 dev_priv->rps.power = HIGH_POWER; /* force a reset */
Chris Wilsonaed242f2015-03-18 09:48:21 +00004422 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
Daniel Vetter7526ed72014-09-29 15:07:19 +02004423
Mika Kuoppala59bad942015-01-16 11:34:40 +02004424 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07004425}
4426
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02004427static void gen6_enable_rps(struct drm_device *dev)
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004428{
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02004429 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01004430 struct intel_engine_cs *ring;
Ben Widawskyd060c162014-03-19 18:31:08 -07004431 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004432 u32 gtfifodbg;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004433 int rc6_mode;
Ben Widawsky42c05262012-09-26 10:34:00 -07004434 int i, ret;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004435
Jesse Barnes4fc688c2012-11-02 11:14:01 -07004436 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02004437
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004438 /* Here begins a magic sequence of register writes to enable
4439 * auto-downclocking.
4440 *
4441 * Perhaps there might be some value in exposing these to
4442 * userspace...
4443 */
4444 I915_WRITE(GEN6_RC_STATE, 0);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004445
4446 /* Clear the DBG now so we don't confuse earlier errors */
4447 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4448 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4449 I915_WRITE(GTFIFODBG, gtfifodbg);
4450 }
4451
Mika Kuoppala59bad942015-01-16 11:34:40 +02004452 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004453
Tom O'Rourke93ee2922014-11-19 14:21:52 -08004454 /* Initialize rps frequencies */
4455 gen6_init_rps_frequencies(dev);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004456
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004457 /* disable the counters and set deterministic thresholds */
4458 I915_WRITE(GEN6_RC_CONTROL, 0);
4459
4460 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4461 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4462 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4463 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4464 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4465
Chris Wilsonb4519512012-05-11 14:29:30 +01004466 for_each_ring(ring, dev_priv, i)
4467 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004468
4469 I915_WRITE(GEN6_RC_SLEEP, 0);
4470 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
Daniel Vetter29c78f62013-11-16 16:04:26 +01004471 if (IS_IVYBRIDGE(dev))
Stéphane Marchesin351aa562013-08-13 11:55:17 -07004472 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4473 else
4474 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
Stéphane Marchesin0920a482013-01-29 19:41:59 -08004475 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004476 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4477
Eugeni Dodonov5a7dc922012-07-02 11:51:05 -03004478 /* Check if we are enabling RC6 */
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004479 rc6_mode = intel_enable_rc6(dev_priv->dev);
4480 if (rc6_mode & INTEL_RC6_ENABLE)
4481 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4482
Eugeni Dodonov5a7dc922012-07-02 11:51:05 -03004483 /* We don't use those on Haswell */
4484 if (!IS_HASWELL(dev)) {
4485 if (rc6_mode & INTEL_RC6p_ENABLE)
4486 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004487
Eugeni Dodonov5a7dc922012-07-02 11:51:05 -03004488 if (rc6_mode & INTEL_RC6pp_ENABLE)
4489 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4490 }
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004491
Ben Widawskydc39fff2013-10-18 12:32:07 -07004492 intel_print_rc6_info(dev, rc6_mask);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004493
4494 I915_WRITE(GEN6_RC_CONTROL,
4495 rc6_mask |
4496 GEN6_RC_CTL_EI_MODE(1) |
4497 GEN6_RC_CTL_HW_ENABLE);
4498
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004499 /* Power down if completely idle for over 50ms */
4500 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004501 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004502
Ben Widawsky42c05262012-09-26 10:34:00 -07004503 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
Ben Widawskyd060c162014-03-19 18:31:08 -07004504 if (ret)
Ben Widawsky42c05262012-09-26 10:34:00 -07004505 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
Ben Widawskyd060c162014-03-19 18:31:08 -07004506
4507 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4508 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4509 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
Ben Widawskyb39fb292014-03-19 18:31:11 -07004510 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
Ben Widawskyd060c162014-03-19 18:31:08 -07004511 (pcu_mbox & 0xff) * 50);
Ben Widawskyb39fb292014-03-19 18:31:11 -07004512 dev_priv->rps.max_freq = pcu_mbox & 0xff;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004513 }
4514
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004515 dev_priv->rps.power = HIGH_POWER; /* force a reset */
Chris Wilsonaed242f2015-03-18 09:48:21 +00004516 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004517
Ben Widawsky31643d52012-09-26 10:34:01 -07004518 rc6vids = 0;
4519 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4520 if (IS_GEN6(dev) && ret) {
4521 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4522 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4523 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4524 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4525 rc6vids &= 0xffff00;
4526 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4527 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4528 if (ret)
4529 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4530 }
4531
Mika Kuoppala59bad942015-01-16 11:34:40 +02004532 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004533}
4534
Imre Deakc2bc2fc2014-04-18 16:16:23 +03004535static void __gen6_update_ring_freq(struct drm_device *dev)
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004536{
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02004537 struct drm_i915_private *dev_priv = dev->dev_private;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004538 int min_freq = 15;
Chris Wilson3ebecd02013-04-12 19:10:13 +01004539 unsigned int gpu_freq;
4540 unsigned int max_ia_freq, min_ring_freq;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004541 int scaling_factor = 180;
Ben Widawskyeda79642013-10-07 17:15:48 -03004542 struct cpufreq_policy *policy;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004543
Jesse Barnes4fc688c2012-11-02 11:14:01 -07004544 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02004545
Ben Widawskyeda79642013-10-07 17:15:48 -03004546 policy = cpufreq_cpu_get(0);
4547 if (policy) {
4548 max_ia_freq = policy->cpuinfo.max_freq;
4549 cpufreq_cpu_put(policy);
4550 } else {
4551 /*
4552 * Default to measured freq if none found, PCU will ensure we
4553 * don't go over
4554 */
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004555 max_ia_freq = tsc_khz;
Ben Widawskyeda79642013-10-07 17:15:48 -03004556 }
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004557
4558 /* Convert from kHz to MHz */
4559 max_ia_freq /= 1000;
4560
Ben Widawsky153b4b952013-10-22 22:05:09 -07004561 min_ring_freq = I915_READ(DCLK) & 0xf;
Ben Widawskyf6aca452013-10-02 09:25:02 -07004562 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4563 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
Chris Wilson3ebecd02013-04-12 19:10:13 +01004564
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004565 /*
4566 * For each potential GPU frequency, load a ring frequency we'd like
4567 * to use for memory access. We do this by specifying the IA frequency
4568 * the PCU should use as a reference to determine the ring frequency.
4569 */
Tom O'Rourke6985b352014-11-19 14:21:55 -08004570 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004571 gpu_freq--) {
Tom O'Rourke6985b352014-11-19 14:21:55 -08004572 int diff = dev_priv->rps.max_freq - gpu_freq;
Chris Wilson3ebecd02013-04-12 19:10:13 +01004573 unsigned int ia_freq = 0, ring_freq = 0;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004574
Ben Widawsky46c764d2013-11-02 21:07:49 -07004575 if (INTEL_INFO(dev)->gen >= 8) {
4576 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4577 ring_freq = max(min_ring_freq, gpu_freq);
4578 } else if (IS_HASWELL(dev)) {
Ben Widawskyf6aca452013-10-02 09:25:02 -07004579 ring_freq = mult_frac(gpu_freq, 5, 4);
Chris Wilson3ebecd02013-04-12 19:10:13 +01004580 ring_freq = max(min_ring_freq, ring_freq);
4581 /* leave ia_freq as the default, chosen by cpufreq */
4582 } else {
4583 /* On older processors, there is no separate ring
4584 * clock domain, so in order to boost the bandwidth
4585 * of the ring, we need to upclock the CPU (ia_freq).
4586 *
4587 * For GPU frequencies less than 750MHz,
4588 * just use the lowest ring freq.
4589 */
4590 if (gpu_freq < min_freq)
4591 ia_freq = 800;
4592 else
4593 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4594 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4595 }
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004596
Ben Widawsky42c05262012-09-26 10:34:00 -07004597 sandybridge_pcode_write(dev_priv,
4598 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
Chris Wilson3ebecd02013-04-12 19:10:13 +01004599 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4600 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4601 gpu_freq);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004602 }
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004603}
4604
Imre Deakc2bc2fc2014-04-18 16:16:23 +03004605void gen6_update_ring_freq(struct drm_device *dev)
4606{
4607 struct drm_i915_private *dev_priv = dev->dev_private;
4608
4609 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4610 return;
4611
4612 mutex_lock(&dev_priv->rps.hw_lock);
4613 __gen6_update_ring_freq(dev);
4614 mutex_unlock(&dev_priv->rps.hw_lock);
4615}
4616
Ville Syrjälä03af2042014-06-28 02:03:53 +03004617static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
Deepak S2b6b3a02014-05-27 15:59:30 +05304618{
Deepak S095acd52015-01-17 11:05:59 +05304619 struct drm_device *dev = dev_priv->dev;
Deepak S2b6b3a02014-05-27 15:59:30 +05304620 u32 val, rp0;
4621
Deepak S095acd52015-01-17 11:05:59 +05304622 if (dev->pdev->revision >= 0x20) {
4623 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
Deepak S2b6b3a02014-05-27 15:59:30 +05304624
Deepak S095acd52015-01-17 11:05:59 +05304625 switch (INTEL_INFO(dev)->eu_total) {
4626 case 8:
4627 /* (2 * 4) config */
4628 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4629 break;
4630 case 12:
4631 /* (2 * 6) config */
4632 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4633 break;
4634 case 16:
4635 /* (2 * 8) config */
4636 default:
4637 /* Setting (2 * 8) Min RP0 for any other combination */
4638 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4639 break;
4640 }
4641 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4642 } else {
4643 /* For pre-production hardware */
4644 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4645 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4646 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4647 }
Deepak S2b6b3a02014-05-27 15:59:30 +05304648 return rp0;
4649}
4650
4651static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4652{
4653 u32 val, rpe;
4654
4655 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4656 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4657
4658 return rpe;
4659}
4660
Deepak S7707df42014-07-12 18:46:14 +05304661static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4662{
Deepak S095acd52015-01-17 11:05:59 +05304663 struct drm_device *dev = dev_priv->dev;
Deepak S7707df42014-07-12 18:46:14 +05304664 u32 val, rp1;
4665
Deepak S095acd52015-01-17 11:05:59 +05304666 if (dev->pdev->revision >= 0x20) {
4667 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4668 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4669 } else {
4670 /* For pre-production hardware */
4671 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4672 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4673 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4674 }
Deepak S7707df42014-07-12 18:46:14 +05304675 return rp1;
4676}
4677
Ville Syrjälä03af2042014-06-28 02:03:53 +03004678static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
Deepak S2b6b3a02014-05-27 15:59:30 +05304679{
Deepak S095acd52015-01-17 11:05:59 +05304680 struct drm_device *dev = dev_priv->dev;
Deepak S2b6b3a02014-05-27 15:59:30 +05304681 u32 val, rpn;
4682
Deepak S095acd52015-01-17 11:05:59 +05304683 if (dev->pdev->revision >= 0x20) {
4684 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
4685 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
4686 FB_GFX_FREQ_FUSE_MASK);
4687 } else { /* For pre-production hardware */
4688 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4689 rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
4690 PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
4691 }
4692
Deepak S2b6b3a02014-05-27 15:59:30 +05304693 return rpn;
4694}
4695
Deepak Sf8f2b002014-07-10 13:16:21 +05304696static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4697{
4698 u32 val, rp1;
4699
4700 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4701
4702 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4703
4704 return rp1;
4705}
4706
Ville Syrjälä03af2042014-06-28 02:03:53 +03004707static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
Jesse Barnes0a073b82013-04-17 15:54:58 -07004708{
4709 u32 val, rp0;
4710
Jani Nikula64936252013-05-22 15:36:20 +03004711 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
Jesse Barnes0a073b82013-04-17 15:54:58 -07004712
4713 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4714 /* Clamp to max */
4715 rp0 = min_t(u32, rp0, 0xea);
4716
4717 return rp0;
4718}
4719
4720static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4721{
4722 u32 val, rpe;
4723
Jani Nikula64936252013-05-22 15:36:20 +03004724 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
Jesse Barnes0a073b82013-04-17 15:54:58 -07004725 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
Jani Nikula64936252013-05-22 15:36:20 +03004726 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
Jesse Barnes0a073b82013-04-17 15:54:58 -07004727 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4728
4729 return rpe;
4730}
4731
Ville Syrjälä03af2042014-06-28 02:03:53 +03004732static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
Jesse Barnes0a073b82013-04-17 15:54:58 -07004733{
Jani Nikula64936252013-05-22 15:36:20 +03004734 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
Jesse Barnes0a073b82013-04-17 15:54:58 -07004735}
4736
Imre Deakae484342014-03-31 15:10:44 +03004737/* Check that the pctx buffer wasn't move under us. */
4738static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4739{
4740 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4741
4742 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4743 dev_priv->vlv_pctx->stolen->start);
4744}
4745
Deepak S38807742014-05-23 21:00:15 +05304746
4747/* Check that the pcbr address is not empty. */
4748static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4749{
4750 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4751
4752 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4753}
4754
4755static void cherryview_setup_pctx(struct drm_device *dev)
4756{
4757 struct drm_i915_private *dev_priv = dev->dev_private;
4758 unsigned long pctx_paddr, paddr;
4759 struct i915_gtt *gtt = &dev_priv->gtt;
4760 u32 pcbr;
4761 int pctx_size = 32*1024;
4762
4763 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4764
4765 pcbr = I915_READ(VLV_PCBR);
4766 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
Ville Syrjäläce611ef2014-11-07 21:33:46 +02004767 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
Deepak S38807742014-05-23 21:00:15 +05304768 paddr = (dev_priv->mm.stolen_base +
4769 (gtt->stolen_size - pctx_size));
4770
4771 pctx_paddr = (paddr & (~4095));
4772 I915_WRITE(VLV_PCBR, pctx_paddr);
4773 }
Ville Syrjäläce611ef2014-11-07 21:33:46 +02004774
4775 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
Deepak S38807742014-05-23 21:00:15 +05304776}
4777
Jesse Barnesc9cddff2013-05-08 10:45:13 -07004778static void valleyview_setup_pctx(struct drm_device *dev)
4779{
4780 struct drm_i915_private *dev_priv = dev->dev_private;
4781 struct drm_i915_gem_object *pctx;
4782 unsigned long pctx_paddr;
4783 u32 pcbr;
4784 int pctx_size = 24*1024;
4785
Imre Deak17b0c1f2014-02-11 21:39:06 +02004786 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4787
Jesse Barnesc9cddff2013-05-08 10:45:13 -07004788 pcbr = I915_READ(VLV_PCBR);
4789 if (pcbr) {
4790 /* BIOS set it up already, grab the pre-alloc'd space */
4791 int pcbr_offset;
4792
4793 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4794 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4795 pcbr_offset,
Daniel Vetter190d6cd2013-07-04 13:06:28 +02004796 I915_GTT_OFFSET_NONE,
Jesse Barnesc9cddff2013-05-08 10:45:13 -07004797 pctx_size);
4798 goto out;
4799 }
4800
Ville Syrjäläce611ef2014-11-07 21:33:46 +02004801 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4802
Jesse Barnesc9cddff2013-05-08 10:45:13 -07004803 /*
4804 * From the Gunit register HAS:
4805 * The Gfx driver is expected to program this register and ensure
4806 * proper allocation within Gfx stolen memory. For example, this
4807 * register should be programmed such than the PCBR range does not
4808 * overlap with other ranges, such as the frame buffer, protected
4809 * memory, or any other relevant ranges.
4810 */
4811 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4812 if (!pctx) {
4813 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4814 return;
4815 }
4816
4817 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4818 I915_WRITE(VLV_PCBR, pctx_paddr);
4819
4820out:
Ville Syrjäläce611ef2014-11-07 21:33:46 +02004821 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
Jesse Barnesc9cddff2013-05-08 10:45:13 -07004822 dev_priv->vlv_pctx = pctx;
4823}
4824
Imre Deakae484342014-03-31 15:10:44 +03004825static void valleyview_cleanup_pctx(struct drm_device *dev)
4826{
4827 struct drm_i915_private *dev_priv = dev->dev_private;
4828
4829 if (WARN_ON(!dev_priv->vlv_pctx))
4830 return;
4831
4832 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4833 dev_priv->vlv_pctx = NULL;
4834}
4835
Imre Deak4e805192014-04-14 20:24:41 +03004836static void valleyview_init_gt_powersave(struct drm_device *dev)
4837{
4838 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03004839 u32 val;
Imre Deak4e805192014-04-14 20:24:41 +03004840
4841 valleyview_setup_pctx(dev);
4842
4843 mutex_lock(&dev_priv->rps.hw_lock);
4844
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03004845 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4846 switch ((val >> 6) & 3) {
4847 case 0:
4848 case 1:
4849 dev_priv->mem_freq = 800;
4850 break;
4851 case 2:
4852 dev_priv->mem_freq = 1066;
4853 break;
4854 case 3:
4855 dev_priv->mem_freq = 1333;
4856 break;
4857 }
Ville Syrjälä80b83b62014-11-10 22:55:14 +02004858 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03004859
Imre Deak4e805192014-04-14 20:24:41 +03004860 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4861 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4862 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02004863 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
Imre Deak4e805192014-04-14 20:24:41 +03004864 dev_priv->rps.max_freq);
4865
4866 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4867 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02004868 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
Imre Deak4e805192014-04-14 20:24:41 +03004869 dev_priv->rps.efficient_freq);
4870
Deepak Sf8f2b002014-07-10 13:16:21 +05304871 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4872 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02004873 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
Deepak Sf8f2b002014-07-10 13:16:21 +05304874 dev_priv->rps.rp1_freq);
4875
Imre Deak4e805192014-04-14 20:24:41 +03004876 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4877 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02004878 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
Imre Deak4e805192014-04-14 20:24:41 +03004879 dev_priv->rps.min_freq);
4880
Chris Wilsonaed242f2015-03-18 09:48:21 +00004881 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4882
Imre Deak4e805192014-04-14 20:24:41 +03004883 /* Preserve min/max settings in case of re-init */
4884 if (dev_priv->rps.max_freq_softlimit == 0)
4885 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4886
4887 if (dev_priv->rps.min_freq_softlimit == 0)
4888 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4889
4890 mutex_unlock(&dev_priv->rps.hw_lock);
4891}
4892
Deepak S38807742014-05-23 21:00:15 +05304893static void cherryview_init_gt_powersave(struct drm_device *dev)
4894{
Deepak S2b6b3a02014-05-27 15:59:30 +05304895 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03004896 u32 val;
Deepak S2b6b3a02014-05-27 15:59:30 +05304897
Deepak S38807742014-05-23 21:00:15 +05304898 cherryview_setup_pctx(dev);
Deepak S2b6b3a02014-05-27 15:59:30 +05304899
4900 mutex_lock(&dev_priv->rps.hw_lock);
4901
Ville Syrjäläc6e8f392014-11-07 21:33:43 +02004902 mutex_lock(&dev_priv->dpio_lock);
4903 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
4904 mutex_unlock(&dev_priv->dpio_lock);
4905
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03004906 switch ((val >> 2) & 0x7) {
4907 case 0:
4908 case 1:
4909 dev_priv->rps.cz_freq = 200;
4910 dev_priv->mem_freq = 1600;
4911 break;
4912 case 2:
4913 dev_priv->rps.cz_freq = 267;
4914 dev_priv->mem_freq = 1600;
4915 break;
4916 case 3:
4917 dev_priv->rps.cz_freq = 333;
4918 dev_priv->mem_freq = 2000;
4919 break;
4920 case 4:
4921 dev_priv->rps.cz_freq = 320;
4922 dev_priv->mem_freq = 1600;
4923 break;
4924 case 5:
4925 dev_priv->rps.cz_freq = 400;
4926 dev_priv->mem_freq = 1600;
4927 break;
4928 }
Ville Syrjälä80b83b62014-11-10 22:55:14 +02004929 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03004930
Deepak S2b6b3a02014-05-27 15:59:30 +05304931 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4932 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4933 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02004934 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
Deepak S2b6b3a02014-05-27 15:59:30 +05304935 dev_priv->rps.max_freq);
4936
4937 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4938 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02004939 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
Deepak S2b6b3a02014-05-27 15:59:30 +05304940 dev_priv->rps.efficient_freq);
4941
Deepak S7707df42014-07-12 18:46:14 +05304942 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4943 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02004944 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
Deepak S7707df42014-07-12 18:46:14 +05304945 dev_priv->rps.rp1_freq);
4946
Deepak S2b6b3a02014-05-27 15:59:30 +05304947 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4948 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02004949 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
Deepak S2b6b3a02014-05-27 15:59:30 +05304950 dev_priv->rps.min_freq);
4951
Ville Syrjälä1c147622014-08-18 14:42:43 +03004952 WARN_ONCE((dev_priv->rps.max_freq |
4953 dev_priv->rps.efficient_freq |
4954 dev_priv->rps.rp1_freq |
4955 dev_priv->rps.min_freq) & 1,
4956 "Odd GPU freq values\n");
4957
Chris Wilsonaed242f2015-03-18 09:48:21 +00004958 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4959
Deepak S2b6b3a02014-05-27 15:59:30 +05304960 /* Preserve min/max settings in case of re-init */
4961 if (dev_priv->rps.max_freq_softlimit == 0)
4962 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4963
4964 if (dev_priv->rps.min_freq_softlimit == 0)
4965 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4966
4967 mutex_unlock(&dev_priv->rps.hw_lock);
Deepak S38807742014-05-23 21:00:15 +05304968}
4969
Imre Deak4e805192014-04-14 20:24:41 +03004970static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4971{
4972 valleyview_cleanup_pctx(dev);
4973}
4974
Deepak S38807742014-05-23 21:00:15 +05304975static void cherryview_enable_rps(struct drm_device *dev)
4976{
4977 struct drm_i915_private *dev_priv = dev->dev_private;
4978 struct intel_engine_cs *ring;
Deepak S2b6b3a02014-05-27 15:59:30 +05304979 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
Deepak S38807742014-05-23 21:00:15 +05304980 int i;
4981
4982 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4983
4984 gtfifodbg = I915_READ(GTFIFODBG);
4985 if (gtfifodbg) {
4986 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4987 gtfifodbg);
4988 I915_WRITE(GTFIFODBG, gtfifodbg);
4989 }
4990
4991 cherryview_check_pctx(dev_priv);
4992
4993 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4994 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
Mika Kuoppala59bad942015-01-16 11:34:40 +02004995 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Deepak S38807742014-05-23 21:00:15 +05304996
Ville Syrjälä160614a2015-01-19 13:50:47 +02004997 /* Disable RC states. */
4998 I915_WRITE(GEN6_RC_CONTROL, 0);
4999
Deepak S38807742014-05-23 21:00:15 +05305000 /* 2a: Program RC6 thresholds.*/
5001 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5002 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5003 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5004
5005 for_each_ring(ring, dev_priv, i)
5006 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5007 I915_WRITE(GEN6_RC_SLEEP, 0);
5008
Ville Syrjäläaf5a75a2015-01-19 13:50:50 +02005009 /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
5010 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
Deepak S38807742014-05-23 21:00:15 +05305011
5012 /* allows RC6 residency counter to work */
5013 I915_WRITE(VLV_COUNTER_CONTROL,
5014 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5015 VLV_MEDIA_RC6_COUNT_EN |
5016 VLV_RENDER_RC6_COUNT_EN));
5017
5018 /* For now we assume BIOS is allocating and populating the PCBR */
5019 pcbr = I915_READ(VLV_PCBR);
5020
Deepak S38807742014-05-23 21:00:15 +05305021 /* 3: Enable RC6 */
5022 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5023 (pcbr >> VLV_PCBR_ADDR_SHIFT))
Ville Syrjäläaf5a75a2015-01-19 13:50:50 +02005024 rc6_mode = GEN7_RC_CTL_TO_MODE;
Deepak S38807742014-05-23 21:00:15 +05305025
5026 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5027
Deepak S2b6b3a02014-05-27 15:59:30 +05305028 /* 4 Program defaults and thresholds for RPS*/
Ville Syrjälä3cbdb482015-01-19 13:50:49 +02005029 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
Deepak S2b6b3a02014-05-27 15:59:30 +05305030 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5031 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5032 I915_WRITE(GEN6_RP_UP_EI, 66000);
5033 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5034
5035 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5036
5037 /* 5: Enable RPS */
5038 I915_WRITE(GEN6_RP_CONTROL,
5039 GEN6_RP_MEDIA_HW_NORMAL_MODE |
Ville Syrjäläeb973a52015-01-21 19:37:59 +02005040 GEN6_RP_MEDIA_IS_GFX |
Deepak S2b6b3a02014-05-27 15:59:30 +05305041 GEN6_RP_ENABLE |
5042 GEN6_RP_UP_BUSY_AVG |
5043 GEN6_RP_DOWN_IDLE_AVG);
5044
5045 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5046
Ville Syrjälä8d40c3a2014-11-07 21:33:45 +02005047 /* RPS code assumes GPLL is used */
5048 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5049
Ville Syrjäläc8e96272014-11-07 21:33:44 +02005050 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
Deepak S2b6b3a02014-05-27 15:59:30 +05305051 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5052
5053 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5054 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02005055 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
Deepak S2b6b3a02014-05-27 15:59:30 +05305056 dev_priv->rps.cur_freq);
5057
5058 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02005059 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
Deepak S2b6b3a02014-05-27 15:59:30 +05305060 dev_priv->rps.efficient_freq);
5061
5062 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5063
Mika Kuoppala59bad942015-01-16 11:34:40 +02005064 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Deepak S38807742014-05-23 21:00:15 +05305065}
5066
Jesse Barnes0a073b82013-04-17 15:54:58 -07005067static void valleyview_enable_rps(struct drm_device *dev)
5068{
5069 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01005070 struct intel_engine_cs *ring;
Ben Widawsky2a5913a2014-03-19 18:31:13 -07005071 u32 gtfifodbg, val, rc6_mode = 0;
Jesse Barnes0a073b82013-04-17 15:54:58 -07005072 int i;
5073
5074 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5075
Imre Deakae484342014-03-31 15:10:44 +03005076 valleyview_check_pctx(dev_priv);
5077
Jesse Barnes0a073b82013-04-17 15:54:58 -07005078 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
Jesse Barnesf7d85c12013-09-27 10:40:54 -07005079 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5080 gtfifodbg);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005081 I915_WRITE(GTFIFODBG, gtfifodbg);
5082 }
5083
Deepak Sc8d9a592013-11-23 14:55:42 +05305084 /* If VLV, Forcewake all wells, else re-direct to regular path */
Mika Kuoppala59bad942015-01-16 11:34:40 +02005085 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005086
Ville Syrjälä160614a2015-01-19 13:50:47 +02005087 /* Disable RC states. */
5088 I915_WRITE(GEN6_RC_CONTROL, 0);
5089
Ville Syrjäläcad725f2015-01-19 13:50:48 +02005090 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005091 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5092 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5093 I915_WRITE(GEN6_RP_UP_EI, 66000);
5094 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5095
5096 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5097
5098 I915_WRITE(GEN6_RP_CONTROL,
5099 GEN6_RP_MEDIA_TURBO |
5100 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5101 GEN6_RP_MEDIA_IS_GFX |
5102 GEN6_RP_ENABLE |
5103 GEN6_RP_UP_BUSY_AVG |
5104 GEN6_RP_DOWN_IDLE_CONT);
5105
5106 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5107 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5108 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5109
5110 for_each_ring(ring, dev_priv, i)
5111 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5112
Jesse Barnes2f0aa302013-11-15 09:32:11 -08005113 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005114
5115 /* allows RC6 residency counter to work */
Jesse Barnes49798eb2013-09-26 17:55:57 -07005116 I915_WRITE(VLV_COUNTER_CONTROL,
Deepak S31685c22014-07-03 17:33:01 -04005117 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5118 VLV_RENDER_RC0_COUNT_EN |
Jesse Barnes49798eb2013-09-26 17:55:57 -07005119 VLV_MEDIA_RC6_COUNT_EN |
5120 VLV_RENDER_RC6_COUNT_EN));
Deepak S31685c22014-07-03 17:33:01 -04005121
Jesse Barnesa2b23fe2013-09-19 09:33:13 -07005122 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
Jesse Barnes6b88f292013-11-15 09:32:12 -08005123 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
Ben Widawskydc39fff2013-10-18 12:32:07 -07005124
5125 intel_print_rc6_info(dev, rc6_mode);
5126
Jesse Barnesa2b23fe2013-09-19 09:33:13 -07005127 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005128
Jani Nikula64936252013-05-22 15:36:20 +03005129 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005130
Ville Syrjälä8d40c3a2014-11-07 21:33:45 +02005131 /* RPS code assumes GPLL is used */
5132 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5133
Ville Syrjäläc8e96272014-11-07 21:33:44 +02005134 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
Jesse Barnes0a073b82013-04-17 15:54:58 -07005135 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5136
Ben Widawskyb39fb292014-03-19 18:31:11 -07005137 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
Ville Syrjälä73008b92013-06-25 19:21:01 +03005138 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02005139 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
Ben Widawskyb39fb292014-03-19 18:31:11 -07005140 dev_priv->rps.cur_freq);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005141
Ville Syrjälä73008b92013-06-25 19:21:01 +03005142 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02005143 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
Ben Widawskyb39fb292014-03-19 18:31:11 -07005144 dev_priv->rps.efficient_freq);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005145
Ben Widawskyb39fb292014-03-19 18:31:11 -07005146 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005147
Mika Kuoppala59bad942015-01-16 11:34:40 +02005148 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005149}
5150
Eugeni Dodonovdde18882012-04-18 15:29:24 -03005151static unsigned long intel_pxfreq(u32 vidfreq)
5152{
5153 unsigned long freq;
5154 int div = (vidfreq & 0x3f0000) >> 16;
5155 int post = (vidfreq & 0x3000) >> 12;
5156 int pre = (vidfreq & 0x7);
5157
5158 if (!pre)
5159 return 0;
5160
5161 freq = ((div * 133333) / ((1<<post) * pre));
5162
5163 return freq;
5164}
5165
Daniel Vettereb48eb02012-04-26 23:28:12 +02005166static const struct cparams {
5167 u16 i;
5168 u16 t;
5169 u16 m;
5170 u16 c;
5171} cparams[] = {
5172 { 1, 1333, 301, 28664 },
5173 { 1, 1066, 294, 24460 },
5174 { 1, 800, 294, 25192 },
5175 { 0, 1333, 276, 27605 },
5176 { 0, 1066, 276, 27605 },
5177 { 0, 800, 231, 23784 },
5178};
5179
Chris Wilsonf531dcb2012-09-25 10:16:12 +01005180static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
Daniel Vettereb48eb02012-04-26 23:28:12 +02005181{
5182 u64 total_count, diff, ret;
5183 u32 count1, count2, count3, m = 0, c = 0;
5184 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5185 int i;
5186
Daniel Vetter02d71952012-08-09 16:44:54 +02005187 assert_spin_locked(&mchdev_lock);
5188
Daniel Vetter20e4d402012-08-08 23:35:39 +02005189 diff1 = now - dev_priv->ips.last_time1;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005190
5191 /* Prevent division-by-zero if we are asking too fast.
5192 * Also, we don't get interesting results if we are polling
5193 * faster than once in 10ms, so just return the saved value
5194 * in such cases.
5195 */
5196 if (diff1 <= 10)
Daniel Vetter20e4d402012-08-08 23:35:39 +02005197 return dev_priv->ips.chipset_power;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005198
5199 count1 = I915_READ(DMIEC);
5200 count2 = I915_READ(DDREC);
5201 count3 = I915_READ(CSIEC);
5202
5203 total_count = count1 + count2 + count3;
5204
5205 /* FIXME: handle per-counter overflow */
Daniel Vetter20e4d402012-08-08 23:35:39 +02005206 if (total_count < dev_priv->ips.last_count1) {
5207 diff = ~0UL - dev_priv->ips.last_count1;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005208 diff += total_count;
5209 } else {
Daniel Vetter20e4d402012-08-08 23:35:39 +02005210 diff = total_count - dev_priv->ips.last_count1;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005211 }
5212
5213 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
Daniel Vetter20e4d402012-08-08 23:35:39 +02005214 if (cparams[i].i == dev_priv->ips.c_m &&
5215 cparams[i].t == dev_priv->ips.r_t) {
Daniel Vettereb48eb02012-04-26 23:28:12 +02005216 m = cparams[i].m;
5217 c = cparams[i].c;
5218 break;
5219 }
5220 }
5221
5222 diff = div_u64(diff, diff1);
5223 ret = ((m * diff) + c);
5224 ret = div_u64(ret, 10);
5225
Daniel Vetter20e4d402012-08-08 23:35:39 +02005226 dev_priv->ips.last_count1 = total_count;
5227 dev_priv->ips.last_time1 = now;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005228
Daniel Vetter20e4d402012-08-08 23:35:39 +02005229 dev_priv->ips.chipset_power = ret;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005230
5231 return ret;
5232}
5233
Chris Wilsonf531dcb2012-09-25 10:16:12 +01005234unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5235{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00005236 struct drm_device *dev = dev_priv->dev;
Chris Wilsonf531dcb2012-09-25 10:16:12 +01005237 unsigned long val;
5238
Damien Lespiau3d13ef22014-02-07 19:12:47 +00005239 if (INTEL_INFO(dev)->gen != 5)
Chris Wilsonf531dcb2012-09-25 10:16:12 +01005240 return 0;
5241
5242 spin_lock_irq(&mchdev_lock);
5243
5244 val = __i915_chipset_val(dev_priv);
5245
5246 spin_unlock_irq(&mchdev_lock);
5247
5248 return val;
5249}
5250
Daniel Vettereb48eb02012-04-26 23:28:12 +02005251unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5252{
5253 unsigned long m, x, b;
5254 u32 tsfs;
5255
5256 tsfs = I915_READ(TSFS);
5257
5258 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5259 x = I915_READ8(TR1);
5260
5261 b = tsfs & TSFS_INTR_MASK;
5262
5263 return ((m * x) / 127) - b;
5264}
5265
Mika Kuoppalad972d6e2014-12-01 18:01:05 +02005266static int _pxvid_to_vd(u8 pxvid)
5267{
5268 if (pxvid == 0)
5269 return 0;
5270
5271 if (pxvid >= 8 && pxvid < 31)
5272 pxvid = 31;
5273
5274 return (pxvid + 2) * 125;
5275}
5276
5277static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
Daniel Vettereb48eb02012-04-26 23:28:12 +02005278{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00005279 struct drm_device *dev = dev_priv->dev;
Mika Kuoppalad972d6e2014-12-01 18:01:05 +02005280 const int vd = _pxvid_to_vd(pxvid);
5281 const int vm = vd - 1125;
5282
Damien Lespiau3d13ef22014-02-07 19:12:47 +00005283 if (INTEL_INFO(dev)->is_mobile)
Mika Kuoppalad972d6e2014-12-01 18:01:05 +02005284 return vm > 0 ? vm : 0;
5285
5286 return vd;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005287}
5288
Daniel Vetter02d71952012-08-09 16:44:54 +02005289static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
Daniel Vettereb48eb02012-04-26 23:28:12 +02005290{
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00005291 u64 now, diff, diffms;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005292 u32 count;
5293
Daniel Vetter02d71952012-08-09 16:44:54 +02005294 assert_spin_locked(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005295
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00005296 now = ktime_get_raw_ns();
5297 diffms = now - dev_priv->ips.last_time2;
5298 do_div(diffms, NSEC_PER_MSEC);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005299
5300 /* Don't divide by 0 */
Daniel Vettereb48eb02012-04-26 23:28:12 +02005301 if (!diffms)
5302 return;
5303
5304 count = I915_READ(GFXEC);
5305
Daniel Vetter20e4d402012-08-08 23:35:39 +02005306 if (count < dev_priv->ips.last_count2) {
5307 diff = ~0UL - dev_priv->ips.last_count2;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005308 diff += count;
5309 } else {
Daniel Vetter20e4d402012-08-08 23:35:39 +02005310 diff = count - dev_priv->ips.last_count2;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005311 }
5312
Daniel Vetter20e4d402012-08-08 23:35:39 +02005313 dev_priv->ips.last_count2 = count;
5314 dev_priv->ips.last_time2 = now;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005315
5316 /* More magic constants... */
5317 diff = diff * 1181;
5318 diff = div_u64(diff, diffms * 10);
Daniel Vetter20e4d402012-08-08 23:35:39 +02005319 dev_priv->ips.gfx_power = diff;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005320}
5321
Daniel Vetter02d71952012-08-09 16:44:54 +02005322void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5323{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00005324 struct drm_device *dev = dev_priv->dev;
5325
5326 if (INTEL_INFO(dev)->gen != 5)
Daniel Vetter02d71952012-08-09 16:44:54 +02005327 return;
5328
Daniel Vetter92703882012-08-09 16:46:01 +02005329 spin_lock_irq(&mchdev_lock);
Daniel Vetter02d71952012-08-09 16:44:54 +02005330
5331 __i915_update_gfx_val(dev_priv);
5332
Daniel Vetter92703882012-08-09 16:46:01 +02005333 spin_unlock_irq(&mchdev_lock);
Daniel Vetter02d71952012-08-09 16:44:54 +02005334}
5335
Chris Wilsonf531dcb2012-09-25 10:16:12 +01005336static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
Daniel Vettereb48eb02012-04-26 23:28:12 +02005337{
5338 unsigned long t, corr, state1, corr2, state2;
5339 u32 pxvid, ext_v;
5340
Daniel Vetter02d71952012-08-09 16:44:54 +02005341 assert_spin_locked(&mchdev_lock);
5342
Ben Widawskyb39fb292014-03-19 18:31:11 -07005343 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
Daniel Vettereb48eb02012-04-26 23:28:12 +02005344 pxvid = (pxvid >> 24) & 0x7f;
5345 ext_v = pvid_to_extvid(dev_priv, pxvid);
5346
5347 state1 = ext_v;
5348
5349 t = i915_mch_val(dev_priv);
5350
5351 /* Revel in the empirically derived constants */
5352
5353 /* Correction factor in 1/100000 units */
5354 if (t > 80)
5355 corr = ((t * 2349) + 135940);
5356 else if (t >= 50)
5357 corr = ((t * 964) + 29317);
5358 else /* < 50 */
5359 corr = ((t * 301) + 1004);
5360
5361 corr = corr * ((150142 * state1) / 10000 - 78642);
5362 corr /= 100000;
Daniel Vetter20e4d402012-08-08 23:35:39 +02005363 corr2 = (corr * dev_priv->ips.corr);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005364
5365 state2 = (corr2 * state1) / 10000;
5366 state2 /= 100; /* convert to mW */
5367
Daniel Vetter02d71952012-08-09 16:44:54 +02005368 __i915_update_gfx_val(dev_priv);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005369
Daniel Vetter20e4d402012-08-08 23:35:39 +02005370 return dev_priv->ips.gfx_power + state2;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005371}
5372
Chris Wilsonf531dcb2012-09-25 10:16:12 +01005373unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5374{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00005375 struct drm_device *dev = dev_priv->dev;
Chris Wilsonf531dcb2012-09-25 10:16:12 +01005376 unsigned long val;
5377
Damien Lespiau3d13ef22014-02-07 19:12:47 +00005378 if (INTEL_INFO(dev)->gen != 5)
Chris Wilsonf531dcb2012-09-25 10:16:12 +01005379 return 0;
5380
5381 spin_lock_irq(&mchdev_lock);
5382
5383 val = __i915_gfx_val(dev_priv);
5384
5385 spin_unlock_irq(&mchdev_lock);
5386
5387 return val;
5388}
5389
Daniel Vettereb48eb02012-04-26 23:28:12 +02005390/**
5391 * i915_read_mch_val - return value for IPS use
5392 *
5393 * Calculate and return a value for the IPS driver to use when deciding whether
5394 * we have thermal and power headroom to increase CPU or GPU power budget.
5395 */
5396unsigned long i915_read_mch_val(void)
5397{
5398 struct drm_i915_private *dev_priv;
5399 unsigned long chipset_val, graphics_val, ret = 0;
5400
Daniel Vetter92703882012-08-09 16:46:01 +02005401 spin_lock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005402 if (!i915_mch_dev)
5403 goto out_unlock;
5404 dev_priv = i915_mch_dev;
5405
Chris Wilsonf531dcb2012-09-25 10:16:12 +01005406 chipset_val = __i915_chipset_val(dev_priv);
5407 graphics_val = __i915_gfx_val(dev_priv);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005408
5409 ret = chipset_val + graphics_val;
5410
5411out_unlock:
Daniel Vetter92703882012-08-09 16:46:01 +02005412 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005413
5414 return ret;
5415}
5416EXPORT_SYMBOL_GPL(i915_read_mch_val);
5417
5418/**
5419 * i915_gpu_raise - raise GPU frequency limit
5420 *
5421 * Raise the limit; IPS indicates we have thermal headroom.
5422 */
5423bool i915_gpu_raise(void)
5424{
5425 struct drm_i915_private *dev_priv;
5426 bool ret = true;
5427
Daniel Vetter92703882012-08-09 16:46:01 +02005428 spin_lock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005429 if (!i915_mch_dev) {
5430 ret = false;
5431 goto out_unlock;
5432 }
5433 dev_priv = i915_mch_dev;
5434
Daniel Vetter20e4d402012-08-08 23:35:39 +02005435 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5436 dev_priv->ips.max_delay--;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005437
5438out_unlock:
Daniel Vetter92703882012-08-09 16:46:01 +02005439 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005440
5441 return ret;
5442}
5443EXPORT_SYMBOL_GPL(i915_gpu_raise);
5444
5445/**
5446 * i915_gpu_lower - lower GPU frequency limit
5447 *
5448 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5449 * frequency maximum.
5450 */
5451bool i915_gpu_lower(void)
5452{
5453 struct drm_i915_private *dev_priv;
5454 bool ret = true;
5455
Daniel Vetter92703882012-08-09 16:46:01 +02005456 spin_lock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005457 if (!i915_mch_dev) {
5458 ret = false;
5459 goto out_unlock;
5460 }
5461 dev_priv = i915_mch_dev;
5462
Daniel Vetter20e4d402012-08-08 23:35:39 +02005463 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5464 dev_priv->ips.max_delay++;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005465
5466out_unlock:
Daniel Vetter92703882012-08-09 16:46:01 +02005467 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005468
5469 return ret;
5470}
5471EXPORT_SYMBOL_GPL(i915_gpu_lower);
5472
5473/**
5474 * i915_gpu_busy - indicate GPU business to IPS
5475 *
5476 * Tell the IPS driver whether or not the GPU is busy.
5477 */
5478bool i915_gpu_busy(void)
5479{
5480 struct drm_i915_private *dev_priv;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01005481 struct intel_engine_cs *ring;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005482 bool ret = false;
Chris Wilsonf047e392012-07-21 12:31:41 +01005483 int i;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005484
Daniel Vetter92703882012-08-09 16:46:01 +02005485 spin_lock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005486 if (!i915_mch_dev)
5487 goto out_unlock;
5488 dev_priv = i915_mch_dev;
5489
Chris Wilsonf047e392012-07-21 12:31:41 +01005490 for_each_ring(ring, dev_priv, i)
5491 ret |= !list_empty(&ring->request_list);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005492
5493out_unlock:
Daniel Vetter92703882012-08-09 16:46:01 +02005494 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005495
5496 return ret;
5497}
5498EXPORT_SYMBOL_GPL(i915_gpu_busy);
5499
5500/**
5501 * i915_gpu_turbo_disable - disable graphics turbo
5502 *
5503 * Disable graphics turbo by resetting the max frequency and setting the
5504 * current frequency to the default.
5505 */
5506bool i915_gpu_turbo_disable(void)
5507{
5508 struct drm_i915_private *dev_priv;
5509 bool ret = true;
5510
Daniel Vetter92703882012-08-09 16:46:01 +02005511 spin_lock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005512 if (!i915_mch_dev) {
5513 ret = false;
5514 goto out_unlock;
5515 }
5516 dev_priv = i915_mch_dev;
5517
Daniel Vetter20e4d402012-08-08 23:35:39 +02005518 dev_priv->ips.max_delay = dev_priv->ips.fstart;
Daniel Vettereb48eb02012-04-26 23:28:12 +02005519
Daniel Vetter20e4d402012-08-08 23:35:39 +02005520 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
Daniel Vettereb48eb02012-04-26 23:28:12 +02005521 ret = false;
5522
5523out_unlock:
Daniel Vetter92703882012-08-09 16:46:01 +02005524 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005525
5526 return ret;
5527}
5528EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5529
5530/**
5531 * Tells the intel_ips driver that the i915 driver is now loaded, if
5532 * IPS got loaded first.
5533 *
5534 * This awkward dance is so that neither module has to depend on the
5535 * other in order for IPS to do the appropriate communication of
5536 * GPU turbo limits to i915.
5537 */
5538static void
5539ips_ping_for_i915_load(void)
5540{
5541 void (*link)(void);
5542
5543 link = symbol_get(ips_link_to_i915_driver);
5544 if (link) {
5545 link();
5546 symbol_put(ips_link_to_i915_driver);
5547 }
5548}
5549
5550void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5551{
Daniel Vetter02d71952012-08-09 16:44:54 +02005552 /* We only register the i915 ips part with intel-ips once everything is
5553 * set up, to avoid intel-ips sneaking in and reading bogus values. */
Daniel Vetter92703882012-08-09 16:46:01 +02005554 spin_lock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005555 i915_mch_dev = dev_priv;
Daniel Vetter92703882012-08-09 16:46:01 +02005556 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005557
5558 ips_ping_for_i915_load();
5559}
5560
5561void intel_gpu_ips_teardown(void)
5562{
Daniel Vetter92703882012-08-09 16:46:01 +02005563 spin_lock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005564 i915_mch_dev = NULL;
Daniel Vetter92703882012-08-09 16:46:01 +02005565 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02005566}
Deepak S76c3552f2014-01-30 23:08:16 +05305567
Daniel Vetter8090c6b2012-06-24 16:42:32 +02005568static void intel_init_emon(struct drm_device *dev)
Eugeni Dodonovdde18882012-04-18 15:29:24 -03005569{
5570 struct drm_i915_private *dev_priv = dev->dev_private;
5571 u32 lcfuse;
5572 u8 pxw[16];
5573 int i;
5574
5575 /* Disable to program */
5576 I915_WRITE(ECR, 0);
5577 POSTING_READ(ECR);
5578
5579 /* Program energy weights for various events */
5580 I915_WRITE(SDEW, 0x15040d00);
5581 I915_WRITE(CSIEW0, 0x007f0000);
5582 I915_WRITE(CSIEW1, 0x1e220004);
5583 I915_WRITE(CSIEW2, 0x04000004);
5584
5585 for (i = 0; i < 5; i++)
5586 I915_WRITE(PEW + (i * 4), 0);
5587 for (i = 0; i < 3; i++)
5588 I915_WRITE(DEW + (i * 4), 0);
5589
5590 /* Program P-state weights to account for frequency power adjustment */
5591 for (i = 0; i < 16; i++) {
5592 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5593 unsigned long freq = intel_pxfreq(pxvidfreq);
5594 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5595 PXVFREQ_PX_SHIFT;
5596 unsigned long val;
5597
5598 val = vid * vid;
5599 val *= (freq / 1000);
5600 val *= 255;
5601 val /= (127*127*900);
5602 if (val > 0xff)
5603 DRM_ERROR("bad pxval: %ld\n", val);
5604 pxw[i] = val;
5605 }
5606 /* Render standby states get 0 weight */
5607 pxw[14] = 0;
5608 pxw[15] = 0;
5609
5610 for (i = 0; i < 4; i++) {
5611 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5612 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5613 I915_WRITE(PXW + (i * 4), val);
5614 }
5615
5616 /* Adjust magic regs to magic values (more experimental results) */
5617 I915_WRITE(OGW0, 0);
5618 I915_WRITE(OGW1, 0);
5619 I915_WRITE(EG0, 0x00007f00);
5620 I915_WRITE(EG1, 0x0000000e);
5621 I915_WRITE(EG2, 0x000e0000);
5622 I915_WRITE(EG3, 0x68000300);
5623 I915_WRITE(EG4, 0x42000000);
5624 I915_WRITE(EG5, 0x00140031);
5625 I915_WRITE(EG6, 0);
5626 I915_WRITE(EG7, 0);
5627
5628 for (i = 0; i < 8; i++)
5629 I915_WRITE(PXWL + (i * 4), 0);
5630
5631 /* Enable PMON + select events */
5632 I915_WRITE(ECR, 0x80000019);
5633
5634 lcfuse = I915_READ(LCFUSE02);
5635
Daniel Vetter20e4d402012-08-08 23:35:39 +02005636 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
Eugeni Dodonovdde18882012-04-18 15:29:24 -03005637}
5638
Imre Deakae484342014-03-31 15:10:44 +03005639void intel_init_gt_powersave(struct drm_device *dev)
5640{
Imre Deake6069ca2014-04-18 16:01:02 +03005641 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5642
Deepak S38807742014-05-23 21:00:15 +05305643 if (IS_CHERRYVIEW(dev))
5644 cherryview_init_gt_powersave(dev);
5645 else if (IS_VALLEYVIEW(dev))
Imre Deak4e805192014-04-14 20:24:41 +03005646 valleyview_init_gt_powersave(dev);
Imre Deakae484342014-03-31 15:10:44 +03005647}
5648
5649void intel_cleanup_gt_powersave(struct drm_device *dev)
5650{
Deepak S38807742014-05-23 21:00:15 +05305651 if (IS_CHERRYVIEW(dev))
5652 return;
5653 else if (IS_VALLEYVIEW(dev))
Imre Deak4e805192014-04-14 20:24:41 +03005654 valleyview_cleanup_gt_powersave(dev);
Imre Deakae484342014-03-31 15:10:44 +03005655}
5656
Imre Deakdbea3ce2014-12-15 18:59:28 +02005657static void gen6_suspend_rps(struct drm_device *dev)
5658{
5659 struct drm_i915_private *dev_priv = dev->dev_private;
5660
5661 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5662
Akash Goel4c2a8892015-03-06 11:07:24 +05305663 gen6_disable_rps_interrupts(dev);
Imre Deakdbea3ce2014-12-15 18:59:28 +02005664}
5665
Jesse Barnes156c7ca2014-06-12 08:35:45 -07005666/**
5667 * intel_suspend_gt_powersave - suspend PM work and helper threads
5668 * @dev: drm device
5669 *
5670 * We don't want to disable RC6 or other features here, we just want
5671 * to make sure any work we've queued has finished and won't bother
5672 * us while we're suspended.
5673 */
5674void intel_suspend_gt_powersave(struct drm_device *dev)
5675{
5676 struct drm_i915_private *dev_priv = dev->dev_private;
5677
Imre Deakd4d70aa2014-11-19 15:30:04 +02005678 if (INTEL_INFO(dev)->gen < 6)
5679 return;
5680
Imre Deakdbea3ce2014-12-15 18:59:28 +02005681 gen6_suspend_rps(dev);
Deepak Sb47adc12014-06-20 20:03:02 +05305682
5683 /* Force GPU to min freq during suspend */
5684 gen6_rps_idle(dev_priv);
Jesse Barnes156c7ca2014-06-12 08:35:45 -07005685}
5686
Daniel Vetter8090c6b2012-06-24 16:42:32 +02005687void intel_disable_gt_powersave(struct drm_device *dev)
5688{
Jesse Barnes1a01ab32012-11-02 11:14:00 -07005689 struct drm_i915_private *dev_priv = dev->dev_private;
5690
Daniel Vetter930ebb42012-06-29 23:32:16 +02005691 if (IS_IRONLAKE_M(dev)) {
Daniel Vetter8090c6b2012-06-24 16:42:32 +02005692 ironlake_disable_drps(dev);
Deepak S38807742014-05-23 21:00:15 +05305693 } else if (INTEL_INFO(dev)->gen >= 6) {
Daniel Vetter10d8d362014-06-12 17:48:52 +02005694 intel_suspend_gt_powersave(dev);
Imre Deake4948372014-05-12 18:35:04 +03005695
Jesse Barnes4fc688c2012-11-02 11:14:01 -07005696 mutex_lock(&dev_priv->rps.hw_lock);
Zhe Wang20e49362014-11-04 17:07:05 +00005697 if (INTEL_INFO(dev)->gen >= 9)
5698 gen9_disable_rps(dev);
5699 else if (IS_CHERRYVIEW(dev))
Deepak S38807742014-05-23 21:00:15 +05305700 cherryview_disable_rps(dev);
5701 else if (IS_VALLEYVIEW(dev))
Jesse Barnesd20d4f02013-04-23 10:09:28 -07005702 valleyview_disable_rps(dev);
5703 else
5704 gen6_disable_rps(dev);
Imre Deake5347702014-11-19 15:30:02 +02005705
Chris Wilsonc0951f02013-10-10 21:58:50 +01005706 dev_priv->rps.enabled = false;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07005707 mutex_unlock(&dev_priv->rps.hw_lock);
Daniel Vetter930ebb42012-06-29 23:32:16 +02005708 }
Daniel Vetter8090c6b2012-06-24 16:42:32 +02005709}
5710
Jesse Barnes1a01ab32012-11-02 11:14:00 -07005711static void intel_gen6_powersave_work(struct work_struct *work)
5712{
5713 struct drm_i915_private *dev_priv =
5714 container_of(work, struct drm_i915_private,
5715 rps.delayed_resume_work.work);
5716 struct drm_device *dev = dev_priv->dev;
5717
Jesse Barnes4fc688c2012-11-02 11:14:01 -07005718 mutex_lock(&dev_priv->rps.hw_lock);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005719
Akash Goel4c2a8892015-03-06 11:07:24 +05305720 gen6_reset_rps_interrupts(dev);
Imre Deak3cc134e2014-11-19 15:30:03 +02005721
Deepak S38807742014-05-23 21:00:15 +05305722 if (IS_CHERRYVIEW(dev)) {
5723 cherryview_enable_rps(dev);
5724 } else if (IS_VALLEYVIEW(dev)) {
Jesse Barnes0a073b82013-04-17 15:54:58 -07005725 valleyview_enable_rps(dev);
Zhe Wang20e49362014-11-04 17:07:05 +00005726 } else if (INTEL_INFO(dev)->gen >= 9) {
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00005727 gen9_enable_rc6(dev);
Zhe Wang20e49362014-11-04 17:07:05 +00005728 gen9_enable_rps(dev);
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00005729 __gen6_update_ring_freq(dev);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005730 } else if (IS_BROADWELL(dev)) {
5731 gen8_enable_rps(dev);
Imre Deakc2bc2fc2014-04-18 16:16:23 +03005732 __gen6_update_ring_freq(dev);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005733 } else {
5734 gen6_enable_rps(dev);
Imre Deakc2bc2fc2014-04-18 16:16:23 +03005735 __gen6_update_ring_freq(dev);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005736 }
Chris Wilsonaed242f2015-03-18 09:48:21 +00005737
5738 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
5739 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
5740
5741 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
5742 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
5743
Chris Wilsonc0951f02013-10-10 21:58:50 +01005744 dev_priv->rps.enabled = true;
Imre Deak3cc134e2014-11-19 15:30:03 +02005745
Akash Goel4c2a8892015-03-06 11:07:24 +05305746 gen6_enable_rps_interrupts(dev);
Imre Deak3cc134e2014-11-19 15:30:03 +02005747
Jesse Barnes4fc688c2012-11-02 11:14:01 -07005748 mutex_unlock(&dev_priv->rps.hw_lock);
Imre Deakc6df39b2014-04-14 20:24:29 +03005749
5750 intel_runtime_pm_put(dev_priv);
Jesse Barnes1a01ab32012-11-02 11:14:00 -07005751}
5752
Daniel Vetter8090c6b2012-06-24 16:42:32 +02005753void intel_enable_gt_powersave(struct drm_device *dev)
5754{
Jesse Barnes1a01ab32012-11-02 11:14:00 -07005755 struct drm_i915_private *dev_priv = dev->dev_private;
5756
Yu Zhangf61018b2015-02-10 19:05:52 +08005757 /* Powersaving is controlled by the host when inside a VM */
5758 if (intel_vgpu_active(dev))
5759 return;
5760
Daniel Vetter8090c6b2012-06-24 16:42:32 +02005761 if (IS_IRONLAKE_M(dev)) {
Imre Deakdc1d0132014-04-14 20:24:28 +03005762 mutex_lock(&dev->struct_mutex);
Daniel Vetter8090c6b2012-06-24 16:42:32 +02005763 ironlake_enable_drps(dev);
Daniel Vetter8090c6b2012-06-24 16:42:32 +02005764 intel_init_emon(dev);
Imre Deakdc1d0132014-04-14 20:24:28 +03005765 mutex_unlock(&dev->struct_mutex);
Deepak S38807742014-05-23 21:00:15 +05305766 } else if (INTEL_INFO(dev)->gen >= 6) {
Jesse Barnes1a01ab32012-11-02 11:14:00 -07005767 /*
5768 * PCU communication is slow and this doesn't need to be
5769 * done at any specific time, so do this out of our fast path
5770 * to make resume and init faster.
Imre Deakc6df39b2014-04-14 20:24:29 +03005771 *
5772 * We depend on the HW RC6 power context save/restore
5773 * mechanism when entering D3 through runtime PM suspend. So
5774 * disable RPM until RPS/RC6 is properly setup. We can only
5775 * get here via the driver load/system resume/runtime resume
5776 * paths, so the _noresume version is enough (and in case of
5777 * runtime resume it's necessary).
Jesse Barnes1a01ab32012-11-02 11:14:00 -07005778 */
Imre Deakc6df39b2014-04-14 20:24:29 +03005779 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5780 round_jiffies_up_relative(HZ)))
5781 intel_runtime_pm_get_noresume(dev_priv);
Daniel Vetter8090c6b2012-06-24 16:42:32 +02005782 }
5783}
5784
Imre Deakc6df39b2014-04-14 20:24:29 +03005785void intel_reset_gt_powersave(struct drm_device *dev)
5786{
5787 struct drm_i915_private *dev_priv = dev->dev_private;
5788
Imre Deakdbea3ce2014-12-15 18:59:28 +02005789 if (INTEL_INFO(dev)->gen < 6)
5790 return;
5791
5792 gen6_suspend_rps(dev);
Imre Deakc6df39b2014-04-14 20:24:29 +03005793 dev_priv->rps.enabled = false;
Imre Deakc6df39b2014-04-14 20:24:29 +03005794}
5795
Daniel Vetter3107bd42012-10-31 22:52:31 +01005796static void ibx_init_clock_gating(struct drm_device *dev)
5797{
5798 struct drm_i915_private *dev_priv = dev->dev_private;
5799
5800 /*
5801 * On Ibex Peak and Cougar Point, we need to disable clock
5802 * gating for the panel power sequencer or it will fail to
5803 * start up when no ports are active.
5804 */
5805 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5806}
5807
Ville Syrjälä0e088b82013-06-07 10:47:04 +03005808static void g4x_disable_trickle_feed(struct drm_device *dev)
5809{
5810 struct drm_i915_private *dev_priv = dev->dev_private;
5811 int pipe;
5812
Damien Lespiau055e3932014-08-18 13:49:10 +01005813 for_each_pipe(dev_priv, pipe) {
Ville Syrjälä0e088b82013-06-07 10:47:04 +03005814 I915_WRITE(DSPCNTR(pipe),
5815 I915_READ(DSPCNTR(pipe)) |
5816 DISPPLANE_TRICKLE_FEED_DISABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03005817 intel_flush_primary_plane(dev_priv, pipe);
Ville Syrjälä0e088b82013-06-07 10:47:04 +03005818 }
5819}
5820
Ville Syrjälä017636c2013-12-05 15:51:37 +02005821static void ilk_init_lp_watermarks(struct drm_device *dev)
5822{
5823 struct drm_i915_private *dev_priv = dev->dev_private;
5824
5825 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5826 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5827 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5828
5829 /*
5830 * Don't touch WM1S_LP_EN here.
5831 * Doing so could cause underruns.
5832 */
5833}
5834
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03005835static void ironlake_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005836{
5837 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau231e54f2012-10-19 17:55:41 +01005838 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005839
Damien Lespiauf1e8fa52013-06-07 17:41:09 +01005840 /*
5841 * Required for FBC
5842 * WaFbcDisableDpfcClockGating:ilk
5843 */
Damien Lespiau4d47e4f2012-10-19 17:55:42 +01005844 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5845 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5846 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005847
5848 I915_WRITE(PCH_3DCGDIS0,
5849 MARIUNIT_CLOCK_GATE_DISABLE |
5850 SVSMUNIT_CLOCK_GATE_DISABLE);
5851 I915_WRITE(PCH_3DCGDIS1,
5852 VFMUNIT_CLOCK_GATE_DISABLE);
5853
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005854 /*
5855 * According to the spec the following bits should be set in
5856 * order to enable memory self-refresh
5857 * The bit 22/21 of 0x42004
5858 * The bit 5 of 0x42020
5859 * The bit 15 of 0x45000
5860 */
5861 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5862 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5863 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
Damien Lespiau4d47e4f2012-10-19 17:55:42 +01005864 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005865 I915_WRITE(DISP_ARB_CTL,
5866 (I915_READ(DISP_ARB_CTL) |
5867 DISP_FBC_WM_DIS));
Ville Syrjälä017636c2013-12-05 15:51:37 +02005868
5869 ilk_init_lp_watermarks(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005870
5871 /*
5872 * Based on the document from hardware guys the following bits
5873 * should be set unconditionally in order to enable FBC.
5874 * The bit 22 of 0x42000
5875 * The bit 22 of 0x42004
5876 * The bit 7,8,9 of 0x42020.
5877 */
5878 if (IS_IRONLAKE_M(dev)) {
Damien Lespiau4bb35332013-06-14 15:23:24 +01005879 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005880 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5881 I915_READ(ILK_DISPLAY_CHICKEN1) |
5882 ILK_FBCQ_DIS);
5883 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5884 I915_READ(ILK_DISPLAY_CHICKEN2) |
5885 ILK_DPARB_GATE);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005886 }
5887
Damien Lespiau4d47e4f2012-10-19 17:55:42 +01005888 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5889
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005890 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5891 I915_READ(ILK_DISPLAY_CHICKEN2) |
5892 ILK_ELPIN_409_SELECT);
5893 I915_WRITE(_3D_CHICKEN2,
5894 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5895 _3D_CHICKEN2_WM_READ_PIPELINED);
Daniel Vetter4358a372012-10-18 11:49:51 +02005896
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01005897 /* WaDisableRenderCachePipelinedFlush:ilk */
Daniel Vetter4358a372012-10-18 11:49:51 +02005898 I915_WRITE(CACHE_MODE_0,
5899 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
Daniel Vetter3107bd42012-10-31 22:52:31 +01005900
Akash Goel4e046322014-04-04 17:14:38 +05305901 /* WaDisable_RenderCache_OperationalFlush:ilk */
5902 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5903
Ville Syrjälä0e088b82013-06-07 10:47:04 +03005904 g4x_disable_trickle_feed(dev);
Ville Syrjäläbdad2b22013-06-07 10:47:03 +03005905
Daniel Vetter3107bd42012-10-31 22:52:31 +01005906 ibx_init_clock_gating(dev);
5907}
5908
5909static void cpt_init_clock_gating(struct drm_device *dev)
5910{
5911 struct drm_i915_private *dev_priv = dev->dev_private;
5912 int pipe;
Paulo Zanoni3f704fa2013-04-08 15:48:07 -03005913 uint32_t val;
Daniel Vetter3107bd42012-10-31 22:52:31 +01005914
5915 /*
5916 * On Ibex Peak and Cougar Point, we need to disable clock
5917 * gating for the panel power sequencer or it will fail to
5918 * start up when no ports are active.
5919 */
Jesse Barnescd664072013-10-02 10:34:19 -07005920 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5921 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5922 PCH_CPUNIT_CLOCK_GATE_DISABLE);
Daniel Vetter3107bd42012-10-31 22:52:31 +01005923 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5924 DPLS_EDP_PPS_FIX_DIS);
Takashi Iwai335c07b2012-12-11 11:46:29 +01005925 /* The below fixes the weird display corruption, a few pixels shifted
5926 * downward, on (only) LVDS of some HP laptops with IVY.
5927 */
Damien Lespiau055e3932014-08-18 13:49:10 +01005928 for_each_pipe(dev_priv, pipe) {
Paulo Zanonidc4bd2d2013-04-08 15:48:08 -03005929 val = I915_READ(TRANS_CHICKEN2(pipe));
5930 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5931 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005932 if (dev_priv->vbt.fdi_rx_polarity_inverted)
Paulo Zanoni3f704fa2013-04-08 15:48:07 -03005933 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
Paulo Zanonidc4bd2d2013-04-08 15:48:08 -03005934 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5935 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5936 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
Paulo Zanoni3f704fa2013-04-08 15:48:07 -03005937 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5938 }
Daniel Vetter3107bd42012-10-31 22:52:31 +01005939 /* WADP0ClockGatingDisable */
Damien Lespiau055e3932014-08-18 13:49:10 +01005940 for_each_pipe(dev_priv, pipe) {
Daniel Vetter3107bd42012-10-31 22:52:31 +01005941 I915_WRITE(TRANS_CHICKEN1(pipe),
5942 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5943 }
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005944}
5945
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01005946static void gen6_check_mch_setup(struct drm_device *dev)
5947{
5948 struct drm_i915_private *dev_priv = dev->dev_private;
5949 uint32_t tmp;
5950
5951 tmp = I915_READ(MCH_SSKPD);
Daniel Vetterdf662a22014-08-04 11:17:25 +02005952 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5953 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5954 tmp);
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01005955}
5956
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03005957static void gen6_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005958{
5959 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau231e54f2012-10-19 17:55:41 +01005960 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005961
Damien Lespiau231e54f2012-10-19 17:55:41 +01005962 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005963
5964 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5965 I915_READ(ILK_DISPLAY_CHICKEN2) |
5966 ILK_ELPIN_409_SELECT);
5967
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01005968 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
Daniel Vetter42839082012-12-14 23:38:28 +01005969 I915_WRITE(_3D_CHICKEN,
5970 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5971
Akash Goel4e046322014-04-04 17:14:38 +05305972 /* WaDisable_RenderCache_OperationalFlush:snb */
5973 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5974
Ville Syrjälä8d85d272014-02-04 21:59:15 +02005975 /*
5976 * BSpec recoomends 8x4 when MSAA is used,
5977 * however in practice 16x4 seems fastest.
Ville Syrjäläc5c98a52014-02-05 12:43:47 +02005978 *
5979 * Note that PS/WM thread counts depend on the WIZ hashing
5980 * disable bit, which we don't touch here, but it's good
5981 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
Ville Syrjälä8d85d272014-02-04 21:59:15 +02005982 */
5983 I915_WRITE(GEN6_GT_MODE,
Damien Lespiau98533252014-12-08 17:33:51 +00005984 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
Ville Syrjälä8d85d272014-02-04 21:59:15 +02005985
Ville Syrjälä017636c2013-12-05 15:51:37 +02005986 ilk_init_lp_watermarks(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005987
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005988 I915_WRITE(CACHE_MODE_0,
Daniel Vetter50743292012-04-26 22:02:54 +02005989 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03005990
5991 I915_WRITE(GEN6_UCGCTL1,
5992 I915_READ(GEN6_UCGCTL1) |
5993 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5994 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5995
5996 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5997 * gating disable must be set. Failure to set it results in
5998 * flickering pixels due to Z write ordering failures after
5999 * some amount of runtime in the Mesa "fire" demo, and Unigine
6000 * Sanctuary and Tropics, and apparently anything else with
6001 * alpha test or pixel discard.
6002 *
6003 * According to the spec, bit 11 (RCCUNIT) must also be set,
6004 * but we didn't debug actual testcases to find it out.
Jesse Barnes0f846f82012-06-14 11:04:47 -07006005 *
Ville Syrjäläef593182014-01-22 21:32:47 +02006006 * WaDisableRCCUnitClockGating:snb
6007 * WaDisableRCPBUnitClockGating:snb
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006008 */
6009 I915_WRITE(GEN6_UCGCTL2,
6010 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6011 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6012
Ville Syrjälä5eb146d2014-02-04 21:59:16 +02006013 /* WaStripsFansDisableFastClipPerformanceFix:snb */
Ville Syrjälä743b57d2014-02-04 21:59:17 +02006014 I915_WRITE(_3D_CHICKEN3,
6015 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006016
6017 /*
Ville Syrjäläe927ecd2014-02-04 21:59:18 +02006018 * Bspec says:
6019 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6020 * 3DSTATE_SF number of SF output attributes is more than 16."
6021 */
6022 I915_WRITE(_3D_CHICKEN3,
6023 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6024
6025 /*
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006026 * According to the spec the following bits should be
6027 * set in order to enable memory self-refresh and fbc:
6028 * The bit21 and bit22 of 0x42000
6029 * The bit21 and bit22 of 0x42004
6030 * The bit5 and bit7 of 0x42020
6031 * The bit14 of 0x70180
6032 * The bit14 of 0x71180
Damien Lespiau4bb35332013-06-14 15:23:24 +01006033 *
6034 * WaFbcAsynchFlipDisableFbcQueue:snb
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006035 */
6036 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6037 I915_READ(ILK_DISPLAY_CHICKEN1) |
6038 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6039 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6040 I915_READ(ILK_DISPLAY_CHICKEN2) |
6041 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
Damien Lespiau231e54f2012-10-19 17:55:41 +01006042 I915_WRITE(ILK_DSPCLK_GATE_D,
6043 I915_READ(ILK_DSPCLK_GATE_D) |
6044 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6045 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006046
Ville Syrjälä0e088b82013-06-07 10:47:04 +03006047 g4x_disable_trickle_feed(dev);
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07006048
Daniel Vetter3107bd42012-10-31 22:52:31 +01006049 cpt_init_clock_gating(dev);
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01006050
6051 gen6_check_mch_setup(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006052}
6053
6054static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6055{
6056 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6057
Ville Syrjälä3aad9052014-01-22 21:32:59 +02006058 /*
Ville Syrjälä46680e02014-01-22 21:33:01 +02006059 * WaVSThreadDispatchOverride:ivb,vlv
Ville Syrjälä3aad9052014-01-22 21:32:59 +02006060 *
6061 * This actually overrides the dispatch
6062 * mode for all thread types.
6063 */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006064 reg &= ~GEN7_FF_SCHED_MASK;
6065 reg |= GEN7_FF_TS_SCHED_HW;
6066 reg |= GEN7_FF_VS_SCHED_HW;
6067 reg |= GEN7_FF_DS_SCHED_HW;
6068
6069 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6070}
6071
Paulo Zanoni17a303e2012-11-20 15:12:07 -02006072static void lpt_init_clock_gating(struct drm_device *dev)
6073{
6074 struct drm_i915_private *dev_priv = dev->dev_private;
6075
6076 /*
6077 * TODO: this bit should only be enabled when really needed, then
6078 * disabled when not needed anymore in order to save power.
6079 */
6080 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6081 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6082 I915_READ(SOUTH_DSPCLK_GATE_D) |
6083 PCH_LP_PARTITION_LEVEL_DISABLE);
Paulo Zanoni0a790cd2013-04-17 18:15:49 -03006084
6085 /* WADPOClockGatingDisable:hsw */
6086 I915_WRITE(_TRANSA_CHICKEN1,
6087 I915_READ(_TRANSA_CHICKEN1) |
6088 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
Paulo Zanoni17a303e2012-11-20 15:12:07 -02006089}
6090
Imre Deak7d708ee2013-04-17 14:04:50 +03006091static void lpt_suspend_hw(struct drm_device *dev)
6092{
6093 struct drm_i915_private *dev_priv = dev->dev_private;
6094
6095 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6096 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6097
6098 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6099 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6100 }
6101}
6102
Paulo Zanoni47c2bd92014-08-21 17:09:37 -03006103static void broadwell_init_clock_gating(struct drm_device *dev)
Ben Widawsky1020a5c2013-11-02 21:07:06 -07006104{
6105 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau07d27e22014-03-03 17:31:46 +00006106 enum pipe pipe;
Ben Widawsky1020a5c2013-11-02 21:07:06 -07006107
6108 I915_WRITE(WM3_LP_ILK, 0);
6109 I915_WRITE(WM2_LP_ILK, 0);
6110 I915_WRITE(WM1_LP_ILK, 0);
Ben Widawsky50ed5fb2013-11-02 21:07:40 -07006111
Ben Widawskyab57fff2013-12-12 15:28:04 -08006112 /* WaSwitchSolVfFArbitrationPriority:bdw */
Ben Widawsky50ed5fb2013-11-02 21:07:40 -07006113 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07006114
Ben Widawskyab57fff2013-12-12 15:28:04 -08006115 /* WaPsrDPAMaskVBlankInSRD:bdw */
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07006116 I915_WRITE(CHICKEN_PAR1_1,
6117 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6118
Ben Widawskyab57fff2013-12-12 15:28:04 -08006119 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
Damien Lespiau055e3932014-08-18 13:49:10 +01006120 for_each_pipe(dev_priv, pipe) {
Damien Lespiau07d27e22014-03-03 17:31:46 +00006121 I915_WRITE(CHICKEN_PIPESL_1(pipe),
Ville Syrjäläc7c65622014-03-05 13:05:45 +02006122 I915_READ(CHICKEN_PIPESL_1(pipe)) |
Ville Syrjälä8f670bb2014-03-05 13:05:47 +02006123 BDW_DPRS_MASK_VBLANK_SRD);
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07006124 }
Ben Widawsky63801f22013-12-12 17:26:03 -08006125
Ben Widawskyab57fff2013-12-12 15:28:04 -08006126 /* WaVSRefCountFullforceMissDisable:bdw */
6127 /* WaDSRefCountFullforceMissDisable:bdw */
6128 I915_WRITE(GEN7_FF_THREAD_MODE,
6129 I915_READ(GEN7_FF_THREAD_MODE) &
6130 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
Ville Syrjälä36075a42014-02-04 21:59:21 +02006131
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02006132 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6133 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02006134
6135 /* WaDisableSDEUnitClockGating:bdw */
6136 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6137 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
Damien Lespiau5d708682014-03-26 18:41:51 +00006138
Paulo Zanoni89d6b2b2014-08-21 17:09:36 -03006139 lpt_init_clock_gating(dev);
Ben Widawsky1020a5c2013-11-02 21:07:06 -07006140}
6141
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03006142static void haswell_init_clock_gating(struct drm_device *dev)
6143{
6144 struct drm_i915_private *dev_priv = dev->dev_private;
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03006145
Ville Syrjälä017636c2013-12-05 15:51:37 +02006146 ilk_init_lp_watermarks(dev);
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03006147
Francisco Jerezf3fc4882013-10-02 15:53:16 -07006148 /* L3 caching of data atomics doesn't work -- disable it. */
6149 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6150 I915_WRITE(HSW_ROW_CHICKEN3,
6151 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6152
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006153 /* This is required by WaCatErrorRejectionIssue:hsw */
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03006154 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6155 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6156 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6157
Ville Syrjäläe36ea7f2014-01-22 21:33:00 +02006158 /* WaVSRefCountFullforceMissDisable:hsw */
6159 I915_WRITE(GEN7_FF_THREAD_MODE,
6160 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03006161
Akash Goel4e046322014-04-04 17:14:38 +05306162 /* WaDisable_RenderCache_OperationalFlush:hsw */
6163 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6164
Chia-I Wufe27c602014-01-28 13:29:33 +08006165 /* enable HiZ Raw Stall Optimization */
6166 I915_WRITE(CACHE_MODE_0_GEN7,
6167 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6168
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006169 /* WaDisable4x2SubspanOptimization:hsw */
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03006170 I915_WRITE(CACHE_MODE_1,
6171 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Eugeni Dodonov1544d9d2012-07-02 11:51:10 -03006172
Ville Syrjäläa12c4962014-02-04 21:59:20 +02006173 /*
6174 * BSpec recommends 8x4 when MSAA is used,
6175 * however in practice 16x4 seems fastest.
Ville Syrjäläc5c98a52014-02-05 12:43:47 +02006176 *
6177 * Note that PS/WM thread counts depend on the WIZ hashing
6178 * disable bit, which we don't touch here, but it's good
6179 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
Ville Syrjäläa12c4962014-02-04 21:59:20 +02006180 */
6181 I915_WRITE(GEN7_GT_MODE,
Damien Lespiau98533252014-12-08 17:33:51 +00006182 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
Ville Syrjäläa12c4962014-02-04 21:59:20 +02006183
Kenneth Graunke94411592014-12-31 16:23:00 -08006184 /* WaSampleCChickenBitEnable:hsw */
6185 I915_WRITE(HALF_SLICE_CHICKEN3,
6186 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6187
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006188 /* WaSwitchSolVfFArbitrationPriority:hsw */
Ben Widawskye3dff582013-03-20 14:49:14 -07006189 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6190
Paulo Zanoni90a88642013-05-03 17:23:45 -03006191 /* WaRsPkgCStateDisplayPMReq:hsw */
6192 I915_WRITE(CHICKEN_PAR1_1,
6193 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
Eugeni Dodonov1544d9d2012-07-02 11:51:10 -03006194
Paulo Zanoni17a303e2012-11-20 15:12:07 -02006195 lpt_init_clock_gating(dev);
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03006196}
6197
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006198static void ivybridge_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006199{
6200 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky20848222012-05-04 18:58:59 -07006201 uint32_t snpcr;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006202
Ville Syrjälä017636c2013-12-05 15:51:37 +02006203 ilk_init_lp_watermarks(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006204
Damien Lespiau231e54f2012-10-19 17:55:41 +01006205 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006206
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006207 /* WaDisableEarlyCull:ivb */
Jesse Barnes87f80202012-10-02 17:43:41 -05006208 I915_WRITE(_3D_CHICKEN3,
6209 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6210
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006211 /* WaDisableBackToBackFlipFix:ivb */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006212 I915_WRITE(IVB_CHICKEN3,
6213 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6214 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6215
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006216 /* WaDisablePSDDualDispatchEnable:ivb */
Jesse Barnes12f33822012-10-25 12:15:45 -07006217 if (IS_IVB_GT1(dev))
6218 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6219 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
Jesse Barnes12f33822012-10-25 12:15:45 -07006220
Akash Goel4e046322014-04-04 17:14:38 +05306221 /* WaDisable_RenderCache_OperationalFlush:ivb */
6222 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6223
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006224 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006225 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6226 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6227
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006228 /* WaApplyL3ControlAndL3ChickenMode:ivb */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006229 I915_WRITE(GEN7_L3CNTLREG1,
6230 GEN7_WA_FOR_GEN7_L3_CONTROL);
6231 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
Jesse Barnes8ab43972012-10-25 12:15:42 -07006232 GEN7_WA_L3_CHICKEN_MODE);
6233 if (IS_IVB_GT1(dev))
6234 I915_WRITE(GEN7_ROW_CHICKEN2,
6235 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
Ville Syrjälä412236c2014-01-22 21:32:44 +02006236 else {
6237 /* must write both registers */
6238 I915_WRITE(GEN7_ROW_CHICKEN2,
6239 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
Jesse Barnes8ab43972012-10-25 12:15:42 -07006240 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6241 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
Ville Syrjälä412236c2014-01-22 21:32:44 +02006242 }
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006243
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006244 /* WaForceL3Serialization:ivb */
Jesse Barnes61939d92012-10-02 17:43:38 -05006245 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6246 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6247
Ville Syrjälä1b80a19a2014-01-22 21:32:53 +02006248 /*
Jesse Barnes0f846f82012-06-14 11:04:47 -07006249 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006250 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
Jesse Barnes0f846f82012-06-14 11:04:47 -07006251 */
6252 I915_WRITE(GEN6_UCGCTL2,
Ville Syrjälä28acf3b2014-01-22 21:32:48 +02006253 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
Jesse Barnes0f846f82012-06-14 11:04:47 -07006254
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006255 /* This is required by WaCatErrorRejectionIssue:ivb */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006256 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6257 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6258 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6259
Ville Syrjälä0e088b82013-06-07 10:47:04 +03006260 g4x_disable_trickle_feed(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006261
6262 gen7_setup_fixed_func_scheduler(dev_priv);
Daniel Vetter97e19302012-04-24 16:00:21 +02006263
Chris Wilson22721342014-03-04 09:41:43 +00006264 if (0) { /* causes HiZ corruption on ivb:gt1 */
6265 /* enable HiZ Raw Stall Optimization */
6266 I915_WRITE(CACHE_MODE_0_GEN7,
6267 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6268 }
Chia-I Wu116f2b62014-01-28 13:29:34 +08006269
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006270 /* WaDisable4x2SubspanOptimization:ivb */
Daniel Vetter97e19302012-04-24 16:00:21 +02006271 I915_WRITE(CACHE_MODE_1,
6272 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Ben Widawsky20848222012-05-04 18:58:59 -07006273
Ville Syrjäläa607c1a2014-02-04 21:59:19 +02006274 /*
6275 * BSpec recommends 8x4 when MSAA is used,
6276 * however in practice 16x4 seems fastest.
Ville Syrjäläc5c98a52014-02-05 12:43:47 +02006277 *
6278 * Note that PS/WM thread counts depend on the WIZ hashing
6279 * disable bit, which we don't touch here, but it's good
6280 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
Ville Syrjäläa607c1a2014-02-04 21:59:19 +02006281 */
6282 I915_WRITE(GEN7_GT_MODE,
Damien Lespiau98533252014-12-08 17:33:51 +00006283 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
Ville Syrjäläa607c1a2014-02-04 21:59:19 +02006284
Ben Widawsky20848222012-05-04 18:58:59 -07006285 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6286 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6287 snpcr |= GEN6_MBC_SNPCR_MED;
6288 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
Daniel Vetter3107bd42012-10-31 22:52:31 +01006289
Ben Widawskyab5c6082013-04-05 13:12:41 -07006290 if (!HAS_PCH_NOP(dev))
6291 cpt_init_clock_gating(dev);
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01006292
6293 gen6_check_mch_setup(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006294}
6295
Ville Syrjäläc6beb132015-03-05 21:19:48 +02006296static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6297{
6298 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6299
6300 /*
6301 * Disable trickle feed and enable pnd deadline calculation
6302 */
6303 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6304 I915_WRITE(CBR1_VLV, 0);
6305}
6306
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006307static void valleyview_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006308{
6309 struct drm_i915_private *dev_priv = dev->dev_private;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006310
Ville Syrjäläc6beb132015-03-05 21:19:48 +02006311 vlv_init_display_clock_gating(dev_priv);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006312
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006313 /* WaDisableEarlyCull:vlv */
Jesse Barnes87f80202012-10-02 17:43:41 -05006314 I915_WRITE(_3D_CHICKEN3,
6315 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6316
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006317 /* WaDisableBackToBackFlipFix:vlv */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006318 I915_WRITE(IVB_CHICKEN3,
6319 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6320 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6321
Ville Syrjäläfad7d362014-01-22 21:32:39 +02006322 /* WaPsdDispatchEnable:vlv */
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006323 /* WaDisablePSDDualDispatchEnable:vlv */
Jesse Barnes12f33822012-10-25 12:15:45 -07006324 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
Jesse Barnesd3bc0302013-03-08 10:45:51 -08006325 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6326 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
Jesse Barnes12f33822012-10-25 12:15:45 -07006327
Akash Goel4e046322014-04-04 17:14:38 +05306328 /* WaDisable_RenderCache_OperationalFlush:vlv */
6329 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6330
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006331 /* WaForceL3Serialization:vlv */
Jesse Barnes61939d92012-10-02 17:43:38 -05006332 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6333 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6334
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006335 /* WaDisableDopClockGating:vlv */
Jesse Barnes8ab43972012-10-25 12:15:42 -07006336 I915_WRITE(GEN7_ROW_CHICKEN2,
6337 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6338
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006339 /* This is required by WaCatErrorRejectionIssue:vlv */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006340 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6341 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6342 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6343
Ville Syrjälä46680e02014-01-22 21:33:01 +02006344 gen7_setup_fixed_func_scheduler(dev_priv);
6345
Ville Syrjälä3c0edae2014-01-22 21:32:56 +02006346 /*
Jesse Barnes0f846f82012-06-14 11:04:47 -07006347 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006348 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
Jesse Barnes0f846f82012-06-14 11:04:47 -07006349 */
6350 I915_WRITE(GEN6_UCGCTL2,
Ville Syrjälä3c0edae2014-01-22 21:32:56 +02006351 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
Jesse Barnes0f846f82012-06-14 11:04:47 -07006352
Akash Goelc98f5062014-03-24 23:00:07 +05306353 /* WaDisableL3Bank2xClockGate:vlv
6354 * Disabling L3 clock gating- MMIO 940c[25] = 1
6355 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6356 I915_WRITE(GEN7_UCGCTL4,
6357 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
Jesse Barnese3f33d42012-06-14 11:04:50 -07006358
Ville Syrjäläafd58e72014-01-22 21:33:03 +02006359 /*
6360 * BSpec says this must be set, even though
6361 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6362 */
Daniel Vetter6b26c862012-04-24 14:04:12 +02006363 I915_WRITE(CACHE_MODE_1,
6364 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Jesse Barnes79831172012-06-20 10:53:12 -07006365
6366 /*
Ville Syrjäläda2518f2015-01-21 19:38:01 +02006367 * BSpec recommends 8x4 when MSAA is used,
6368 * however in practice 16x4 seems fastest.
6369 *
6370 * Note that PS/WM thread counts depend on the WIZ hashing
6371 * disable bit, which we don't touch here, but it's good
6372 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6373 */
6374 I915_WRITE(GEN7_GT_MODE,
6375 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6376
6377 /*
Ville Syrjälä031994e2014-01-22 21:32:46 +02006378 * WaIncreaseL3CreditsForVLVB0:vlv
6379 * This is the hardware default actually.
6380 */
6381 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6382
6383 /*
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006384 * WaDisableVLVClockGating_VBIIssue:vlv
Jesse Barnes2d809572012-10-25 12:15:44 -07006385 * Disable clock gating on th GCFG unit to prevent a delay
6386 * in the reporting of vblank events.
6387 */
Ville Syrjälä7a0d1ee2014-01-22 21:33:04 +02006388 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006389}
6390
Ville Syrjäläa4565da2014-04-09 13:28:10 +03006391static void cherryview_init_clock_gating(struct drm_device *dev)
6392{
6393 struct drm_i915_private *dev_priv = dev->dev_private;
6394
Ville Syrjäläc6beb132015-03-05 21:19:48 +02006395 vlv_init_display_clock_gating(dev_priv);
Ville Syrjälädd811e72014-04-09 13:28:33 +03006396
Ville Syrjälä232ce332014-04-09 13:28:35 +03006397 /* WaVSRefCountFullforceMissDisable:chv */
6398 /* WaDSRefCountFullforceMissDisable:chv */
6399 I915_WRITE(GEN7_FF_THREAD_MODE,
6400 I915_READ(GEN7_FF_THREAD_MODE) &
6401 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
Ville Syrjäläacea6f92014-04-09 13:28:36 +03006402
6403 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6404 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6405 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
Ville Syrjälä08466972014-04-09 13:28:37 +03006406
6407 /* WaDisableCSUnitClockGating:chv */
6408 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6409 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
Ville Syrjäläc6317802014-04-09 13:28:38 +03006410
6411 /* WaDisableSDEUnitClockGating:chv */
6412 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6413 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
Ville Syrjäläa4565da2014-04-09 13:28:10 +03006414}
6415
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006416static void g4x_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006417{
6418 struct drm_i915_private *dev_priv = dev->dev_private;
6419 uint32_t dspclk_gate;
6420
6421 I915_WRITE(RENCLK_GATE_D1, 0);
6422 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6423 GS_UNIT_CLOCK_GATE_DISABLE |
6424 CL_UNIT_CLOCK_GATE_DISABLE);
6425 I915_WRITE(RAMCLK_GATE_D, 0);
6426 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6427 OVRUNIT_CLOCK_GATE_DISABLE |
6428 OVCUNIT_CLOCK_GATE_DISABLE;
6429 if (IS_GM45(dev))
6430 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6431 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
Daniel Vetter4358a372012-10-18 11:49:51 +02006432
6433 /* WaDisableRenderCachePipelinedFlush */
6434 I915_WRITE(CACHE_MODE_0,
6435 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
Ville Syrjäläde1aa622013-06-07 10:47:01 +03006436
Akash Goel4e046322014-04-04 17:14:38 +05306437 /* WaDisable_RenderCache_OperationalFlush:g4x */
6438 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6439
Ville Syrjälä0e088b82013-06-07 10:47:04 +03006440 g4x_disable_trickle_feed(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006441}
6442
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006443static void crestline_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006444{
6445 struct drm_i915_private *dev_priv = dev->dev_private;
6446
6447 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6448 I915_WRITE(RENCLK_GATE_D2, 0);
6449 I915_WRITE(DSPCLK_GATE_D, 0);
6450 I915_WRITE(RAMCLK_GATE_D, 0);
6451 I915_WRITE16(DEUC, 0);
Ville Syrjälä20f94962013-06-07 10:47:02 +03006452 I915_WRITE(MI_ARB_STATE,
6453 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
Akash Goel4e046322014-04-04 17:14:38 +05306454
6455 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6456 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006457}
6458
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006459static void broadwater_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006460{
6461 struct drm_i915_private *dev_priv = dev->dev_private;
6462
6463 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6464 I965_RCC_CLOCK_GATE_DISABLE |
6465 I965_RCPB_CLOCK_GATE_DISABLE |
6466 I965_ISC_CLOCK_GATE_DISABLE |
6467 I965_FBC_CLOCK_GATE_DISABLE);
6468 I915_WRITE(RENCLK_GATE_D2, 0);
Ville Syrjälä20f94962013-06-07 10:47:02 +03006469 I915_WRITE(MI_ARB_STATE,
6470 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
Akash Goel4e046322014-04-04 17:14:38 +05306471
6472 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6473 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006474}
6475
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006476static void gen3_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006477{
6478 struct drm_i915_private *dev_priv = dev->dev_private;
6479 u32 dstate = I915_READ(D_STATE);
6480
6481 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6482 DSTATE_DOT_CLOCK_GATING;
6483 I915_WRITE(D_STATE, dstate);
Chris Wilson13a86b82012-04-24 14:51:43 +01006484
6485 if (IS_PINEVIEW(dev))
6486 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
Daniel Vetter974a3b02012-09-09 11:54:16 +02006487
6488 /* IIR "flip pending" means done if this bit is set */
6489 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
Ville Syrjälä12fabbcb92014-02-25 15:13:38 +02006490
6491 /* interrupts should cause a wake up from C3 */
Ville Syrjälä32992542014-02-25 15:13:39 +02006492 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
Ville Syrjälädbb42742014-02-25 15:13:41 +02006493
6494 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6495 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
Ville Syrjälä10383922014-08-15 01:21:54 +03006496
6497 I915_WRITE(MI_ARB_STATE,
6498 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006499}
6500
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006501static void i85x_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006502{
6503 struct drm_i915_private *dev_priv = dev->dev_private;
6504
6505 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
Ville Syrjälä54e472a2014-02-25 15:13:40 +02006506
6507 /* interrupts should cause a wake up from C3 */
6508 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6509 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
Ville Syrjälä10383922014-08-15 01:21:54 +03006510
6511 I915_WRITE(MEM_MODE,
6512 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006513}
6514
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006515static void i830_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006516{
6517 struct drm_i915_private *dev_priv = dev->dev_private;
6518
6519 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
Ville Syrjälä10383922014-08-15 01:21:54 +03006520
6521 I915_WRITE(MEM_MODE,
6522 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6523 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006524}
6525
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006526void intel_init_clock_gating(struct drm_device *dev)
6527{
6528 struct drm_i915_private *dev_priv = dev->dev_private;
6529
Damien Lespiauc57e3552015-02-09 19:33:05 +00006530 if (dev_priv->display.init_clock_gating)
6531 dev_priv->display.init_clock_gating(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006532}
6533
Imre Deak7d708ee2013-04-17 14:04:50 +03006534void intel_suspend_hw(struct drm_device *dev)
6535{
6536 if (HAS_PCH_LPT(dev))
6537 lpt_suspend_hw(dev);
6538}
6539
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006540/* Set up chip specific power management-related functions */
6541void intel_init_pm(struct drm_device *dev)
6542{
6543 struct drm_i915_private *dev_priv = dev->dev_private;
6544
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02006545 intel_fbc_init(dev_priv);
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006546
Daniel Vetterc921aba2012-04-26 23:28:17 +02006547 /* For cxsr */
6548 if (IS_PINEVIEW(dev))
6549 i915_pineview_get_mem_freq(dev);
6550 else if (IS_GEN5(dev))
6551 i915_ironlake_get_mem_freq(dev);
6552
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006553 /* For FIFO watermark updates */
Damien Lespiauf5ed50c2014-11-13 17:51:52 +00006554 if (INTEL_INFO(dev)->gen >= 9) {
Pradeep Bhat2af30a52014-11-04 17:06:38 +00006555 skl_setup_wm_latency(dev);
6556
Damien Lespiau45db2192015-02-09 19:33:09 +00006557 dev_priv->display.init_clock_gating = skl_init_clock_gating;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00006558 dev_priv->display.update_wm = skl_update_wm;
6559 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
Damien Lespiauc83155a2014-03-28 00:18:35 +05306560 } else if (HAS_PCH_SPLIT(dev)) {
Damien Lespiaufa50ad62014-03-17 18:01:16 +00006561 ilk_setup_wm_latency(dev);
Ville Syrjälä53615a52013-08-01 16:18:50 +03006562
Ville Syrjäläbd602542014-01-07 16:14:10 +02006563 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6564 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6565 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6566 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6567 dev_priv->display.update_wm = ilk_update_wm;
6568 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6569 } else {
6570 DRM_DEBUG_KMS("Failed to read display plane latency. "
6571 "Disable CxSR\n");
6572 }
6573
6574 if (IS_GEN5(dev))
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006575 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
Ville Syrjäläbd602542014-01-07 16:14:10 +02006576 else if (IS_GEN6(dev))
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006577 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
Ville Syrjäläbd602542014-01-07 16:14:10 +02006578 else if (IS_IVYBRIDGE(dev))
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006579 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
Ville Syrjäläbd602542014-01-07 16:14:10 +02006580 else if (IS_HASWELL(dev))
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03006581 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
Ville Syrjäläbd602542014-01-07 16:14:10 +02006582 else if (INTEL_INFO(dev)->gen == 8)
Paulo Zanoni47c2bd92014-08-21 17:09:37 -03006583 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
Ville Syrjäläa4565da2014-04-09 13:28:10 +03006584 } else if (IS_CHERRYVIEW(dev)) {
Ville Syrjäläae801522015-03-05 21:19:49 +02006585 dev_priv->display.update_wm = valleyview_update_wm;
Gajanan Bhat01e184c2014-08-07 17:03:30 +05306586 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
Ville Syrjäläa4565da2014-04-09 13:28:10 +03006587 dev_priv->display.init_clock_gating =
6588 cherryview_init_clock_gating;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006589 } else if (IS_VALLEYVIEW(dev)) {
6590 dev_priv->display.update_wm = valleyview_update_wm;
Gajanan Bhat01e184c2014-08-07 17:03:30 +05306591 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006592 dev_priv->display.init_clock_gating =
6593 valleyview_init_clock_gating;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006594 } else if (IS_PINEVIEW(dev)) {
6595 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6596 dev_priv->is_ddr3,
6597 dev_priv->fsb_freq,
6598 dev_priv->mem_freq)) {
6599 DRM_INFO("failed to find known CxSR latency "
6600 "(found ddr%s fsb freq %d, mem freq %d), "
6601 "disabling CxSR\n",
6602 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6603 dev_priv->fsb_freq, dev_priv->mem_freq);
6604 /* Disable CxSR and never update its watermark again */
Imre Deak5209b1f2014-07-01 12:36:17 +03006605 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006606 dev_priv->display.update_wm = NULL;
6607 } else
6608 dev_priv->display.update_wm = pineview_update_wm;
6609 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6610 } else if (IS_G4X(dev)) {
6611 dev_priv->display.update_wm = g4x_update_wm;
6612 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6613 } else if (IS_GEN4(dev)) {
6614 dev_priv->display.update_wm = i965_update_wm;
6615 if (IS_CRESTLINE(dev))
6616 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6617 else if (IS_BROADWATER(dev))
6618 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6619 } else if (IS_GEN3(dev)) {
6620 dev_priv->display.update_wm = i9xx_update_wm;
6621 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6622 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
Daniel Vetterfeb56b92013-12-14 20:38:30 -02006623 } else if (IS_GEN2(dev)) {
6624 if (INTEL_INFO(dev)->num_pipes == 1) {
6625 dev_priv->display.update_wm = i845_update_wm;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006626 dev_priv->display.get_fifo_size = i845_get_fifo_size;
Daniel Vetterfeb56b92013-12-14 20:38:30 -02006627 } else {
6628 dev_priv->display.update_wm = i9xx_update_wm;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006629 dev_priv->display.get_fifo_size = i830_get_fifo_size;
Daniel Vetterfeb56b92013-12-14 20:38:30 -02006630 }
6631
6632 if (IS_I85X(dev) || IS_I865G(dev))
6633 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6634 else
6635 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6636 } else {
6637 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006638 }
6639}
6640
Tom O'Rourke151a49d2014-11-13 18:50:10 -08006641int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
Ben Widawsky42c05262012-09-26 10:34:00 -07006642{
Jesse Barnes4fc688c2012-11-02 11:14:01 -07006643 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
Ben Widawsky42c05262012-09-26 10:34:00 -07006644
6645 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6646 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6647 return -EAGAIN;
6648 }
6649
6650 I915_WRITE(GEN6_PCODE_DATA, *val);
Damien Lespiaudddab342014-11-13 17:51:50 +00006651 I915_WRITE(GEN6_PCODE_DATA1, 0);
Ben Widawsky42c05262012-09-26 10:34:00 -07006652 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6653
6654 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6655 500)) {
6656 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6657 return -ETIMEDOUT;
6658 }
6659
6660 *val = I915_READ(GEN6_PCODE_DATA);
6661 I915_WRITE(GEN6_PCODE_DATA, 0);
6662
6663 return 0;
6664}
6665
Tom O'Rourke151a49d2014-11-13 18:50:10 -08006666int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
Ben Widawsky42c05262012-09-26 10:34:00 -07006667{
Jesse Barnes4fc688c2012-11-02 11:14:01 -07006668 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
Ben Widawsky42c05262012-09-26 10:34:00 -07006669
6670 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6671 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6672 return -EAGAIN;
6673 }
6674
6675 I915_WRITE(GEN6_PCODE_DATA, val);
6676 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6677
6678 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6679 500)) {
6680 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6681 return -ETIMEDOUT;
6682 }
6683
6684 I915_WRITE(GEN6_PCODE_DATA, 0);
6685
6686 return 0;
6687}
Jesse Barnesa0e4e192013-04-02 11:23:05 -07006688
Ville Syrjälädd06f882014-11-10 22:55:12 +02006689static int vlv_gpu_freq_div(unsigned int czclk_freq)
Jesse Barnes855ba3b2013-04-17 15:54:57 -07006690{
Ville Syrjälädd06f882014-11-10 22:55:12 +02006691 switch (czclk_freq) {
6692 case 200:
6693 return 10;
6694 case 267:
6695 return 12;
6696 case 320:
6697 case 333:
Ville Syrjälädd06f882014-11-10 22:55:12 +02006698 return 16;
Ville Syrjäläab3fb152014-11-10 22:55:15 +02006699 case 400:
6700 return 20;
Jesse Barnes855ba3b2013-04-17 15:54:57 -07006701 default:
6702 return -1;
6703 }
Ville Syrjälädd06f882014-11-10 22:55:12 +02006704}
Jesse Barnes855ba3b2013-04-17 15:54:57 -07006705
Ville Syrjälädd06f882014-11-10 22:55:12 +02006706static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6707{
6708 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6709
6710 div = vlv_gpu_freq_div(czclk_freq);
6711 if (div < 0)
6712 return div;
6713
6714 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
Jesse Barnes855ba3b2013-04-17 15:54:57 -07006715}
6716
Fengguang Wub55dd642014-07-12 11:21:39 +02006717static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
Jesse Barnes855ba3b2013-04-17 15:54:57 -07006718{
Ville Syrjälädd06f882014-11-10 22:55:12 +02006719 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
Jesse Barnes855ba3b2013-04-17 15:54:57 -07006720
Ville Syrjälädd06f882014-11-10 22:55:12 +02006721 mul = vlv_gpu_freq_div(czclk_freq);
6722 if (mul < 0)
6723 return mul;
Jesse Barnes855ba3b2013-04-17 15:54:57 -07006724
Ville Syrjälädd06f882014-11-10 22:55:12 +02006725 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
Jesse Barnes855ba3b2013-04-17 15:54:57 -07006726}
6727
Fengguang Wub55dd642014-07-12 11:21:39 +02006728static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
Deepak S22b1b2f2014-07-12 14:54:33 +05306729{
Ville Syrjälädd06f882014-11-10 22:55:12 +02006730 int div, czclk_freq = dev_priv->rps.cz_freq;
Deepak S22b1b2f2014-07-12 14:54:33 +05306731
Ville Syrjälädd06f882014-11-10 22:55:12 +02006732 div = vlv_gpu_freq_div(czclk_freq) / 2;
6733 if (div < 0)
6734 return div;
Deepak S22b1b2f2014-07-12 14:54:33 +05306735
Ville Syrjälädd06f882014-11-10 22:55:12 +02006736 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
Deepak S22b1b2f2014-07-12 14:54:33 +05306737}
6738
Fengguang Wub55dd642014-07-12 11:21:39 +02006739static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
Deepak S22b1b2f2014-07-12 14:54:33 +05306740{
Ville Syrjälädd06f882014-11-10 22:55:12 +02006741 int mul, czclk_freq = dev_priv->rps.cz_freq;
Deepak S22b1b2f2014-07-12 14:54:33 +05306742
Ville Syrjälädd06f882014-11-10 22:55:12 +02006743 mul = vlv_gpu_freq_div(czclk_freq) / 2;
6744 if (mul < 0)
6745 return mul;
Deepak S22b1b2f2014-07-12 14:54:33 +05306746
Ville Syrjälä1c147622014-08-18 14:42:43 +03006747 /* CHV needs even values */
Ville Syrjälädd06f882014-11-10 22:55:12 +02006748 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
Deepak S22b1b2f2014-07-12 14:54:33 +05306749}
6750
Ville Syrjälä616bc822015-01-23 21:04:25 +02006751int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
6752{
Akash Goel80b6dda2015-03-06 11:07:15 +05306753 if (IS_GEN9(dev_priv->dev))
6754 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
6755 else if (IS_CHERRYVIEW(dev_priv->dev))
Ville Syrjälä616bc822015-01-23 21:04:25 +02006756 return chv_gpu_freq(dev_priv, val);
6757 else if (IS_VALLEYVIEW(dev_priv->dev))
6758 return byt_gpu_freq(dev_priv, val);
6759 else
6760 return val * GT_FREQUENCY_MULTIPLIER;
6761}
6762
Ville Syrjälä616bc822015-01-23 21:04:25 +02006763int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
6764{
Akash Goel80b6dda2015-03-06 11:07:15 +05306765 if (IS_GEN9(dev_priv->dev))
6766 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
6767 else if (IS_CHERRYVIEW(dev_priv->dev))
Ville Syrjälä616bc822015-01-23 21:04:25 +02006768 return chv_freq_opcode(dev_priv, val);
Deepak S22b1b2f2014-07-12 14:54:33 +05306769 else if (IS_VALLEYVIEW(dev_priv->dev))
Ville Syrjälä616bc822015-01-23 21:04:25 +02006770 return byt_freq_opcode(dev_priv, val);
6771 else
6772 return val / GT_FREQUENCY_MULTIPLIER;
Deepak S22b1b2f2014-07-12 14:54:33 +05306773}
6774
Chris Wilson6ad790c2015-04-07 16:20:31 +01006775struct request_boost {
6776 struct work_struct work;
6777 struct drm_i915_gem_request *rq;
6778};
6779
6780static void __intel_rps_boost_work(struct work_struct *work)
6781{
6782 struct request_boost *boost = container_of(work, struct request_boost, work);
6783
6784 if (!i915_gem_request_completed(boost->rq, true))
6785 gen6_rps_boost(to_i915(boost->rq->ring->dev));
6786
6787 i915_gem_request_unreference__unlocked(boost->rq);
6788 kfree(boost);
6789}
6790
6791void intel_queue_rps_boost_for_request(struct drm_device *dev,
6792 struct drm_i915_gem_request *rq)
6793{
6794 struct request_boost *boost;
6795
6796 if (rq == NULL || INTEL_INFO(dev)->gen < 6)
6797 return;
6798
6799 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
6800 if (boost == NULL)
6801 return;
6802
6803 i915_gem_request_reference(rq);
6804 boost->rq = rq;
6805
6806 INIT_WORK(&boost->work, __intel_rps_boost_work);
6807 queue_work(to_i915(dev)->wq, &boost->work);
6808}
6809
Daniel Vetterf742a552013-12-06 10:17:53 +01006810void intel_pm_setup(struct drm_device *dev)
Chris Wilson907b28c2013-07-19 20:36:52 +01006811{
6812 struct drm_i915_private *dev_priv = dev->dev_private;
6813
Daniel Vetterf742a552013-12-06 10:17:53 +01006814 mutex_init(&dev_priv->rps.hw_lock);
6815
Chris Wilson907b28c2013-07-19 20:36:52 +01006816 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6817 intel_gen6_powersave_work);
Paulo Zanoni5d584b22014-03-07 20:08:15 -03006818
Paulo Zanoni33688d92014-03-07 20:08:19 -03006819 dev_priv->pm.suspended = false;
Chris Wilson907b28c2013-07-19 20:36:52 +01006820}