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gerrit-public.fairphone.software / kernel / msm-5.4 / 18619ff55d613dc5c8276ae70e5ca4e48c609f44 / . / arch / arm / boot / dts / imx6ul.dtsi
blob: 70a11e395b9d2534a197b35143a7ba0cf7ae75e5 [file] [log] [blame]
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6ul-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include "imx6ul-pinfunc.h"
13#include "skeleton.dtsi"
14
15/ {
16 aliases {
Fugang Duan01f3dc72015-07-28 15:30:41 +0800[diff] [blame]17 ethernet0 = &fec1;
18 ethernet1 = &fec2;
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]19 gpio0 = &gpio1;
20 gpio1 = &gpio2;
21 gpio2 = &gpio3;
22 gpio3 = &gpio4;
23 gpio4 = &gpio5;
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 mmc0 = &usdhc1;
29 mmc1 = &usdhc2;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 serial6 = &uart7;
37 serial7 = &uart8;
38 spi0 = &ecspi1;
39 spi1 = &ecspi2;
40 spi2 = &ecspi3;
41 spi3 = &ecspi4;
42 usbphy0 = &usbphy1;
43 usbphy1 = &usbphy2;
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu0: cpu@0 {
51 compatible = "arm,cortex-a7";
52 device_type = "cpu";
53 reg = <0>;
54 clock-latency = <61036>; /* two CLK32 periods */
55 operating-points = <
56 /* kHz uV */
57 528000 1250000
58 396000 1150000
59 198000 1150000
60 >;
61 fsl,soc-operating-points = <
62 /* KHz uV */
63 528000 1250000
64 396000 1150000
65 198000 1150000
66 >;
67 clocks = <&clks IMX6UL_CLK_ARM>,
68 <&clks IMX6UL_CLK_PLL2_BUS>,
69 <&clks IMX6UL_CLK_PLL2_PFD2>,
70 <&clks IMX6UL_CA7_SECONDARY_SEL>,
71 <&clks IMX6UL_CLK_STEP>,
72 <&clks IMX6UL_CLK_PLL1_SW>,
73 <&clks IMX6UL_CLK_PLL1_SYS>,
74 <&clks IMX6UL_PLL1_BYPASS>,
75 <&clks IMX6UL_CLK_PLL1>,
76 <&clks IMX6UL_PLL1_BYPASS_SRC>,
77 <&clks IMX6UL_CLK_OSC>;
78 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
79 "secondary_sel", "step", "pll1_sw",
80 "pll1_sys", "pll1_bypass", "pll1",
81 "pll1_bypass_src", "osc";
82 arm-supply = <&reg_arm>;
83 soc-supply = <&reg_soc>;
84 };
85 };
86
87 intc: interrupt-controller@00a01000 {
88 compatible = "arm,cortex-a7-gic";
89 #interrupt-cells = <3>;
90 interrupt-controller;
91 reg = <0x00a01000 0x1000>,
92 <0x00a02000 0x1000>,
93 <0x00a04000 0x2000>,
94 <0x00a06000 0x2000>;
95 };
96
97 ckil: clock-cli {
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
100 clock-frequency = <32768>;
101 clock-output-names = "ckil";
102 };
103
104 osc: clock-osc {
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
107 clock-frequency = <24000000>;
108 clock-output-names = "osc";
109 };
110
111 ipp_di0: clock-di0 {
112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <0>;
115 clock-output-names = "ipp_di0";
116 };
117
118 ipp_di1: clock-di1 {
119 compatible = "fixed-clock";
120 #clock-cells = <0>;
121 clock-frequency = <0>;
122 clock-output-names = "ipp_di1";
123 };
124
125 soc {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "simple-bus";
Anson Huang18619ff2015-08-04 01:12:12 +0800[diff] [blame^]129 interrupt-parent = <&gpc>;
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]130 ranges;
131
132 pmu {
133 compatible = "arm,cortex-a7-pmu";
134 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
135 status = "disabled";
136 };
137
138 aips1: aips-bus@02000000 {
139 compatible = "fsl,aips-bus", "simple-bus";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 reg = <0x02000000 0x100000>;
143 ranges;
144
145 spba-bus@02000000 {
146 compatible = "fsl,spba-bus", "simple-bus";
147 #address-cells = <1>;
148 #size-cells = <1>;
149 reg = <0x02000000 0x40000>;
150 ranges;
151
152 ecspi1: ecspi@02008000 {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
156 reg = <0x02008000 0x4000>;
157 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clks IMX6UL_CLK_ECSPI1>,
159 <&clks IMX6UL_CLK_ECSPI1>;
160 clock-names = "ipg", "per";
161 status = "disabled";
162 };
163
164 ecspi2: ecspi@0200c000 {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
168 reg = <0x0200c000 0x4000>;
169 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&clks IMX6UL_CLK_ECSPI2>,
171 <&clks IMX6UL_CLK_ECSPI2>;
172 clock-names = "ipg", "per";
173 status = "disabled";
174 };
175
176 ecspi3: ecspi@02010000 {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
180 reg = <0x02010000 0x4000>;
181 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&clks IMX6UL_CLK_ECSPI3>,
183 <&clks IMX6UL_CLK_ECSPI3>;
184 clock-names = "ipg", "per";
185 status = "disabled";
186 };
187
188 ecspi4: ecspi@02014000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
192 reg = <0x02014000 0x4000>;
193 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&clks IMX6UL_CLK_ECSPI4>,
195 <&clks IMX6UL_CLK_ECSPI4>;
196 clock-names = "ipg", "per";
197 status = "disabled";
198 };
199
200 uart7: serial@02018000 {
201 compatible = "fsl,imx6ul-uart",
202 "fsl,imx6q-uart";
203 reg = <0x02018000 0x4000>;
204 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
206 <&clks IMX6UL_CLK_UART7_SERIAL>;
207 clock-names = "ipg", "per";
208 status = "disabled";
209 };
210
211 uart1: serial@02020000 {
212 compatible = "fsl,imx6ul-uart",
213 "fsl,imx6q-uart";
214 reg = <0x02020000 0x4000>;
215 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
217 <&clks IMX6UL_CLK_UART1_SERIAL>;
218 clock-names = "ipg", "per";
219 status = "disabled";
220 };
221
222 uart8: serial@02024000 {
223 compatible = "fsl,imx6ul-uart",
224 "fsl,imx6q-uart";
225 reg = <0x02024000 0x4000>;
226 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
228 <&clks IMX6UL_CLK_UART8_SERIAL>;
229 clock-names = "ipg", "per";
230 status = "disabled";
231 };
232 };
233
234 gpt1: gpt@02098000 {
235 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
236 reg = <0x02098000 0x4000>;
237 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
239 <&clks IMX6UL_CLK_GPT1_SERIAL>;
240 clock-names = "ipg", "per";
241 };
242
243 gpio1: gpio@0209c000 {
244 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
245 reg = <0x0209c000 0x4000>;
246 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
248 gpio-controller;
249 #gpio-cells = <2>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 };
253
254 gpio2: gpio@020a0000 {
255 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
256 reg = <0x020a0000 0x4000>;
257 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
259 gpio-controller;
260 #gpio-cells = <2>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
263 };
264
265 gpio3: gpio@020a4000 {
266 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
267 reg = <0x020a4000 0x4000>;
268 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
270 gpio-controller;
271 #gpio-cells = <2>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
274 };
275
276 gpio4: gpio@020a8000 {
277 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
278 reg = <0x020a8000 0x4000>;
279 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
281 gpio-controller;
282 #gpio-cells = <2>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 };
286
287 gpio5: gpio@020ac000 {
288 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
289 reg = <0x020ac000 0x4000>;
290 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
292 gpio-controller;
293 #gpio-cells = <2>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 };
297
Fugang Duan01f3dc72015-07-28 15:30:41 +0800[diff] [blame]298 fec2: ethernet@020b4000 {
299 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
300 reg = <0x020b4000 0x4000>;
301 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&clks IMX6UL_CLK_ENET>,
304 <&clks IMX6UL_CLK_ENET_AHB>,
305 <&clks IMX6UL_CLK_ENET_PTP>,
306 <&clks IMX6UL_CLK_ENET2_REF_125M>,
307 <&clks IMX6UL_CLK_ENET2_REF_125M>;
308 clock-names = "ipg", "ahb", "ptp",
309 "enet_clk_ref", "enet_out";
310 fsl,num-tx-queues=<1>;
311 fsl,num-rx-queues=<1>;
312 status = "disabled";
313 };
314
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]315 wdog1: wdog@020bc000 {
316 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
317 reg = <0x020bc000 0x4000>;
318 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clks IMX6UL_CLK_WDOG1>;
320 };
321
322 wdog2: wdog@020c0000 {
323 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
324 reg = <0x020c0000 0x4000>;
325 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&clks IMX6UL_CLK_WDOG2>;
327 status = "disabled";
328 };
329
330 clks: ccm@020c4000 {
331 compatible = "fsl,imx6ul-ccm";
332 reg = <0x020c4000 0x4000>;
333 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
335 #clock-cells = <1>;
336 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
337 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
338 };
339
340 anatop: anatop@020c8000 {
341 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
342 "syscon", "simple-bus";
343 reg = <0x020c8000 0x1000>;
344 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
347
348 reg_3p0: regulator-3p0@120 {
349 compatible = "fsl,anatop-regulator";
350 regulator-name = "vdd3p0";
351 regulator-min-microvolt = <2625000>;
352 regulator-max-microvolt = <3400000>;
353 anatop-reg-offset = <0x120>;
354 anatop-vol-bit-shift = <8>;
355 anatop-vol-bit-width = <5>;
356 anatop-min-bit-val = <0>;
357 anatop-min-voltage = <2625000>;
358 anatop-max-voltage = <3400000>;
359 anatop-enable-bit = <0>;
360 };
361
362 reg_arm: regulator-vddcore@140 {
363 compatible = "fsl,anatop-regulator";
364 regulator-name = "cpu";
365 regulator-min-microvolt = <725000>;
366 regulator-max-microvolt = <1450000>;
367 regulator-always-on;
368 anatop-reg-offset = <0x140>;
369 anatop-vol-bit-shift = <0>;
370 anatop-vol-bit-width = <5>;
371 anatop-delay-reg-offset = <0x170>;
372 anatop-delay-bit-shift = <24>;
373 anatop-delay-bit-width = <2>;
374 anatop-min-bit-val = <1>;
375 anatop-min-voltage = <725000>;
376 anatop-max-voltage = <1450000>;
377 };
378
379 reg_soc: regulator-vddsoc@140 {
380 compatible = "fsl,anatop-regulator";
381 regulator-name = "vddsoc";
382 regulator-min-microvolt = <725000>;
383 regulator-max-microvolt = <1450000>;
384 regulator-always-on;
385 anatop-reg-offset = <0x140>;
386 anatop-vol-bit-shift = <18>;
387 anatop-vol-bit-width = <5>;
388 anatop-delay-reg-offset = <0x170>;
389 anatop-delay-bit-shift = <28>;
390 anatop-delay-bit-width = <2>;
391 anatop-min-bit-val = <1>;
392 anatop-min-voltage = <725000>;
393 anatop-max-voltage = <1450000>;
394 };
395 };
396
397 usbphy1: usbphy@020c9000 {
398 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
399 reg = <0x020c9000 0x1000>;
400 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&clks IMX6UL_CLK_USBPHY1>;
402 phy-3p0-supply = <&reg_3p0>;
403 fsl,anatop = <&anatop>;
404 };
405
406 usbphy2: usbphy@020ca000 {
407 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
408 reg = <0x020ca000 0x1000>;
409 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clks IMX6UL_CLK_USBPHY2>;
411 phy-3p0-supply = <&reg_3p0>;
412 fsl,anatop = <&anatop>;
413 };
414
415 epit1: epit@020d0000 {
416 reg = <0x020d0000 0x4000>;
417 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
418 };
419
420 epit2: epit@020d4000 {
421 reg = <0x020d4000 0x4000>;
422 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
423 };
424
425 src: src@020d8000 {
426 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
427 reg = <0x020d8000 0x4000>;
428 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
430 #reset-cells = <1>;
431 };
432
433 gpc: gpc@020dc000 {
434 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
435 reg = <0x020dc000 0x4000>;
Anson Huang18619ff2015-08-04 01:12:12 +0800[diff] [blame^]436 interrupt-controller;
437 #interrupt-cells = <3>;
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]438 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
Anson Huang18619ff2015-08-04 01:12:12 +0800[diff] [blame^]439 interrupt-parent = <&intc>;
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]440 };
441
442 iomuxc: iomuxc@020e0000 {
443 compatible = "fsl,imx6ul-iomuxc";
444 reg = <0x020e0000 0x4000>;
445 };
446
447 gpr: iomuxc-gpr@020e4000 {
448 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
449 reg = <0x020e4000 0x4000>;
450 };
451
452 gpt2: gpt@020e8000 {
453 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
454 reg = <0x020e8000 0x4000>;
455 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&clks IMX6UL_CLK_DUMMY>,
457 <&clks IMX6UL_CLK_DUMMY>;
458 clock-names = "ipg", "per";
459 };
460
461 pwm5: pwm@020f0000 {
462 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
463 reg = <0x020f0000 0x4000>;
464 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&clks IMX6UL_CLK_DUMMY>,
466 <&clks IMX6UL_CLK_DUMMY>;
467 clock-names = "ipg", "per";
468 #pwm-cells = <2>;
469 };
470
471 pwm6: pwm@020f4000 {
472 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
473 reg = <0x020f4000 0x4000>;
474 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clks IMX6UL_CLK_DUMMY>,
476 <&clks IMX6UL_CLK_DUMMY>;
477 clock-names = "ipg", "per";
478 #pwm-cells = <2>;
479 };
480
481 pwm7: pwm@020f8000 {
482 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
483 reg = <0x020f8000 0x4000>;
484 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clks IMX6UL_CLK_DUMMY>,
486 <&clks IMX6UL_CLK_DUMMY>;
487 clock-names = "ipg", "per";
488 #pwm-cells = <2>;
489 };
490
491 pwm8: pwm@020fc000 {
492 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
493 reg = <0x020fc000 0x4000>;
494 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&clks IMX6UL_CLK_DUMMY>,
496 <&clks IMX6UL_CLK_DUMMY>;
497 clock-names = "ipg", "per";
498 #pwm-cells = <2>;
499 };
500 };
501
502 aips2: aips-bus@02100000 {
503 compatible = "fsl,aips-bus", "simple-bus";
504 #address-cells = <1>;
505 #size-cells = <1>;
506 reg = <0x02100000 0x100000>;
507 ranges;
508
Frank Licad2cb62015-07-17 04:03:16 +0800[diff] [blame]509 usbotg1: usb@02184000 {
510 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
511 reg = <0x02184000 0x200>;
512 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&clks IMX6UL_CLK_USBOH3>;
514 fsl,usbphy = <&usbphy1>;
515 fsl,usbmisc = <&usbmisc 0>;
516 fsl,anatop = <&anatop>;
517 status = "disabled";
518 };
519
520 usbotg2: usb@02184200 {
521 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
522 reg = <0x02184200 0x200>;
523 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&clks IMX6UL_CLK_USBOH3>;
525 fsl,usbphy = <&usbphy2>;
526 fsl,usbmisc = <&usbmisc 1>;
527 status = "disabled";
528 };
529
530 usbmisc: usbmisc@02184800 {
531 #index-cells = <1>;
532 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
533 reg = <0x02184800 0x200>;
534 };
535
Fugang Duan01f3dc72015-07-28 15:30:41 +0800[diff] [blame]536 fec1: ethernet@02188000 {
537 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
538 reg = <0x02188000 0x4000>;
539 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&clks IMX6UL_CLK_ENET>,
542 <&clks IMX6UL_CLK_ENET_AHB>,
543 <&clks IMX6UL_CLK_ENET_PTP>,
544 <&clks IMX6UL_CLK_ENET_REF>,
545 <&clks IMX6UL_CLK_ENET_REF>;
546 clock-names = "ipg", "ahb", "ptp",
547 "enet_clk_ref", "enet_out";
548 fsl,num-tx-queues=<1>;
549 fsl,num-rx-queues=<1>;
550 status = "disabled";
551 };
552
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]553 usdhc1: usdhc@02190000 {
554 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
555 reg = <0x02190000 0x4000>;
556 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&clks IMX6UL_CLK_USDHC1>,
558 <&clks IMX6UL_CLK_USDHC1>,
559 <&clks IMX6UL_CLK_USDHC1>;
560 clock-names = "ipg", "ahb", "per";
561 bus-width = <4>;
562 status = "disabled";
563 };
564
565 usdhc2: usdhc@02194000 {
566 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
567 reg = <0x02194000 0x4000>;
568 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&clks IMX6UL_CLK_USDHC2>,
570 <&clks IMX6UL_CLK_USDHC2>,
571 <&clks IMX6UL_CLK_USDHC2>;
572 clock-names = "ipg", "ahb", "per";
573 bus-width = <4>;
574 status = "disabled";
575 };
576
577 i2c1: i2c@021a0000 {
578 #address-cells = <1>;
579 #size-cells = <0>;
580 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
581 reg = <0x021a0000 0x4000>;
582 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&clks IMX6UL_CLK_I2C1>;
584 status = "disabled";
585 };
586
587 i2c2: i2c@021a4000 {
588 #address-cells = <1>;
589 #size-cells = <0>;
590 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
591 reg = <0x021a4000 0x4000>;
592 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&clks IMX6UL_CLK_I2C2>;
594 status = "disabled";
595 };
596
597 i2c3: i2c@021a8000 {
598 #address-cells = <1>;
599 #size-cells = <0>;
600 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
601 reg = <0x021a8000 0x4000>;
602 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&clks IMX6UL_CLK_I2C3>;
604 status = "disabled";
605 };
606
Frank Li5ff807a2015-07-21 03:33:53 +0800[diff] [blame]607 qspi: qspi@021e0000 {
608 #address-cells = <1>;
609 #size-cells = <0>;
610 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
611 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
612 reg-names = "QuadSPI", "QuadSPI-memory";
613 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&clks IMX6UL_CLK_QSPI>,
615 <&clks IMX6UL_CLK_QSPI>;
616 clock-names = "qspi_en", "qspi";
617 status = "disabled";
618 };
619
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]620 uart2: serial@021e8000 {
621 compatible = "fsl,imx6ul-uart",
622 "fsl,imx6q-uart";
623 reg = <0x021e8000 0x4000>;
624 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
626 <&clks IMX6UL_CLK_UART2_SERIAL>;
627 clock-names = "ipg", "per";
628 status = "disabled";
629 };
630
631 uart3: serial@021ec000 {
632 compatible = "fsl,imx6ul-uart",
633 "fsl,imx6q-uart";
634 reg = <0x021ec000 0x4000>;
635 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
637 <&clks IMX6UL_CLK_UART3_SERIAL>;
638 clock-names = "ipg", "per";
639 status = "disabled";
640 };
641
642 uart4: serial@021f0000 {
643 compatible = "fsl,imx6ul-uart",
644 "fsl,imx6q-uart";
645 reg = <0x021f0000 0x4000>;
646 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
648 <&clks IMX6UL_CLK_UART4_SERIAL>;
649 clock-names = "ipg", "per";
650 status = "disabled";
651 };
652
653 uart5: serial@021f4000 {
654 compatible = "fsl,imx6ul-uart",
655 "fsl,imx6q-uart";
656 reg = <0x021f4000 0x4000>;
657 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
659 <&clks IMX6UL_CLK_UART5_SERIAL>;
660 clock-names = "ipg", "per";
661 status = "disabled";
662 };
663
664 i2c4: i2c@021f8000 {
665 #address-cells = <1>;
666 #size-cells = <0>;
667 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
668 reg = <0x021f8000 0x4000>;
669 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clks IMX6UL_CLK_I2C4>;
671 status = "disabled";
672 };
673
674 uart6: serial@021fc000 {
675 compatible = "fsl,imx6ul-uart",
676 "fsl,imx6q-uart";
677 reg = <0x021fc000 0x4000>;
678 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
680 <&clks IMX6UL_CLK_UART6_SERIAL>;
681 clock-names = "ipg", "per";
682 status = "disabled";
683 };
684 };
685 };
686};