blob: 7a5713df54b34e45d2c1581070618d3fb68ba41f [file] [log] [blame]
Paul Walmsley543d9372008-03-18 10:22:06 +02001/*
2 * linux/arch/arm/mach-omap2/clock.c
3 *
Tony Lindgrena16e9702008-03-18 11:56:39 +02004 * Copyright (C) 2005-2008 Texas Instruments, Inc.
Paul Walmsley8c349742010-02-22 22:09:24 -07005 * Copyright (C) 2004-2010 Nokia Corporation
Tony Lindgrena16e9702008-03-18 11:56:39 +02006 *
7 * Contacts:
Paul Walmsley543d9372008-03-18 10:22:06 +02008 * Richard Woodruff <r-woodruff2@ti.com>
Paul Walmsley543d9372008-03-18 10:22:06 +02009 * Paul Walmsley
10 *
Paul Walmsley543d9372008-03-18 10:22:06 +020011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15#undef DEBUG
16
Paul Walmsley543d9372008-03-18 10:22:06 +020017#include <linux/kernel.h>
Paul Walmsley1fe9be82012-09-27 10:33:33 -060018#include <linux/export.h>
Paul Walmsley543d9372008-03-18 10:22:06 +020019#include <linux/list.h>
20#include <linux/errno.h>
Paul Walmsley4d30e822010-02-22 22:09:36 -070021#include <linux/err.h>
22#include <linux/delay.h>
Mike Turquette32cc0022012-11-10 16:58:41 -070023#include <linux/clk-provider.h>
Russell Kingfced80c2008-09-06 12:10:45 +010024#include <linux/io.h>
Russell Kingfbd3bdb2008-09-06 12:13:59 +010025#include <linux/bitops.h>
Tero Kristo80cbb222015-02-06 16:00:32 +020026#include <linux/regmap.h>
Tero Kristo9f029b12014-10-22 15:15:36 +030027#include <linux/of_address.h>
Tero Kristo80cbb222015-02-06 16:00:32 +020028#include <linux/bootmem.h>
Jean Pihet5e7c58d2011-03-03 11:25:43 +010029#include <asm/cpu.h>
Tony Lindgrendbc04162012-08-31 10:59:07 -070030
Tony Lindgrendbc04162012-08-31 10:59:07 -070031#include <trace/events/power.h>
32
33#include "soc.h"
34#include "clockdomain.h"
Paul Walmsley543d9372008-03-18 10:22:06 +020035#include "clock.h"
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -060036#include "cm.h"
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -060037#include "cm2xxx.h"
38#include "cm3xxx.h"
Paul Walmsley543d9372008-03-18 10:22:06 +020039#include "cm-regbits-24xx.h"
40#include "cm-regbits-34xx.h"
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -060041#include "common.h"
42
43/*
44 * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait
45 * for a module to indicate that it is no longer in idle
46 */
47#define MAX_MODULE_ENABLE_WAIT 100000
Paul Walmsley543d9372008-03-18 10:22:06 +020048
Afzal Mohammed99541192011-12-13 10:46:43 -080049u16 cpu_mask;
Paul Walmsley543d9372008-03-18 10:22:06 +020050
Tero Kristoa24886e2014-07-02 11:47:40 +030051/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
52#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
53#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
54#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
55#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
56
57/*
58 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
59 * From device data manual section 4.3 "DPLL and DLL Specifications".
60 */
61#define OMAP3PLUS_DPLL_FINT_MIN 32000
62#define OMAP3PLUS_DPLL_FINT_MAX 52000000
63
Tero Kristo8111e012014-07-02 11:47:39 +030064/*
Paul Walmsley12706c52011-07-10 05:57:06 -060065 * clkdm_control: if true, then when a clock is enabled in the
66 * hardware, its clockdomain will first be enabled; and when a clock
67 * is disabled in the hardware, its clockdomain will be disabled
68 * afterwards.
69 */
70static bool clkdm_control = true;
71
Tero Kristo80cbb222015-02-06 16:00:32 +020072struct clk_iomap {
73 struct regmap *regmap;
74 void __iomem *mem;
75};
76
77static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
Tero Kristo9f029b12014-10-22 15:15:36 +030078
79static void clk_memmap_writel(u32 val, void __iomem *reg)
80{
81 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
Tero Kristo80cbb222015-02-06 16:00:32 +020082 struct clk_iomap *io = clk_memmaps[r->index];
Tero Kristo9f029b12014-10-22 15:15:36 +030083
Tero Kristo80cbb222015-02-06 16:00:32 +020084 if (io->regmap)
85 regmap_write(io->regmap, r->offset, val);
86 else
87 writel_relaxed(val, io->mem + r->offset);
Tero Kristo9f029b12014-10-22 15:15:36 +030088}
89
90static u32 clk_memmap_readl(void __iomem *reg)
91{
Tero Kristo80cbb222015-02-06 16:00:32 +020092 u32 val;
Tero Kristo9f029b12014-10-22 15:15:36 +030093 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
Tero Kristo80cbb222015-02-06 16:00:32 +020094 struct clk_iomap *io = clk_memmaps[r->index];
Tero Kristo9f029b12014-10-22 15:15:36 +030095
Tero Kristo80cbb222015-02-06 16:00:32 +020096 if (io->regmap)
97 regmap_read(io->regmap, r->offset, &val);
98 else
99 val = readl_relaxed(io->mem + r->offset);
100
101 return val;
Tero Kristo9f029b12014-10-22 15:15:36 +0300102}
Tero Kristo3ada6b102013-10-22 11:47:08 +0300103
104void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
105{
Tero Kristo9f029b12014-10-22 15:15:36 +0300106 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
Tero Kristo3ada6b102013-10-22 11:47:08 +0300107 writel_relaxed(val, reg);
Tero Kristo9f029b12014-10-22 15:15:36 +0300108 else
109 clk_memmap_writel(val, reg);
Tero Kristo3ada6b102013-10-22 11:47:08 +0300110}
111
112u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
113{
Tero Kristo9f029b12014-10-22 15:15:36 +0300114 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
115 return readl_relaxed(reg);
116 else
117 return clk_memmap_readl(reg);
118}
Tero Kristo3ada6b102013-10-22 11:47:08 +0300119
Tero Kristo9f029b12014-10-22 15:15:36 +0300120static struct ti_clk_ll_ops omap_clk_ll_ops = {
121 .clk_readl = clk_memmap_readl,
122 .clk_writel = clk_memmap_writel,
Tero Kristo9a356d62015-03-03 11:14:31 +0200123 .clkdm_clk_enable = clkdm_clk_enable,
124 .clkdm_clk_disable = clkdm_clk_disable,
Tero Kristo192383d2015-03-03 13:47:08 +0200125 .cm_wait_module_ready = omap_cm_wait_module_ready,
126 .cm_split_idlest_reg = cm_split_idlest_reg,
Tero Kristo9f029b12014-10-22 15:15:36 +0300127};
Tero Kristo3ada6b102013-10-22 11:47:08 +0300128
Tero Kristo9f029b12014-10-22 15:15:36 +0300129/**
130 * omap2_clk_provider_init - initialize a clock provider
131 * @match_table: DT device table to match for devices to init
132 * @np: device node pointer for the this clock provider
133 * @index: index for the clock provider
Tero Kristo80cbb222015-02-06 16:00:32 +0200134 + @syscon: syscon regmap pointer
135 * @mem: iomem pointer for the clock provider memory area, only used if
136 * syscon is not provided
Tero Kristo9f029b12014-10-22 15:15:36 +0300137 *
138 * Initializes a clock provider module (CM/PRM etc.), registering
139 * the memory mapping at specified index and initializing the
140 * low level driver infrastructure. Returns 0 in success.
141 */
142int __init omap2_clk_provider_init(struct device_node *np, int index,
Tero Kristo80cbb222015-02-06 16:00:32 +0200143 struct regmap *syscon, void __iomem *mem)
Tero Kristo9f029b12014-10-22 15:15:36 +0300144{
Tero Kristo80cbb222015-02-06 16:00:32 +0200145 struct clk_iomap *io;
146
Tero Kristo9f029b12014-10-22 15:15:36 +0300147 ti_clk_ll_ops = &omap_clk_ll_ops;
148
Tero Kristo80cbb222015-02-06 16:00:32 +0200149 io = kzalloc(sizeof(*io), GFP_KERNEL);
150
151 io->regmap = syscon;
152 io->mem = mem;
153
154 clk_memmaps[index] = io;
Tero Kristo9f029b12014-10-22 15:15:36 +0300155
156 ti_dt_clk_init_provider(np, index);
157
158 return 0;
159}
160
161/**
162 * omap2_clk_legacy_provider_init - initialize a legacy clock provider
163 * @index: index for the clock provider
164 * @mem: iomem pointer for the clock provider memory area
165 *
166 * Initializes a legacy clock provider memory mapping.
167 */
168void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem)
169{
Tero Kristo80cbb222015-02-06 16:00:32 +0200170 struct clk_iomap *io;
171
Tero Kristo9f029b12014-10-22 15:15:36 +0300172 ti_clk_ll_ops = &omap_clk_ll_ops;
173
Tero Kristo80cbb222015-02-06 16:00:32 +0200174 io = memblock_virt_alloc(sizeof(*io), 0);
175
176 io->mem = mem;
177
178 clk_memmaps[index] = io;
Tero Kristo3ada6b102013-10-22 11:47:08 +0300179}
Mike Turquette32cc0022012-11-10 16:58:41 -0700180
181/*
Paul Walmsley30962d92010-02-22 22:09:38 -0700182 * OMAP2+ specific clock functions
183 */
Paul Walmsley543d9372008-03-18 10:22:06 +0200184
Paul Walmsley4b1f76e2010-01-26 20:13:04 -0700185/* Private functions */
186
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600187
188/**
189 * _wait_idlest_generic - wait for a module to leave the idle state
Tero Kristo519ab8b2013-10-22 11:49:58 +0300190 * @clk: module clock to wait for (needed for register offsets)
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600191 * @reg: virtual address of module IDLEST register
192 * @mask: value to mask against to determine if the module is active
193 * @idlest: idle state indicator (0 or 1) for the clock
194 * @name: name of the clock (for printk)
195 *
196 * Wait for a module to leave idle, where its idle-status register is
197 * not inside the CM module. Returns 1 if the module left idle
198 * promptly, or 0 if the module did not leave idle before the timeout
199 * elapsed. XXX Deprecated - should be moved into drivers for the
200 * individual IP block that the IDLEST register exists in.
201 */
Tero Kristo519ab8b2013-10-22 11:49:58 +0300202static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg,
203 u32 mask, u8 idlest, const char *name)
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600204{
205 int i = 0, ena = 0;
206
207 ena = (idlest) ? 0 : mask;
208
Tero Kristo519ab8b2013-10-22 11:49:58 +0300209 omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena),
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600210 MAX_MODULE_ENABLE_WAIT, i);
211
212 if (i < MAX_MODULE_ENABLE_WAIT)
213 pr_debug("omap clock: module associated with clock %s ready after %d loops\n",
214 name, i);
215 else
216 pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n",
217 name, MAX_MODULE_ENABLE_WAIT);
218
219 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
220};
221
Paul Walmsley4b1f76e2010-01-26 20:13:04 -0700222/**
223 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
224 * @clk: struct clk * belonging to the module
225 *
226 * If the necessary clocks for the OMAP hardware IP block that
227 * corresponds to clock @clk are enabled, then wait for the module to
228 * indicate readiness (i.e., to leave IDLE). This code does not
229 * belong in the clock code and will be moved in the medium term to
230 * module-dependent code. No return value.
231 */
Mike Turquette32cc0022012-11-10 16:58:41 -0700232static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
Paul Walmsley4b1f76e2010-01-26 20:13:04 -0700233{
234 void __iomem *companion_reg, *idlest_reg;
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600235 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id;
236 s16 prcm_mod;
237 int r;
Paul Walmsley4b1f76e2010-01-26 20:13:04 -0700238
239 /* Not all modules have multiple clocks that their IDLEST depends on */
240 if (clk->ops->find_companion) {
241 clk->ops->find_companion(clk, &companion_reg, &other_bit);
Tero Kristo519ab8b2013-10-22 11:49:58 +0300242 if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit)))
Paul Walmsley4b1f76e2010-01-26 20:13:04 -0700243 return;
244 }
245
Ranjith Lohithakshan419cc972010-02-24 12:05:54 -0700246 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600247 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);
248 if (r) {
249 /* IDLEST register not in the CM module */
Tero Kristo519ab8b2013-10-22 11:49:58 +0300250 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit),
251 idlest_val, __clk_get_name(clk->hw.clk));
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600252 } else {
Tero Kristo021b6ff2014-10-27 08:39:23 -0700253 omap_cm_wait_module_ready(0, prcm_mod, idlest_reg_id,
254 idlest_bit);
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600255 };
Paul Walmsley4b1f76e2010-01-26 20:13:04 -0700256}
257
Paul Walmsley4b1f76e2010-01-26 20:13:04 -0700258/* Public functions */
259
Paul Walmsley543d9372008-03-18 10:22:06 +0200260/**
Paul Walmsley333943b2008-08-19 11:08:45 +0300261 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
262 * @clk: OMAP clock struct ptr to use
263 *
264 * Convert a clockdomain name stored in a struct clk 'clk' into a
265 * clockdomain pointer, and save it into the struct clk. Intended to be
266 * called during clk_register(). No return value.
267 */
Mike Turquette32cc0022012-11-10 16:58:41 -0700268void omap2_init_clk_clkdm(struct clk_hw *hw)
269{
270 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
Paul Walmsley333943b2008-08-19 11:08:45 +0300271 struct clockdomain *clkdm;
Rajendra Nayak5dcc3b92012-09-22 02:24:17 -0600272 const char *clk_name;
Paul Walmsley333943b2008-08-19 11:08:45 +0300273
274 if (!clk->clkdm_name)
275 return;
276
Mike Turquette32cc0022012-11-10 16:58:41 -0700277 clk_name = __clk_get_name(hw->clk);
Rajendra Nayak5dcc3b92012-09-22 02:24:17 -0600278
Paul Walmsley333943b2008-08-19 11:08:45 +0300279 clkdm = clkdm_lookup(clk->clkdm_name);
280 if (clkdm) {
281 pr_debug("clock: associated clk %s to clkdm %s\n",
Rajendra Nayak5dcc3b92012-09-22 02:24:17 -0600282 clk_name, clk->clkdm_name);
Paul Walmsley333943b2008-08-19 11:08:45 +0300283 clk->clkdm = clkdm;
284 } else {
Paul Walmsley7852ec02012-07-26 00:54:26 -0600285 pr_debug("clock: could not associate clk %s to clkdm %s\n",
Rajendra Nayak5dcc3b92012-09-22 02:24:17 -0600286 clk_name, clk->clkdm_name);
Paul Walmsley333943b2008-08-19 11:08:45 +0300287 }
288}
289
290/**
Paul Walmsley12706c52011-07-10 05:57:06 -0600291 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
292 *
293 * Prevent the OMAP clock code from calling into the clockdomain code
294 * when a hardware clock in that clockdomain is enabled or disabled.
295 * Intended to be called at init time from omap*_clk_init(). No
296 * return value.
297 */
298void __init omap2_clk_disable_clkdm_control(void)
299{
300 clkdm_control = false;
301}
302
303/**
Paul Walmsley72350b22009-07-24 19:44:03 -0600304 * omap2_clk_dflt_find_companion - find companion clock to @clk
305 * @clk: struct clk * to find the companion clock of
306 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
307 * @other_bit: u8 ** to return the companion clock bit shift in
Paul Walmsley543d9372008-03-18 10:22:06 +0200308 *
Paul Walmsley72350b22009-07-24 19:44:03 -0600309 * Note: We don't need special code here for INVERT_ENABLE for the
310 * time being since INVERT_ENABLE only applies to clocks enabled by
Paul Walmsley543d9372008-03-18 10:22:06 +0200311 * CM_CLKEN_PLL
Paul Walmsley72350b22009-07-24 19:44:03 -0600312 *
313 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
314 * just a matter of XORing the bits.
315 *
316 * Some clocks don't have companion clocks. For example, modules with
317 * only an interface clock (such as MAILBOXES) don't have a companion
318 * clock. Right now, this code relies on the hardware exporting a bit
319 * in the correct companion register that indicates that the
320 * nonexistent 'companion clock' is active. Future patches will
321 * associate this type of code with per-module data structures to
322 * avoid this issue, and remove the casts. No return value.
Paul Walmsley543d9372008-03-18 10:22:06 +0200323 */
Mike Turquette32cc0022012-11-10 16:58:41 -0700324void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
Mike Turquette32cc0022012-11-10 16:58:41 -0700325 void __iomem **other_reg, u8 *other_bit)
Paul Walmsley543d9372008-03-18 10:22:06 +0200326{
Paul Walmsley72350b22009-07-24 19:44:03 -0600327 u32 r;
Paul Walmsley543d9372008-03-18 10:22:06 +0200328
Russell Kingc1168dc2008-11-04 21:24:00 +0000329 /*
330 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
331 * it's just a matter of XORing the bits.
332 */
Paul Walmsley72350b22009-07-24 19:44:03 -0600333 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
Paul Walmsley543d9372008-03-18 10:22:06 +0200334
Paul Walmsley72350b22009-07-24 19:44:03 -0600335 *other_reg = (__force void __iomem *)r;
336 *other_bit = clk->enable_bit;
Paul Walmsley543d9372008-03-18 10:22:06 +0200337}
338
Paul Walmsley72350b22009-07-24 19:44:03 -0600339/**
340 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
341 * @clk: struct clk * to find IDLEST info for
342 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
Ranjith Lohithakshan419cc972010-02-24 12:05:54 -0700343 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in
344 * @idlest_val: u8 * to return the idle status indicator
Paul Walmsley72350b22009-07-24 19:44:03 -0600345 *
346 * Return the CM_IDLEST register address and bit shift corresponding
347 * to the module that "owns" this clock. This default code assumes
348 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
349 * the IDLEST register address ID corresponds to the CM_*CLKEN
350 * register address ID (e.g., that CM_FCLKEN2 corresponds to
351 * CM_IDLEST2). This is not true for all modules. No return value.
352 */
Mike Turquette32cc0022012-11-10 16:58:41 -0700353void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
Mike Turquette32cc0022012-11-10 16:58:41 -0700354 void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val)
Paul Walmsley72350b22009-07-24 19:44:03 -0600355{
356 u32 r;
357
358 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
359 *idlest_reg = (__force void __iomem *)r;
360 *idlest_bit = clk->enable_bit;
Ranjith Lohithakshan419cc972010-02-24 12:05:54 -0700361
362 /*
363 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
364 * 34xx reverses this, just to keep us on our toes
365 * AM35xx uses both, depending on the module.
366 */
Tero Kristof3b19aa2015-02-27 17:54:14 +0200367 *idlest_val = ti_clk_get_features()->cm_idlest_val;
Paul Walmsley72350b22009-07-24 19:44:03 -0600368}
369
Mike Turquette32cc0022012-11-10 16:58:41 -0700370/**
371 * omap2_dflt_clk_enable - enable a clock in the hardware
372 * @hw: struct clk_hw * of the clock to enable
373 *
374 * Enable the clock @hw in the hardware. We first call into the OMAP
375 * clockdomain code to "enable" the corresponding clockdomain if this
376 * is the first enabled user of the clockdomain. Then program the
377 * hardware to enable the clock. Then wait for the IP block that uses
378 * this clock to leave idle (if applicable). Returns the error value
379 * from clkdm_clk_enable() if it terminated with an error, or -EINVAL
380 * if @hw has a null clock enable_reg, or zero upon success.
381 */
382int omap2_dflt_clk_enable(struct clk_hw *hw)
383{
384 struct clk_hw_omap *clk;
385 u32 v;
386 int ret = 0;
387
388 clk = to_clk_hw_omap(hw);
389
390 if (clkdm_control && clk->clkdm) {
391 ret = clkdm_clk_enable(clk->clkdm, hw->clk);
392 if (ret) {
393 WARN(1, "%s: could not enable %s's clockdomain %s: %d\n",
394 __func__, __clk_get_name(hw->clk),
395 clk->clkdm->name, ret);
396 return ret;
397 }
398 }
399
400 if (unlikely(clk->enable_reg == NULL)) {
401 pr_err("%s: %s missing enable_reg\n", __func__,
402 __clk_get_name(hw->clk));
403 ret = -EINVAL;
404 goto err;
405 }
406
407 /* FIXME should not have INVERT_ENABLE bit here */
Tero Kristo519ab8b2013-10-22 11:49:58 +0300408 v = omap2_clk_readl(clk, clk->enable_reg);
Mike Turquette32cc0022012-11-10 16:58:41 -0700409 if (clk->flags & INVERT_ENABLE)
410 v &= ~(1 << clk->enable_bit);
411 else
412 v |= (1 << clk->enable_bit);
Tero Kristo519ab8b2013-10-22 11:49:58 +0300413 omap2_clk_writel(v, clk, clk->enable_reg);
414 v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */
Mike Turquette32cc0022012-11-10 16:58:41 -0700415
416 if (clk->ops && clk->ops->find_idlest)
417 _omap2_module_wait_ready(clk);
418
419 return 0;
420
421err:
422 if (clkdm_control && clk->clkdm)
423 clkdm_clk_disable(clk->clkdm, hw->clk);
424 return ret;
425}
426
427/**
428 * omap2_dflt_clk_disable - disable a clock in the hardware
429 * @hw: struct clk_hw * of the clock to disable
430 *
431 * Disable the clock @hw in the hardware, and call into the OMAP
432 * clockdomain code to "disable" the corresponding clockdomain if all
433 * clocks/hwmods in that clockdomain are now disabled. No return
434 * value.
435 */
436void omap2_dflt_clk_disable(struct clk_hw *hw)
437{
438 struct clk_hw_omap *clk;
439 u32 v;
440
441 clk = to_clk_hw_omap(hw);
442 if (!clk->enable_reg) {
443 /*
444 * 'independent' here refers to a clock which is not
445 * controlled by its parent.
446 */
447 pr_err("%s: independent clock %s has no enable_reg\n",
448 __func__, __clk_get_name(hw->clk));
449 return;
450 }
451
Tero Kristo519ab8b2013-10-22 11:49:58 +0300452 v = omap2_clk_readl(clk, clk->enable_reg);
Mike Turquette32cc0022012-11-10 16:58:41 -0700453 if (clk->flags & INVERT_ENABLE)
454 v |= (1 << clk->enable_bit);
455 else
456 v &= ~(1 << clk->enable_bit);
Tero Kristo519ab8b2013-10-22 11:49:58 +0300457 omap2_clk_writel(v, clk, clk->enable_reg);
Mike Turquette32cc0022012-11-10 16:58:41 -0700458 /* No OCP barrier needed here since it is a disable operation */
459
460 if (clkdm_control && clk->clkdm)
461 clkdm_clk_disable(clk->clkdm, hw->clk);
462}
463
464/**
465 * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw
466 * @hw: struct clk_hw * of the clock being enabled
467 *
468 * Increment the usecount of the clockdomain of the clock pointed to
469 * by @hw; if the usecount is 1, the clockdomain will be "enabled."
470 * Only needed for clocks that don't use omap2_dflt_clk_enable() as
471 * their enable function pointer. Passes along the return value of
472 * clkdm_clk_enable(), -EINVAL if @hw is not associated with a
473 * clockdomain, or 0 if clock framework-based clockdomain control is
474 * not implemented.
475 */
476int omap2_clkops_enable_clkdm(struct clk_hw *hw)
477{
478 struct clk_hw_omap *clk;
479 int ret = 0;
480
481 clk = to_clk_hw_omap(hw);
482
483 if (unlikely(!clk->clkdm)) {
484 pr_err("%s: %s: no clkdm set ?!\n", __func__,
485 __clk_get_name(hw->clk));
486 return -EINVAL;
487 }
488
489 if (unlikely(clk->enable_reg))
490 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__,
491 __clk_get_name(hw->clk));
492
493 if (!clkdm_control) {
494 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
495 __func__, __clk_get_name(hw->clk));
496 return 0;
497 }
498
499 ret = clkdm_clk_enable(clk->clkdm, hw->clk);
500 WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n",
501 __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret);
502
503 return ret;
504}
505
506/**
507 * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw
508 * @hw: struct clk_hw * of the clock being disabled
509 *
510 * Decrement the usecount of the clockdomain of the clock pointed to
511 * by @hw; if the usecount is 0, the clockdomain will be "disabled."
512 * Only needed for clocks that don't use omap2_dflt_clk_disable() as their
513 * disable function pointer. No return value.
514 */
515void omap2_clkops_disable_clkdm(struct clk_hw *hw)
516{
517 struct clk_hw_omap *clk;
518
519 clk = to_clk_hw_omap(hw);
520
521 if (unlikely(!clk->clkdm)) {
522 pr_err("%s: %s: no clkdm set ?!\n", __func__,
523 __clk_get_name(hw->clk));
524 return;
525 }
526
527 if (unlikely(clk->enable_reg))
528 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__,
529 __clk_get_name(hw->clk));
530
531 if (!clkdm_control) {
532 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
533 __func__, __clk_get_name(hw->clk));
534 return;
535 }
536
537 clkdm_clk_disable(clk->clkdm, hw->clk);
538}
539
540/**
541 * omap2_dflt_clk_is_enabled - is clock enabled in the hardware?
542 * @hw: struct clk_hw * to check
543 *
544 * Return 1 if the clock represented by @hw is enabled in the
545 * hardware, or 0 otherwise. Intended for use in the struct
546 * clk_ops.is_enabled function pointer.
547 */
548int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
549{
550 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
551 u32 v;
552
Tero Kristo519ab8b2013-10-22 11:49:58 +0300553 v = omap2_clk_readl(clk, clk->enable_reg);
Mike Turquette32cc0022012-11-10 16:58:41 -0700554
555 if (clk->flags & INVERT_ENABLE)
556 v ^= BIT(clk->enable_bit);
557
558 v &= BIT(clk->enable_bit);
559
560 return v ? 1 : 0;
561}
562
563static int __initdata mpurate;
564
565/*
566 * By default we use the rate set by the bootloader.
567 * You can override this with mpurate= cmdline option.
568 */
569static int __init omap_clk_setup(char *str)
570{
571 get_option(&str, &mpurate);
572
573 if (!mpurate)
574 return 1;
575
576 if (mpurate < 1000)
577 mpurate *= 1000000;
578
579 return 1;
580}
581__setup("mpurate=", omap_clk_setup);
582
583const struct clk_hw_omap_ops clkhwops_wait = {
584 .find_idlest = omap2_clk_dflt_find_idlest,
585 .find_companion = omap2_clk_dflt_find_companion,
586};
Mike Turquette32cc0022012-11-10 16:58:41 -0700587
Paul Walmsley4d30e822010-02-22 22:09:36 -0700588/**
Paul Walmsley4d30e822010-02-22 22:09:36 -0700589 * omap2_clk_print_new_rates - print summary of current clock tree rates
590 * @hfclkin_ck_name: clk name for the off-chip HF oscillator
591 * @core_ck_name: clk name for the on-chip CORE_CLK
592 * @mpu_ck_name: clk name for the ARM MPU clock
593 *
594 * Prints a short message to the console with the HFCLKIN oscillator
595 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
596 * Called by the boot-time MPU rate switching code. XXX This is intended
597 * to be handled by the OPP layer code in the near future and should be
598 * removed from the clock code. No return value.
599 */
600void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
601 const char *core_ck_name,
602 const char *mpu_ck_name)
603{
604 struct clk *hfclkin_ck, *core_ck, *mpu_ck;
605 unsigned long hfclkin_rate;
606
607 mpu_ck = clk_get(NULL, mpu_ck_name);
608 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
609 return;
610
611 core_ck = clk_get(NULL, core_ck_name);
612 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
613 return;
614
615 hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
616 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
617 return;
618
619 hfclkin_rate = clk_get_rate(hfclkin_ck);
620
Paul Walmsley7852ec02012-07-26 00:54:26 -0600621 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
622 (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
Paul Walmsley4d30e822010-02-22 22:09:36 -0700623 (clk_get_rate(core_ck) / 1000000),
624 (clk_get_rate(mpu_ck) / 1000000));
625}
Tero Kristo8111e012014-07-02 11:47:39 +0300626
627/**
628 * ti_clk_init_features - init clock features struct for the SoC
629 *
630 * Initializes the clock features struct based on the SoC type.
631 */
632void __init ti_clk_init_features(void)
633{
Tero Kristof3b19aa2015-02-27 17:54:14 +0200634 struct ti_clk_features features = { 0 };
Tero Kristoa24886e2014-07-02 11:47:40 +0300635 /* Fint setup for DPLLs */
636 if (cpu_is_omap3430()) {
Tero Kristof3b19aa2015-02-27 17:54:14 +0200637 features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
638 features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
639 features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
640 features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
Tero Kristoa24886e2014-07-02 11:47:40 +0300641 } else {
Tero Kristof3b19aa2015-02-27 17:54:14 +0200642 features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
643 features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
Tero Kristoa24886e2014-07-02 11:47:40 +0300644 }
Tero Kristo512d91c2014-07-02 11:47:42 +0300645
646 /* Bypass value setup for DPLLs */
647 if (cpu_is_omap24xx()) {
Tero Kristof3b19aa2015-02-27 17:54:14 +0200648 features.dpll_bypass_vals |=
Tero Kristo512d91c2014-07-02 11:47:42 +0300649 (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
650 (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
651 } else if (cpu_is_omap34xx()) {
Tero Kristof3b19aa2015-02-27 17:54:14 +0200652 features.dpll_bypass_vals |=
Tero Kristo512d91c2014-07-02 11:47:42 +0300653 (1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
654 (1 << OMAP3XXX_EN_DPLL_FRBYPASS);
655 } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
656 soc_is_omap54xx() || soc_is_dra7xx()) {
Tero Kristof3b19aa2015-02-27 17:54:14 +0200657 features.dpll_bypass_vals |=
Tero Kristo512d91c2014-07-02 11:47:42 +0300658 (1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
659 (1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
660 (1 << OMAP4XXX_EN_DPLL_MNBYPASS);
661 }
Tero Kristo2337c5b2014-07-02 11:47:43 +0300662
663 /* Jitter correction only available on OMAP343X */
664 if (cpu_is_omap343x())
Tero Kristof3b19aa2015-02-27 17:54:14 +0200665 features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
Tero Kristo066edb22014-07-02 11:47:44 +0300666
667 /* Idlest value for interface clocks.
668 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
669 * 34xx reverses this, just to keep us on our toes
670 * AM35xx uses both, depending on the module.
671 */
672 if (cpu_is_omap24xx())
Tero Kristof3b19aa2015-02-27 17:54:14 +0200673 features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
Tero Kristo066edb22014-07-02 11:47:44 +0300674 else if (cpu_is_omap34xx())
Tero Kristof3b19aa2015-02-27 17:54:14 +0200675 features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
Tero Kristof0d2f682014-10-03 16:57:10 +0300676
677 /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
678 if (omap_rev() == OMAP3430_REV_ES1_0)
Tero Kristof3b19aa2015-02-27 17:54:14 +0200679 features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
680
681 ti_clk_setup_features(&features);
Tero Kristo8111e012014-07-02 11:47:39 +0300682}