blob: 6442a717ec3bf7532477372b9fd74b5f8a92d167 [file] [log] [blame]
Andy Fleming2654d632006-08-18 18:04:34 -05001/*
2 * MPC8540 ADS Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13/ {
14 model = "MPC8540ADS";
Kumar Gala52094872007-02-17 16:04:23 -060015 compatible = "MPC8540ADS", "MPC85xxADS";
Andy Fleming2654d632006-08-18 18:04:34 -050016 #address-cells = <1>;
17 #size-cells = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -050018
19 cpus {
Andy Fleming2654d632006-08-18 18:04:34 -050020 #address-cells = <1>;
21 #size-cells = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -050022
23 PowerPC,8540@0 {
24 device_type = "cpu";
25 reg = <0>;
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <8000>; // L1, 32K
29 i-cache-size = <8000>; // L1, 32K
30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot
Andy Fleming2654d632006-08-18 18:04:34 -050033 };
34 };
35
36 memory {
37 device_type = "memory";
Andy Fleming2654d632006-08-18 18:04:34 -050038 reg = <00000000 08000000>; // 128M at 0x0
39 };
40
41 soc8540@e0000000 {
42 #address-cells = <1>;
43 #size-cells = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -050044 device_type = "soc";
45 ranges = <0 e0000000 00100000>;
46 reg = <e0000000 00100000>; // CCSRBAR 1M
47 bus-frequency = <0>;
48
Dave Jiang50cf6702007-05-10 10:03:05 -070049 memory-controller@2000 {
50 compatible = "fsl,8540-memory-controller";
51 reg = <2000 1000>;
52 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050053 interrupts = <12 2>;
Dave Jiang50cf6702007-05-10 10:03:05 -070054 };
55
56 l2-cache-controller@20000 {
57 compatible = "fsl,8540-l2-cache-controller";
58 reg = <20000 1000>;
59 cache-line-size = <20>; // 32 bytes
60 cache-size = <40000>; // L2, 256K
61 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050062 interrupts = <10 2>;
Dave Jiang50cf6702007-05-10 10:03:05 -070063 };
64
Andy Fleming2654d632006-08-18 18:04:34 -050065 i2c@3000 {
66 device_type = "i2c";
67 compatible = "fsl-i2c";
68 reg = <3000 100>;
Kumar Galab533f8a2007-07-03 02:35:35 -050069 interrupts = <2b 2>;
Kumar Gala52094872007-02-17 16:04:23 -060070 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -050071 dfsrr;
72 };
73
74 mdio@24520 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 device_type = "mdio";
78 compatible = "gianfar";
79 reg = <24520 20>;
Kumar Gala52094872007-02-17 16:04:23 -060080 phy0: ethernet-phy@0 {
81 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050082 interrupts = <5 1>;
Andy Fleming2654d632006-08-18 18:04:34 -050083 reg = <0>;
84 device_type = "ethernet-phy";
85 };
Kumar Gala52094872007-02-17 16:04:23 -060086 phy1: ethernet-phy@1 {
87 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050088 interrupts = <5 1>;
Andy Fleming2654d632006-08-18 18:04:34 -050089 reg = <1>;
90 device_type = "ethernet-phy";
91 };
Kumar Gala52094872007-02-17 16:04:23 -060092 phy3: ethernet-phy@3 {
93 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050094 interrupts = <7 1>;
Andy Flemingaa74a302006-08-21 14:29:28 -050095 reg = <3>;
Andy Fleming2654d632006-08-18 18:04:34 -050096 device_type = "ethernet-phy";
97 };
98 };
99
100 ethernet@24000 {
101 #address-cells = <1>;
102 #size-cells = <0>;
103 device_type = "network";
104 model = "TSEC";
105 compatible = "gianfar";
106 reg = <24000 1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500107 /*
108 * address is deprecated and will be removed
109 * in 2.6.25. Only recent versions of
110 * U-Boot support local-mac-address, however.
111 */
112 address = [ 00 00 00 00 00 00 ];
113 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Galab533f8a2007-07-03 02:35:35 -0500114 interrupts = <1d 2 1e 2 22 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600115 interrupt-parent = <&mpic>;
116 phy-handle = <&phy0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500117 };
118
119 ethernet@25000 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 device_type = "network";
123 model = "TSEC";
124 compatible = "gianfar";
125 reg = <25000 1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500126 /*
127 * address is deprecated and will be removed
128 * in 2.6.25. Only recent versions of
129 * U-Boot support local-mac-address, however.
130 */
131 address = [ 00 00 00 00 00 00 ];
132 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Galab533f8a2007-07-03 02:35:35 -0500133 interrupts = <23 2 24 2 28 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600134 interrupt-parent = <&mpic>;
135 phy-handle = <&phy1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500136 };
137
138 ethernet@26000 {
139 #address-cells = <1>;
140 #size-cells = <0>;
141 device_type = "network";
Andy Flemingaa74a302006-08-21 14:29:28 -0500142 model = "FEC";
Andy Fleming2654d632006-08-18 18:04:34 -0500143 compatible = "gianfar";
144 reg = <26000 1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500145 /*
146 * address is deprecated and will be removed
147 * in 2.6.25. Only recent versions of
148 * U-Boot support local-mac-address, however.
149 */
150 address = [ 00 00 00 00 00 00 ];
151 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Galab533f8a2007-07-03 02:35:35 -0500152 interrupts = <29 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600153 interrupt-parent = <&mpic>;
154 phy-handle = <&phy3>;
Andy Fleming2654d632006-08-18 18:04:34 -0500155 };
156
157 serial@4500 {
158 device_type = "serial";
159 compatible = "ns16550";
160 reg = <4500 100>; // reg base, size
161 clock-frequency = <0>; // should we fill in in uboot?
Kumar Galab533f8a2007-07-03 02:35:35 -0500162 interrupts = <2a 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600163 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -0500164 };
165
166 serial@4600 {
167 device_type = "serial";
168 compatible = "ns16550";
169 reg = <4600 100>; // reg base, size
170 clock-frequency = <0>; // should we fill in in uboot?
Kumar Galab533f8a2007-07-03 02:35:35 -0500171 interrupts = <2a 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600172 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -0500173 };
Kumar Gala52094872007-02-17 16:04:23 -0600174 mpic: pic@40000 {
Andy Fleming2654d632006-08-18 18:04:34 -0500175 clock-frequency = <0>;
176 interrupt-controller;
177 #address-cells = <0>;
178 #interrupt-cells = <2>;
179 reg = <40000 40000>;
Andy Fleming2654d632006-08-18 18:04:34 -0500180 compatible = "chrp,open-pic";
181 device_type = "open-pic";
Andy Flemingaa74a302006-08-21 14:29:28 -0500182 big-endian;
Andy Fleming2654d632006-08-18 18:04:34 -0500183 };
184 };
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500185
186 pci@e0008000 {
187 interrupt-map-mask = <f800 0 0 7>;
188 interrupt-map = <
189
190 /* IDSEL 0x02 */
191 1000 0 0 1 &mpic 1 1
192 1000 0 0 2 &mpic 2 1
193 1000 0 0 3 &mpic 3 1
194 1000 0 0 4 &mpic 4 1
195
196 /* IDSEL 0x03 */
197 1800 0 0 1 &mpic 4 1
198 1800 0 0 2 &mpic 1 1
199 1800 0 0 3 &mpic 2 1
200 1800 0 0 4 &mpic 3 1
201
202 /* IDSEL 0x04 */
203 2000 0 0 1 &mpic 3 1
204 2000 0 0 2 &mpic 4 1
205 2000 0 0 3 &mpic 1 1
206 2000 0 0 4 &mpic 2 1
207
208 /* IDSEL 0x05 */
209 2800 0 0 1 &mpic 2 1
210 2800 0 0 2 &mpic 3 1
211 2800 0 0 3 &mpic 4 1
212 2800 0 0 4 &mpic 1 1
213
214 /* IDSEL 0x0c */
215 6000 0 0 1 &mpic 1 1
216 6000 0 0 2 &mpic 2 1
217 6000 0 0 3 &mpic 3 1
218 6000 0 0 4 &mpic 4 1
219
220 /* IDSEL 0x0d */
221 6800 0 0 1 &mpic 4 1
222 6800 0 0 2 &mpic 1 1
223 6800 0 0 3 &mpic 2 1
224 6800 0 0 4 &mpic 3 1
225
226 /* IDSEL 0x0e */
227 7000 0 0 1 &mpic 3 1
228 7000 0 0 2 &mpic 4 1
229 7000 0 0 3 &mpic 1 1
230 7000 0 0 4 &mpic 2 1
231
232 /* IDSEL 0x0f */
233 7800 0 0 1 &mpic 2 1
234 7800 0 0 2 &mpic 3 1
235 7800 0 0 3 &mpic 4 1
236 7800 0 0 4 &mpic 1 1
237
238 /* IDSEL 0x12 */
239 9000 0 0 1 &mpic 1 1
240 9000 0 0 2 &mpic 2 1
241 9000 0 0 3 &mpic 3 1
242 9000 0 0 4 &mpic 4 1
243
244 /* IDSEL 0x13 */
245 9800 0 0 1 &mpic 4 1
246 9800 0 0 2 &mpic 1 1
247 9800 0 0 3 &mpic 2 1
248 9800 0 0 4 &mpic 3 1
249
250 /* IDSEL 0x14 */
251 a000 0 0 1 &mpic 3 1
252 a000 0 0 2 &mpic 4 1
253 a000 0 0 3 &mpic 1 1
254 a000 0 0 4 &mpic 2 1
255
256 /* IDSEL 0x15 */
257 a800 0 0 1 &mpic 2 1
258 a800 0 0 2 &mpic 3 1
259 a800 0 0 3 &mpic 4 1
260 a800 0 0 4 &mpic 1 1>;
261 interrupt-parent = <&mpic>;
262 interrupts = <18 2>;
263 bus-range = <0 0>;
264 ranges = <02000000 0 80000000 80000000 0 20000000
265 01000000 0 00000000 e2000000 0 00100000>;
266 clock-frequency = <3f940aa>;
267 #interrupt-cells = <1>;
268 #size-cells = <2>;
269 #address-cells = <3>;
270 reg = <e0008000 1000>;
271 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
272 device_type = "pci";
273 };
Andy Fleming2654d632006-08-18 18:04:34 -0500274};