Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 1 | /* |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 2 | * Copyright (C) 2009 Samsung Electronics Ltd. |
| 3 | * Jaswinder Singh <jassi.brar@samsung.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/workqueue.h> |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 23 | #include <linux/interrupt.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 24 | #include <linux/delay.h> |
| 25 | #include <linux/clk.h> |
| 26 | #include <linux/dma-mapping.h> |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 27 | #include <linux/dmaengine.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 28 | #include <linux/platform_device.h> |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 29 | #include <linux/pm_runtime.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 30 | #include <linux/spi/spi.h> |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 31 | #include <linux/gpio.h> |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 32 | #include <linux/of.h> |
| 33 | #include <linux/of_gpio.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 34 | |
Arnd Bergmann | 436d42c | 2012-08-24 15:22:12 +0200 | [diff] [blame] | 35 | #include <linux/platform_data/spi-s3c64xx.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 36 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 37 | #define MAX_SPI_PORTS 3 |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 38 | #define S3C64XX_SPI_QUIRK_POLL (1 << 0) |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 39 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 40 | /* Registers and bit-fields */ |
| 41 | |
| 42 | #define S3C64XX_SPI_CH_CFG 0x00 |
| 43 | #define S3C64XX_SPI_CLK_CFG 0x04 |
| 44 | #define S3C64XX_SPI_MODE_CFG 0x08 |
| 45 | #define S3C64XX_SPI_SLAVE_SEL 0x0C |
| 46 | #define S3C64XX_SPI_INT_EN 0x10 |
| 47 | #define S3C64XX_SPI_STATUS 0x14 |
| 48 | #define S3C64XX_SPI_TX_DATA 0x18 |
| 49 | #define S3C64XX_SPI_RX_DATA 0x1C |
| 50 | #define S3C64XX_SPI_PACKET_CNT 0x20 |
| 51 | #define S3C64XX_SPI_PENDING_CLR 0x24 |
| 52 | #define S3C64XX_SPI_SWAP_CFG 0x28 |
| 53 | #define S3C64XX_SPI_FB_CLK 0x2C |
| 54 | |
| 55 | #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ |
| 56 | #define S3C64XX_SPI_CH_SW_RST (1<<5) |
| 57 | #define S3C64XX_SPI_CH_SLAVE (1<<4) |
| 58 | #define S3C64XX_SPI_CPOL_L (1<<3) |
| 59 | #define S3C64XX_SPI_CPHA_B (1<<2) |
| 60 | #define S3C64XX_SPI_CH_RXCH_ON (1<<1) |
| 61 | #define S3C64XX_SPI_CH_TXCH_ON (1<<0) |
| 62 | |
| 63 | #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) |
| 64 | #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 |
| 65 | #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 66 | #define S3C64XX_SPI_PSR_MASK 0xff |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 67 | |
| 68 | #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) |
| 69 | #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) |
| 70 | #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) |
| 71 | #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) |
| 72 | #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) |
| 73 | #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) |
| 74 | #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) |
| 75 | #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) |
| 76 | #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) |
| 77 | #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) |
| 78 | #define S3C64XX_SPI_MODE_4BURST (1<<0) |
| 79 | |
| 80 | #define S3C64XX_SPI_SLAVE_AUTO (1<<1) |
| 81 | #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) |
| 82 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 83 | #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) |
| 84 | #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) |
| 85 | #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) |
| 86 | #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) |
| 87 | #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) |
| 88 | #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) |
| 89 | #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) |
| 90 | |
| 91 | #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) |
| 92 | #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) |
| 93 | #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) |
| 94 | #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) |
| 95 | #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) |
| 96 | #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) |
| 97 | |
| 98 | #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) |
| 99 | |
| 100 | #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) |
| 101 | #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) |
| 102 | #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) |
| 103 | #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) |
| 104 | #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) |
| 105 | |
| 106 | #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) |
| 107 | #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) |
| 108 | #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) |
| 109 | #define S3C64XX_SPI_SWAP_RX_EN (1<<4) |
| 110 | #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) |
| 111 | #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) |
| 112 | #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) |
| 113 | #define S3C64XX_SPI_SWAP_TX_EN (1<<0) |
| 114 | |
| 115 | #define S3C64XX_SPI_FBCLK_MSK (3<<0) |
| 116 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 117 | #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) |
| 118 | #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ |
| 119 | (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) |
| 120 | #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) |
| 121 | #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ |
| 122 | FIFO_LVL_MASK(i)) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 123 | |
| 124 | #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff |
| 125 | #define S3C64XX_SPI_TRAILCNT_OFF 19 |
| 126 | |
| 127 | #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT |
| 128 | |
| 129 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 130 | #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 131 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 132 | #define RXBUSY (1<<2) |
| 133 | #define TXBUSY (1<<3) |
| 134 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 135 | struct s3c64xx_spi_dma_data { |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 136 | struct dma_chan *ch; |
Arnd Bergmann | c10356b | 2012-04-30 16:31:27 +0000 | [diff] [blame] | 137 | enum dma_transfer_direction direction; |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 138 | unsigned int dmach; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 139 | }; |
| 140 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 141 | /** |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 142 | * struct s3c64xx_spi_info - SPI Controller hardware info |
| 143 | * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. |
| 144 | * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. |
| 145 | * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. |
| 146 | * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. |
| 147 | * @clk_from_cmu: True, if the controller does not include a clock mux and |
| 148 | * prescaler unit. |
| 149 | * |
| 150 | * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but |
| 151 | * differ in some aspects such as the size of the fifo and spi bus clock |
| 152 | * setup. Such differences are specified to the driver using this structure |
| 153 | * which is provided as driver data to the driver. |
| 154 | */ |
| 155 | struct s3c64xx_spi_port_config { |
| 156 | int fifo_lvl_mask[MAX_SPI_PORTS]; |
| 157 | int rx_lvl_offset; |
| 158 | int tx_st_done; |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 159 | int quirks; |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 160 | bool high_speed; |
| 161 | bool clk_from_cmu; |
| 162 | }; |
| 163 | |
| 164 | /** |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 165 | * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. |
| 166 | * @clk: Pointer to the spi clock. |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 167 | * @src_clk: Pointer to the clock used to generate SPI signals. |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 168 | * @master: Pointer to the SPI Protocol master. |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 169 | * @cntrlr_info: Platform specific data for the controller this driver manages. |
| 170 | * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 171 | * @lock: Controller specific lock. |
| 172 | * @state: Set of FLAGS to indicate status. |
| 173 | * @rx_dmach: Controller's DMA channel for Rx. |
| 174 | * @tx_dmach: Controller's DMA channel for Tx. |
| 175 | * @sfr_start: BUS address of SPI controller regs. |
| 176 | * @regs: Pointer to ioremap'ed controller registers. |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 177 | * @irq: interrupt |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 178 | * @xfer_completion: To indicate completion of xfer task. |
| 179 | * @cur_mode: Stores the active configuration of the controller. |
| 180 | * @cur_bpw: Stores the active bits per word settings. |
| 181 | * @cur_speed: Stores the active xfer clock speed. |
| 182 | */ |
| 183 | struct s3c64xx_spi_driver_data { |
| 184 | void __iomem *regs; |
| 185 | struct clk *clk; |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 186 | struct clk *src_clk; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 187 | struct platform_device *pdev; |
| 188 | struct spi_master *master; |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 189 | struct s3c64xx_spi_info *cntrlr_info; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 190 | struct spi_device *tgl_spi; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 191 | spinlock_t lock; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 192 | unsigned long sfr_start; |
| 193 | struct completion xfer_completion; |
| 194 | unsigned state; |
| 195 | unsigned cur_mode, cur_bpw; |
| 196 | unsigned cur_speed; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 197 | struct s3c64xx_spi_dma_data rx_dma; |
| 198 | struct s3c64xx_spi_dma_data tx_dma; |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 199 | struct s3c64xx_spi_port_config *port_conf; |
| 200 | unsigned int port_id; |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 201 | bool cs_gpio; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 202 | }; |
| 203 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 204 | static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) |
| 205 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 206 | void __iomem *regs = sdd->regs; |
| 207 | unsigned long loops; |
| 208 | u32 val; |
| 209 | |
| 210 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); |
| 211 | |
| 212 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
Kyoungil Kim | 7d859ff | 2012-05-23 21:29:51 +0900 | [diff] [blame] | 213 | val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); |
| 214 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 215 | |
| 216 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 217 | val |= S3C64XX_SPI_CH_SW_RST; |
| 218 | val &= ~S3C64XX_SPI_CH_HS_EN; |
| 219 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 220 | |
| 221 | /* Flush TxFIFO*/ |
| 222 | loops = msecs_to_loops(1); |
| 223 | do { |
| 224 | val = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 225 | } while (TX_FIFO_LVL(val, sdd) && loops--); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 226 | |
Mark Brown | be7852a | 2010-08-23 17:40:56 +0100 | [diff] [blame] | 227 | if (loops == 0) |
| 228 | dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); |
| 229 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 230 | /* Flush RxFIFO*/ |
| 231 | loops = msecs_to_loops(1); |
| 232 | do { |
| 233 | val = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 234 | if (RX_FIFO_LVL(val, sdd)) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 235 | readl(regs + S3C64XX_SPI_RX_DATA); |
| 236 | else |
| 237 | break; |
| 238 | } while (loops--); |
| 239 | |
Mark Brown | be7852a | 2010-08-23 17:40:56 +0100 | [diff] [blame] | 240 | if (loops == 0) |
| 241 | dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); |
| 242 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 243 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
| 244 | val &= ~S3C64XX_SPI_CH_SW_RST; |
| 245 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 246 | |
| 247 | val = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 248 | val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); |
| 249 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 250 | } |
| 251 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 252 | static void s3c64xx_spi_dmacb(void *data) |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 253 | { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 254 | struct s3c64xx_spi_driver_data *sdd; |
| 255 | struct s3c64xx_spi_dma_data *dma = data; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 256 | unsigned long flags; |
| 257 | |
Kyoungil Kim | 054ebcc | 2012-03-10 09:48:46 +0900 | [diff] [blame] | 258 | if (dma->direction == DMA_DEV_TO_MEM) |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 259 | sdd = container_of(data, |
| 260 | struct s3c64xx_spi_driver_data, rx_dma); |
| 261 | else |
| 262 | sdd = container_of(data, |
| 263 | struct s3c64xx_spi_driver_data, tx_dma); |
| 264 | |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 265 | spin_lock_irqsave(&sdd->lock, flags); |
| 266 | |
Kyoungil Kim | 054ebcc | 2012-03-10 09:48:46 +0900 | [diff] [blame] | 267 | if (dma->direction == DMA_DEV_TO_MEM) { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 268 | sdd->state &= ~RXBUSY; |
| 269 | if (!(sdd->state & TXBUSY)) |
| 270 | complete(&sdd->xfer_completion); |
| 271 | } else { |
| 272 | sdd->state &= ~TXBUSY; |
| 273 | if (!(sdd->state & RXBUSY)) |
| 274 | complete(&sdd->xfer_completion); |
| 275 | } |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 276 | |
| 277 | spin_unlock_irqrestore(&sdd->lock, flags); |
| 278 | } |
| 279 | |
Mark Brown | 3f29588 | 2014-01-16 12:25:46 +0000 | [diff] [blame] | 280 | static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, |
| 281 | struct spi_message *msg) |
| 282 | { |
| 283 | return 0; |
| 284 | } |
| 285 | |
| 286 | static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, |
| 287 | struct spi_message *msg) |
| 288 | { |
| 289 | } |
| 290 | |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 291 | static void prepare_dma(struct s3c64xx_spi_dma_data *dma, |
Mark Brown | 6ad45a2 | 2014-02-02 13:47:47 +0000 | [diff] [blame] | 292 | struct sg_table *sgt) |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 293 | { |
| 294 | struct s3c64xx_spi_driver_data *sdd; |
| 295 | struct dma_slave_config config; |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 296 | struct dma_async_tx_descriptor *desc; |
| 297 | |
Tomasz Figa | b1a8e78 | 2013-08-11 02:33:28 +0200 | [diff] [blame] | 298 | memset(&config, 0, sizeof(config)); |
| 299 | |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 300 | if (dma->direction == DMA_DEV_TO_MEM) { |
| 301 | sdd = container_of((void *)dma, |
| 302 | struct s3c64xx_spi_driver_data, rx_dma); |
| 303 | config.direction = dma->direction; |
| 304 | config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; |
| 305 | config.src_addr_width = sdd->cur_bpw / 8; |
| 306 | config.src_maxburst = 1; |
| 307 | dmaengine_slave_config(dma->ch, &config); |
| 308 | } else { |
| 309 | sdd = container_of((void *)dma, |
| 310 | struct s3c64xx_spi_driver_data, tx_dma); |
| 311 | config.direction = dma->direction; |
| 312 | config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; |
| 313 | config.dst_addr_width = sdd->cur_bpw / 8; |
| 314 | config.dst_maxburst = 1; |
| 315 | dmaengine_slave_config(dma->ch, &config); |
| 316 | } |
| 317 | |
Mark Brown | 6ad45a2 | 2014-02-02 13:47:47 +0000 | [diff] [blame] | 318 | desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, |
| 319 | dma->direction, DMA_PREP_INTERRUPT); |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 320 | |
| 321 | desc->callback = s3c64xx_spi_dmacb; |
| 322 | desc->callback_param = dma; |
| 323 | |
| 324 | dmaengine_submit(desc); |
| 325 | dma_async_issue_pending(dma->ch); |
| 326 | } |
| 327 | |
| 328 | static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) |
| 329 | { |
| 330 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); |
| 331 | dma_filter_fn filter = sdd->cntrlr_info->filter; |
| 332 | struct device *dev = &sdd->pdev->dev; |
| 333 | dma_cap_mask_t mask; |
Mark Brown | fb9d044 | 2013-04-18 18:12:00 +0100 | [diff] [blame] | 334 | int ret; |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 335 | |
Mark Brown | c12f964 | 2013-08-13 19:03:01 +0100 | [diff] [blame] | 336 | if (!is_polling(sdd)) { |
| 337 | dma_cap_zero(mask); |
| 338 | dma_cap_set(DMA_SLAVE, mask); |
Girish K S | d96760f9 | 2013-06-27 12:26:53 +0530 | [diff] [blame] | 339 | |
Mark Brown | c12f964 | 2013-08-13 19:03:01 +0100 | [diff] [blame] | 340 | /* Acquire DMA channels */ |
| 341 | sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter, |
| 342 | (void *)sdd->rx_dma.dmach, dev, "rx"); |
| 343 | if (!sdd->rx_dma.ch) { |
| 344 | dev_err(dev, "Failed to get RX DMA channel\n"); |
| 345 | ret = -EBUSY; |
| 346 | goto out; |
| 347 | } |
Mark Brown | 3f29588 | 2014-01-16 12:25:46 +0000 | [diff] [blame] | 348 | spi->dma_rx = sdd->rx_dma.ch; |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 349 | |
Mark Brown | c12f964 | 2013-08-13 19:03:01 +0100 | [diff] [blame] | 350 | sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter, |
| 351 | (void *)sdd->tx_dma.dmach, dev, "tx"); |
| 352 | if (!sdd->tx_dma.ch) { |
| 353 | dev_err(dev, "Failed to get TX DMA channel\n"); |
| 354 | ret = -EBUSY; |
| 355 | goto out_rx; |
| 356 | } |
Mark Brown | 3f29588 | 2014-01-16 12:25:46 +0000 | [diff] [blame] | 357 | spi->dma_tx = sdd->tx_dma.ch; |
Mark Brown | fb9d044 | 2013-04-18 18:12:00 +0100 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | ret = pm_runtime_get_sync(&sdd->pdev->dev); |
Sylwester Nawrocki | 6c6cf64 | 2013-06-10 18:22:26 +0200 | [diff] [blame] | 361 | if (ret < 0) { |
Mark Brown | fb9d044 | 2013-04-18 18:12:00 +0100 | [diff] [blame] | 362 | dev_err(dev, "Failed to enable device: %d\n", ret); |
| 363 | goto out_tx; |
| 364 | } |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 365 | |
| 366 | return 0; |
Mark Brown | fb9d044 | 2013-04-18 18:12:00 +0100 | [diff] [blame] | 367 | |
| 368 | out_tx: |
| 369 | dma_release_channel(sdd->tx_dma.ch); |
| 370 | out_rx: |
| 371 | dma_release_channel(sdd->rx_dma.ch); |
| 372 | out: |
| 373 | return ret; |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 374 | } |
| 375 | |
| 376 | static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) |
| 377 | { |
| 378 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); |
| 379 | |
| 380 | /* Free DMA channels */ |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 381 | if (!is_polling(sdd)) { |
| 382 | dma_release_channel(sdd->rx_dma.ch); |
| 383 | dma_release_channel(sdd->tx_dma.ch); |
| 384 | } |
Arnd Bergmann | 7884372 | 2013-04-11 22:42:03 +0200 | [diff] [blame] | 385 | |
| 386 | pm_runtime_put(&sdd->pdev->dev); |
| 387 | return 0; |
| 388 | } |
| 389 | |
| 390 | static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd, |
| 391 | struct s3c64xx_spi_dma_data *dma) |
| 392 | { |
| 393 | dmaengine_terminate_all(dma->ch); |
| 394 | } |
Mark Brown | 3f29588 | 2014-01-16 12:25:46 +0000 | [diff] [blame] | 395 | |
| 396 | static bool s3c64xx_spi_can_dma(struct spi_master *master, |
| 397 | struct spi_device *spi, |
| 398 | struct spi_transfer *xfer) |
| 399 | { |
| 400 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
| 401 | |
| 402 | return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; |
| 403 | } |
| 404 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 405 | static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, |
| 406 | struct spi_device *spi, |
| 407 | struct spi_transfer *xfer, int dma_mode) |
| 408 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 409 | void __iomem *regs = sdd->regs; |
| 410 | u32 modecfg, chcfg; |
| 411 | |
| 412 | modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 413 | modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); |
| 414 | |
| 415 | chcfg = readl(regs + S3C64XX_SPI_CH_CFG); |
| 416 | chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; |
| 417 | |
| 418 | if (dma_mode) { |
| 419 | chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; |
| 420 | } else { |
| 421 | /* Always shift in data in FIFO, even if xfer is Tx only, |
| 422 | * this helps setting PCKT_CNT value for generating clocks |
| 423 | * as exactly needed. |
| 424 | */ |
| 425 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; |
| 426 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) |
| 427 | | S3C64XX_SPI_PACKET_CNT_EN, |
| 428 | regs + S3C64XX_SPI_PACKET_CNT); |
| 429 | } |
| 430 | |
| 431 | if (xfer->tx_buf != NULL) { |
| 432 | sdd->state |= TXBUSY; |
| 433 | chcfg |= S3C64XX_SPI_CH_TXCH_ON; |
| 434 | if (dma_mode) { |
| 435 | modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; |
Mark Brown | 6ad45a2 | 2014-02-02 13:47:47 +0000 | [diff] [blame] | 436 | prepare_dma(&sdd->tx_dma, &xfer->tx_sg); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 437 | } else { |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 438 | switch (sdd->cur_bpw) { |
| 439 | case 32: |
| 440 | iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, |
| 441 | xfer->tx_buf, xfer->len / 4); |
| 442 | break; |
| 443 | case 16: |
| 444 | iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, |
| 445 | xfer->tx_buf, xfer->len / 2); |
| 446 | break; |
| 447 | default: |
| 448 | iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, |
| 449 | xfer->tx_buf, xfer->len); |
| 450 | break; |
| 451 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 452 | } |
| 453 | } |
| 454 | |
| 455 | if (xfer->rx_buf != NULL) { |
| 456 | sdd->state |= RXBUSY; |
| 457 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 458 | if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 459 | && !(sdd->cur_mode & SPI_CPHA)) |
| 460 | chcfg |= S3C64XX_SPI_CH_HS_EN; |
| 461 | |
| 462 | if (dma_mode) { |
| 463 | modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; |
| 464 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; |
| 465 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) |
| 466 | | S3C64XX_SPI_PACKET_CNT_EN, |
| 467 | regs + S3C64XX_SPI_PACKET_CNT); |
Mark Brown | 6ad45a2 | 2014-02-02 13:47:47 +0000 | [diff] [blame] | 468 | prepare_dma(&sdd->rx_dma, &xfer->rx_sg); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 469 | } |
| 470 | } |
| 471 | |
| 472 | writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); |
| 473 | writel(chcfg, regs + S3C64XX_SPI_CH_CFG); |
| 474 | } |
| 475 | |
Mark Brown | 7961707 | 2013-06-19 19:12:39 +0100 | [diff] [blame] | 476 | static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 477 | int timeout_ms) |
| 478 | { |
| 479 | void __iomem *regs = sdd->regs; |
| 480 | unsigned long val = 1; |
| 481 | u32 status; |
| 482 | |
| 483 | /* max fifo depth available */ |
| 484 | u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; |
| 485 | |
| 486 | if (timeout_ms) |
| 487 | val = msecs_to_loops(timeout_ms); |
| 488 | |
| 489 | do { |
| 490 | status = readl(regs + S3C64XX_SPI_STATUS); |
| 491 | } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); |
| 492 | |
| 493 | /* return the actual received data length */ |
| 494 | return RX_FIFO_LVL(status, sdd); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 495 | } |
| 496 | |
Mark Brown | 3700c6e | 2014-01-24 20:05:43 +0000 | [diff] [blame] | 497 | static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd, |
| 498 | struct spi_transfer *xfer) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 499 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 500 | void __iomem *regs = sdd->regs; |
| 501 | unsigned long val; |
Mark Brown | 3700c6e | 2014-01-24 20:05:43 +0000 | [diff] [blame] | 502 | u32 status; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 503 | int ms; |
| 504 | |
| 505 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ |
| 506 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; |
Mark Brown | 9d8f86b | 2010-09-07 16:37:52 +0100 | [diff] [blame] | 507 | ms += 10; /* some tolerance */ |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 508 | |
Mark Brown | 3700c6e | 2014-01-24 20:05:43 +0000 | [diff] [blame] | 509 | val = msecs_to_jiffies(ms) + 10; |
| 510 | val = wait_for_completion_timeout(&sdd->xfer_completion, val); |
| 511 | |
| 512 | /* |
| 513 | * If the previous xfer was completed within timeout, then |
| 514 | * proceed further else return -EIO. |
| 515 | * DmaTx returns after simply writing data in the FIFO, |
| 516 | * w/o waiting for real transmission on the bus to finish. |
| 517 | * DmaRx returns only after Dma read data from FIFO which |
| 518 | * needs bus transmission to finish, so we don't worry if |
| 519 | * Xfer involved Rx(with or without Tx). |
| 520 | */ |
| 521 | if (val && !xfer->rx_buf) { |
| 522 | val = msecs_to_loops(10); |
| 523 | status = readl(regs + S3C64XX_SPI_STATUS); |
| 524 | while ((TX_FIFO_LVL(status, sdd) |
| 525 | || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) |
| 526 | && --val) { |
| 527 | cpu_relax(); |
Jassi Brar | c3f139b | 2010-09-03 10:36:46 +0900 | [diff] [blame] | 528 | status = readl(regs + S3C64XX_SPI_STATUS); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 529 | } |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 530 | |
Mark Brown | 3700c6e | 2014-01-24 20:05:43 +0000 | [diff] [blame] | 531 | } |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 532 | |
Mark Brown | 3700c6e | 2014-01-24 20:05:43 +0000 | [diff] [blame] | 533 | /* If timed out while checking rx/tx status return error */ |
| 534 | if (!val) |
| 535 | return -EIO; |
| 536 | |
| 537 | return 0; |
| 538 | } |
| 539 | |
| 540 | static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd, |
| 541 | struct spi_transfer *xfer) |
| 542 | { |
| 543 | void __iomem *regs = sdd->regs; |
| 544 | unsigned long val; |
| 545 | u32 status; |
| 546 | int loops; |
| 547 | u32 cpy_len; |
| 548 | u8 *buf; |
| 549 | int ms; |
| 550 | |
| 551 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ |
| 552 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; |
| 553 | ms += 10; /* some tolerance */ |
| 554 | |
| 555 | val = msecs_to_loops(ms); |
| 556 | do { |
| 557 | status = readl(regs + S3C64XX_SPI_STATUS); |
| 558 | } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); |
| 559 | |
| 560 | |
| 561 | /* If it was only Tx */ |
| 562 | if (!xfer->rx_buf) { |
| 563 | sdd->state &= ~TXBUSY; |
| 564 | return 0; |
| 565 | } |
| 566 | |
| 567 | /* |
| 568 | * If the receive length is bigger than the controller fifo |
| 569 | * size, calculate the loops and read the fifo as many times. |
| 570 | * loops = length / max fifo size (calculated by using the |
| 571 | * fifo mask). |
| 572 | * For any size less than the fifo size the below code is |
| 573 | * executed atleast once. |
| 574 | */ |
| 575 | loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); |
| 576 | buf = xfer->rx_buf; |
| 577 | do { |
| 578 | /* wait for data to be received in the fifo */ |
| 579 | cpy_len = s3c64xx_spi_wait_for_timeout(sdd, |
| 580 | (loops ? ms : 0)); |
| 581 | |
| 582 | switch (sdd->cur_bpw) { |
| 583 | case 32: |
| 584 | ioread32_rep(regs + S3C64XX_SPI_RX_DATA, |
| 585 | buf, cpy_len / 4); |
| 586 | break; |
| 587 | case 16: |
| 588 | ioread16_rep(regs + S3C64XX_SPI_RX_DATA, |
| 589 | buf, cpy_len / 2); |
| 590 | break; |
| 591 | default: |
| 592 | ioread8_rep(regs + S3C64XX_SPI_RX_DATA, |
| 593 | buf, cpy_len); |
| 594 | break; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 595 | } |
| 596 | |
Mark Brown | 3700c6e | 2014-01-24 20:05:43 +0000 | [diff] [blame] | 597 | buf = buf + cpy_len; |
| 598 | } while (loops--); |
| 599 | sdd->state &= ~RXBUSY; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 600 | |
| 601 | return 0; |
| 602 | } |
| 603 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 604 | static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) |
| 605 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 606 | void __iomem *regs = sdd->regs; |
| 607 | u32 val; |
| 608 | |
| 609 | /* Disable Clock */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 610 | if (sdd->port_conf->clk_from_cmu) { |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 611 | clk_disable_unprepare(sdd->src_clk); |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 612 | } else { |
| 613 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
| 614 | val &= ~S3C64XX_SPI_ENCLK_ENABLE; |
| 615 | writel(val, regs + S3C64XX_SPI_CLK_CFG); |
| 616 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 617 | |
| 618 | /* Set Polarity and Phase */ |
| 619 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
| 620 | val &= ~(S3C64XX_SPI_CH_SLAVE | |
| 621 | S3C64XX_SPI_CPOL_L | |
| 622 | S3C64XX_SPI_CPHA_B); |
| 623 | |
| 624 | if (sdd->cur_mode & SPI_CPOL) |
| 625 | val |= S3C64XX_SPI_CPOL_L; |
| 626 | |
| 627 | if (sdd->cur_mode & SPI_CPHA) |
| 628 | val |= S3C64XX_SPI_CPHA_B; |
| 629 | |
| 630 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 631 | |
| 632 | /* Set Channel & DMA Mode */ |
| 633 | val = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 634 | val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK |
| 635 | | S3C64XX_SPI_MODE_CH_TSZ_MASK); |
| 636 | |
| 637 | switch (sdd->cur_bpw) { |
| 638 | case 32: |
| 639 | val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 640 | val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 641 | break; |
| 642 | case 16: |
| 643 | val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 644 | val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 645 | break; |
| 646 | default: |
| 647 | val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 648 | val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 649 | break; |
| 650 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 651 | |
| 652 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
| 653 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 654 | if (sdd->port_conf->clk_from_cmu) { |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 655 | /* Configure Clock */ |
| 656 | /* There is half-multiplier before the SPI */ |
| 657 | clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); |
| 658 | /* Enable Clock */ |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 659 | clk_prepare_enable(sdd->src_clk); |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 660 | } else { |
| 661 | /* Configure Clock */ |
| 662 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
| 663 | val &= ~S3C64XX_SPI_PSR_MASK; |
| 664 | val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) |
| 665 | & S3C64XX_SPI_PSR_MASK); |
| 666 | writel(val, regs + S3C64XX_SPI_CLK_CFG); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 667 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 668 | /* Enable Clock */ |
| 669 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
| 670 | val |= S3C64XX_SPI_ENCLK_ENABLE; |
| 671 | writel(val, regs + S3C64XX_SPI_CLK_CFG); |
| 672 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 673 | } |
| 674 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 675 | #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) |
| 676 | |
Mark Brown | 6bb9c0e | 2013-10-05 00:42:58 +0100 | [diff] [blame] | 677 | static int s3c64xx_spi_prepare_message(struct spi_master *master, |
| 678 | struct spi_message *msg) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 679 | { |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 680 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 681 | struct spi_device *spi = msg->spi; |
| 682 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 683 | |
| 684 | /* If Master's(controller) state differs from that needed by Slave */ |
| 685 | if (sdd->cur_speed != spi->max_speed_hz |
| 686 | || sdd->cur_mode != spi->mode |
| 687 | || sdd->cur_bpw != spi->bits_per_word) { |
| 688 | sdd->cur_bpw = spi->bits_per_word; |
| 689 | sdd->cur_speed = spi->max_speed_hz; |
| 690 | sdd->cur_mode = spi->mode; |
| 691 | s3c64xx_spi_config(sdd); |
| 692 | } |
| 693 | |
| 694 | /* Map all the transfers if needed */ |
| 695 | if (s3c64xx_spi_map_mssg(sdd, msg)) { |
| 696 | dev_err(&spi->dev, |
| 697 | "Xfer: Unable to map message buffers!\n"); |
Mark Brown | 6bb9c0e | 2013-10-05 00:42:58 +0100 | [diff] [blame] | 698 | return -ENOMEM; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 699 | } |
| 700 | |
| 701 | /* Configure feedback delay */ |
| 702 | writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); |
| 703 | |
Mark Brown | 6bb9c0e | 2013-10-05 00:42:58 +0100 | [diff] [blame] | 704 | return 0; |
| 705 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 706 | |
Mark Brown | 0732a9d | 2013-10-05 11:51:14 +0100 | [diff] [blame] | 707 | static int s3c64xx_spi_transfer_one(struct spi_master *master, |
| 708 | struct spi_device *spi, |
| 709 | struct spi_transfer *xfer) |
Mark Brown | 6bb9c0e | 2013-10-05 00:42:58 +0100 | [diff] [blame] | 710 | { |
| 711 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Mark Brown | 0732a9d | 2013-10-05 11:51:14 +0100 | [diff] [blame] | 712 | int status; |
Mark Brown | 6bb9c0e | 2013-10-05 00:42:58 +0100 | [diff] [blame] | 713 | u32 speed; |
| 714 | u8 bpw; |
Mark Brown | 0732a9d | 2013-10-05 11:51:14 +0100 | [diff] [blame] | 715 | unsigned long flags; |
| 716 | int use_dma; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 717 | |
Geert Uytterhoeven | 3e83c19 | 2014-01-12 14:07:50 +0100 | [diff] [blame] | 718 | reinit_completion(&sdd->xfer_completion); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 719 | |
Mark Brown | 0732a9d | 2013-10-05 11:51:14 +0100 | [diff] [blame] | 720 | /* Only BPW and Speed may change across transfers */ |
| 721 | bpw = xfer->bits_per_word; |
| 722 | speed = xfer->speed_hz ? : spi->max_speed_hz; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 723 | |
Mark Brown | 0732a9d | 2013-10-05 11:51:14 +0100 | [diff] [blame] | 724 | if (xfer->len % (bpw / 8)) { |
| 725 | dev_err(&spi->dev, |
| 726 | "Xfer length(%u) not a multiple of word size(%u)\n", |
| 727 | xfer->len, bpw / 8); |
| 728 | return -EIO; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 729 | } |
| 730 | |
Mark Brown | 0732a9d | 2013-10-05 11:51:14 +0100 | [diff] [blame] | 731 | if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { |
| 732 | sdd->cur_bpw = bpw; |
| 733 | sdd->cur_speed = speed; |
| 734 | s3c64xx_spi_config(sdd); |
| 735 | } |
| 736 | |
| 737 | /* Polling method for xfers not bigger than FIFO capacity */ |
| 738 | use_dma = 0; |
| 739 | if (!is_polling(sdd) && |
| 740 | (sdd->rx_dma.ch && sdd->tx_dma.ch && |
| 741 | (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1)))) |
| 742 | use_dma = 1; |
| 743 | |
| 744 | spin_lock_irqsave(&sdd->lock, flags); |
| 745 | |
| 746 | /* Pending only which is to be done */ |
| 747 | sdd->state &= ~RXBUSY; |
| 748 | sdd->state &= ~TXBUSY; |
| 749 | |
| 750 | enable_datapath(sdd, spi, xfer, use_dma); |
| 751 | |
| 752 | /* Start the signals */ |
| 753 | writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); |
| 754 | |
Mark Brown | 0732a9d | 2013-10-05 11:51:14 +0100 | [diff] [blame] | 755 | spin_unlock_irqrestore(&sdd->lock, flags); |
| 756 | |
Mark Brown | 3700c6e | 2014-01-24 20:05:43 +0000 | [diff] [blame] | 757 | if (use_dma) |
| 758 | status = wait_for_dma(sdd, xfer); |
| 759 | else |
| 760 | status = wait_for_pio(sdd, xfer); |
Mark Brown | 0732a9d | 2013-10-05 11:51:14 +0100 | [diff] [blame] | 761 | |
| 762 | if (status) { |
| 763 | dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n", |
| 764 | xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, |
| 765 | (sdd->state & RXBUSY) ? 'f' : 'p', |
| 766 | (sdd->state & TXBUSY) ? 'f' : 'p', |
| 767 | xfer->len); |
| 768 | |
| 769 | if (use_dma) { |
| 770 | if (xfer->tx_buf != NULL |
| 771 | && (sdd->state & TXBUSY)) |
| 772 | s3c64xx_spi_dma_stop(sdd, &sdd->tx_dma); |
| 773 | if (xfer->rx_buf != NULL |
| 774 | && (sdd->state & RXBUSY)) |
| 775 | s3c64xx_spi_dma_stop(sdd, &sdd->rx_dma); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 776 | } |
Mark Brown | 8c09daa | 2013-09-27 19:56:31 +0100 | [diff] [blame] | 777 | } else { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 778 | flush_fifo(sdd); |
| 779 | } |
| 780 | |
Mark Brown | 0732a9d | 2013-10-05 11:51:14 +0100 | [diff] [blame] | 781 | return status; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 782 | } |
| 783 | |
Mark Brown | 6bb9c0e | 2013-10-05 00:42:58 +0100 | [diff] [blame] | 784 | static int s3c64xx_spi_unprepare_message(struct spi_master *master, |
| 785 | struct spi_message *msg) |
| 786 | { |
| 787 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 788 | |
| 789 | s3c64xx_spi_unmap_mssg(sdd, msg); |
| 790 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 791 | return 0; |
| 792 | } |
| 793 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 794 | static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 795 | struct spi_device *spi) |
| 796 | { |
| 797 | struct s3c64xx_spi_csinfo *cs; |
Arnd Bergmann | 4732cc6 | 2012-08-04 11:18:20 +0000 | [diff] [blame] | 798 | struct device_node *slave_np, *data_np = NULL; |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 799 | struct s3c64xx_spi_driver_data *sdd; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 800 | u32 fb_delay = 0; |
| 801 | |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 802 | sdd = spi_master_get_devdata(spi->master); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 803 | slave_np = spi->dev.of_node; |
| 804 | if (!slave_np) { |
| 805 | dev_err(&spi->dev, "device node not found\n"); |
| 806 | return ERR_PTR(-EINVAL); |
| 807 | } |
| 808 | |
Srinivas Kandagatla | 06455bb | 2012-09-18 08:10:49 +0100 | [diff] [blame] | 809 | data_np = of_get_child_by_name(slave_np, "controller-data"); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 810 | if (!data_np) { |
| 811 | dev_err(&spi->dev, "child node 'controller-data' not found\n"); |
| 812 | return ERR_PTR(-EINVAL); |
| 813 | } |
| 814 | |
| 815 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
| 816 | if (!cs) { |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 817 | dev_err(&spi->dev, "could not allocate memory for controller data\n"); |
Srinivas Kandagatla | 06455bb | 2012-09-18 08:10:49 +0100 | [diff] [blame] | 818 | of_node_put(data_np); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 819 | return ERR_PTR(-ENOMEM); |
| 820 | } |
| 821 | |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 822 | /* The CS line is asserted/deasserted by the gpio pin */ |
| 823 | if (sdd->cs_gpio) |
| 824 | cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); |
| 825 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 826 | if (!gpio_is_valid(cs->line)) { |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 827 | dev_err(&spi->dev, "chip select gpio is not specified or invalid\n"); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 828 | kfree(cs); |
Srinivas Kandagatla | 06455bb | 2012-09-18 08:10:49 +0100 | [diff] [blame] | 829 | of_node_put(data_np); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 830 | return ERR_PTR(-EINVAL); |
| 831 | } |
| 832 | |
| 833 | of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); |
| 834 | cs->fb_delay = fb_delay; |
Srinivas Kandagatla | 06455bb | 2012-09-18 08:10:49 +0100 | [diff] [blame] | 835 | of_node_put(data_np); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 836 | return cs; |
| 837 | } |
| 838 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 839 | /* |
| 840 | * Here we only check the validity of requested configuration |
| 841 | * and save the configuration in a local data-structure. |
| 842 | * The controller is actually configured only just before we |
| 843 | * get a message to transfer. |
| 844 | */ |
| 845 | static int s3c64xx_spi_setup(struct spi_device *spi) |
| 846 | { |
| 847 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
| 848 | struct s3c64xx_spi_driver_data *sdd; |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 849 | struct s3c64xx_spi_info *sci; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 850 | int err; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 851 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 852 | sdd = spi_master_get_devdata(spi->master); |
| 853 | if (!cs && spi->dev.of_node) { |
Matthias Brugger | 5c725b3 | 2013-03-26 10:27:35 +0100 | [diff] [blame] | 854 | cs = s3c64xx_get_slave_ctrldata(spi); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 855 | spi->controller_data = cs; |
| 856 | } |
| 857 | |
| 858 | if (IS_ERR_OR_NULL(cs)) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 859 | dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); |
| 860 | return -ENODEV; |
| 861 | } |
| 862 | |
Tomasz Figa | 0149871 | 2013-08-11 02:33:29 +0200 | [diff] [blame] | 863 | if (!spi_get_ctldata(spi)) { |
| 864 | /* Request gpio only if cs line is asserted by gpio pins */ |
| 865 | if (sdd->cs_gpio) { |
| 866 | err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH, |
| 867 | dev_name(&spi->dev)); |
| 868 | if (err) { |
| 869 | dev_err(&spi->dev, |
| 870 | "Failed to get /CS gpio [%d]: %d\n", |
| 871 | cs->line, err); |
| 872 | goto err_gpio_req; |
| 873 | } |
Mark Brown | dd97e26 | 2013-09-27 18:58:55 +0100 | [diff] [blame] | 874 | |
| 875 | spi->cs_gpio = cs->line; |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 876 | } |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 877 | |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 878 | spi_set_ctldata(spi, cs); |
Tomasz Figa | 0149871 | 2013-08-11 02:33:29 +0200 | [diff] [blame] | 879 | } |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 880 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 881 | sci = sdd->cntrlr_info; |
| 882 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 883 | pm_runtime_get_sync(&sdd->pdev->dev); |
| 884 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 885 | /* Check if we can provide the requested rate */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 886 | if (!sdd->port_conf->clk_from_cmu) { |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 887 | u32 psr, speed; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 888 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 889 | /* Max possible */ |
| 890 | speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 891 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 892 | if (spi->max_speed_hz > speed) |
| 893 | spi->max_speed_hz = speed; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 894 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 895 | psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; |
| 896 | psr &= S3C64XX_SPI_PSR_MASK; |
| 897 | if (psr == S3C64XX_SPI_PSR_MASK) |
| 898 | psr--; |
| 899 | |
| 900 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
| 901 | if (spi->max_speed_hz < speed) { |
| 902 | if (psr+1 < S3C64XX_SPI_PSR_MASK) { |
| 903 | psr++; |
| 904 | } else { |
| 905 | err = -EINVAL; |
| 906 | goto setup_exit; |
| 907 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 908 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 909 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 910 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 911 | if (spi->max_speed_hz >= speed) { |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 912 | spi->max_speed_hz = speed; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 913 | } else { |
Mark Brown | e1b0f0d | 2012-12-20 18:27:31 +0000 | [diff] [blame] | 914 | dev_err(&spi->dev, "Can't set %dHz transfer speed\n", |
| 915 | spi->max_speed_hz); |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 916 | err = -EINVAL; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 917 | goto setup_exit; |
| 918 | } |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 919 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 920 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 921 | pm_runtime_put(&sdd->pdev->dev); |
Mark Brown | 8c09daa | 2013-09-27 19:56:31 +0100 | [diff] [blame] | 922 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 923 | return 0; |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 924 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 925 | setup_exit: |
Krzysztof Kozlowski | 7b8f7ee | 2013-10-17 14:45:41 +0200 | [diff] [blame] | 926 | pm_runtime_put(&sdd->pdev->dev); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 927 | /* setup() returns with device de-selected */ |
Mark Brown | 8c09daa | 2013-09-27 19:56:31 +0100 | [diff] [blame] | 928 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 929 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 930 | gpio_free(cs->line); |
| 931 | spi_set_ctldata(spi, NULL); |
| 932 | |
| 933 | err_gpio_req: |
Sylwester Nawrocki | 5bee3b9 | 2012-09-13 16:31:30 +0200 | [diff] [blame] | 934 | if (spi->dev.of_node) |
| 935 | kfree(cs); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 936 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 937 | return err; |
| 938 | } |
| 939 | |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 940 | static void s3c64xx_spi_cleanup(struct spi_device *spi) |
| 941 | { |
| 942 | struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 943 | struct s3c64xx_spi_driver_data *sdd; |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 944 | |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 945 | sdd = spi_master_get_devdata(spi->master); |
Mark Brown | dd97e26 | 2013-09-27 18:58:55 +0100 | [diff] [blame] | 946 | if (spi->cs_gpio) { |
| 947 | gpio_free(spi->cs_gpio); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 948 | if (spi->dev.of_node) |
| 949 | kfree(cs); |
| 950 | } |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 951 | spi_set_ctldata(spi, NULL); |
| 952 | } |
| 953 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 954 | static irqreturn_t s3c64xx_spi_irq(int irq, void *data) |
| 955 | { |
| 956 | struct s3c64xx_spi_driver_data *sdd = data; |
| 957 | struct spi_master *spi = sdd->master; |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 958 | unsigned int val, clr = 0; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 959 | |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 960 | val = readl(sdd->regs + S3C64XX_SPI_STATUS); |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 961 | |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 962 | if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { |
| 963 | clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 964 | dev_err(&spi->dev, "RX overrun\n"); |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 965 | } |
| 966 | if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { |
| 967 | clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 968 | dev_err(&spi->dev, "RX underrun\n"); |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 969 | } |
| 970 | if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { |
| 971 | clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 972 | dev_err(&spi->dev, "TX overrun\n"); |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 973 | } |
| 974 | if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { |
| 975 | clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 976 | dev_err(&spi->dev, "TX underrun\n"); |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 977 | } |
| 978 | |
| 979 | /* Clear the pending irq by setting and then clearing it */ |
| 980 | writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); |
| 981 | writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 982 | |
| 983 | return IRQ_HANDLED; |
| 984 | } |
| 985 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 986 | static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) |
| 987 | { |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 988 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 989 | void __iomem *regs = sdd->regs; |
| 990 | unsigned int val; |
| 991 | |
| 992 | sdd->cur_speed = 0; |
| 993 | |
Mark Brown | 5fc3e83 | 2012-07-19 14:36:23 +0900 | [diff] [blame] | 994 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 995 | |
| 996 | /* Disable Interrupts - we use Polling if not DMA mode */ |
| 997 | writel(0, regs + S3C64XX_SPI_INT_EN); |
| 998 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 999 | if (!sdd->port_conf->clk_from_cmu) |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 1000 | writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1001 | regs + S3C64XX_SPI_CLK_CFG); |
| 1002 | writel(0, regs + S3C64XX_SPI_MODE_CFG); |
| 1003 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); |
| 1004 | |
Girish K S | 375981f | 2013-03-13 12:13:30 +0530 | [diff] [blame] | 1005 | /* Clear any irq pending bits, should set and clear the bits */ |
| 1006 | val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | |
| 1007 | S3C64XX_SPI_PND_RX_UNDERRUN_CLR | |
| 1008 | S3C64XX_SPI_PND_TX_OVERRUN_CLR | |
| 1009 | S3C64XX_SPI_PND_TX_UNDERRUN_CLR; |
| 1010 | writel(val, regs + S3C64XX_SPI_PENDING_CLR); |
| 1011 | writel(0, regs + S3C64XX_SPI_PENDING_CLR); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1012 | |
| 1013 | writel(0, regs + S3C64XX_SPI_SWAP_CFG); |
| 1014 | |
| 1015 | val = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 1016 | val &= ~S3C64XX_SPI_MODE_4BURST; |
| 1017 | val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); |
| 1018 | val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); |
| 1019 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
| 1020 | |
| 1021 | flush_fifo(sdd); |
| 1022 | } |
| 1023 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1024 | #ifdef CONFIG_OF |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 1025 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1026 | { |
| 1027 | struct s3c64xx_spi_info *sci; |
| 1028 | u32 temp; |
| 1029 | |
| 1030 | sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); |
| 1031 | if (!sci) { |
| 1032 | dev_err(dev, "memory allocation for spi_info failed\n"); |
| 1033 | return ERR_PTR(-ENOMEM); |
| 1034 | } |
| 1035 | |
| 1036 | if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 1037 | dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1038 | sci->src_clk_nr = 0; |
| 1039 | } else { |
| 1040 | sci->src_clk_nr = temp; |
| 1041 | } |
| 1042 | |
| 1043 | if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 1044 | dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1045 | sci->num_cs = 1; |
| 1046 | } else { |
| 1047 | sci->num_cs = temp; |
| 1048 | } |
| 1049 | |
| 1050 | return sci; |
| 1051 | } |
| 1052 | #else |
| 1053 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) |
| 1054 | { |
Jingoo Han | 8074cf0 | 2013-07-30 16:58:59 +0900 | [diff] [blame] | 1055 | return dev_get_platdata(dev); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1056 | } |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1057 | #endif |
| 1058 | |
| 1059 | static const struct of_device_id s3c64xx_spi_dt_match[]; |
| 1060 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1061 | static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( |
| 1062 | struct platform_device *pdev) |
| 1063 | { |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1064 | #ifdef CONFIG_OF |
| 1065 | if (pdev->dev.of_node) { |
| 1066 | const struct of_device_id *match; |
| 1067 | match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); |
| 1068 | return (struct s3c64xx_spi_port_config *)match->data; |
| 1069 | } |
| 1070 | #endif |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1071 | return (struct s3c64xx_spi_port_config *) |
| 1072 | platform_get_device_id(pdev)->driver_data; |
| 1073 | } |
| 1074 | |
Grant Likely | 2deff8d | 2013-02-05 13:27:35 +0000 | [diff] [blame] | 1075 | static int s3c64xx_spi_probe(struct platform_device *pdev) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1076 | { |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1077 | struct resource *mem_res; |
Padmavathi Venna | b5be04d | 2013-01-18 17:17:03 +0530 | [diff] [blame] | 1078 | struct resource *res; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1079 | struct s3c64xx_spi_driver_data *sdd; |
Jingoo Han | 8074cf0 | 2013-07-30 16:58:59 +0900 | [diff] [blame] | 1080 | struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1081 | struct spi_master *master; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1082 | int ret, irq; |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1083 | char clk_name[16]; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1084 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1085 | if (!sci && pdev->dev.of_node) { |
| 1086 | sci = s3c64xx_spi_parse_dt(&pdev->dev); |
| 1087 | if (IS_ERR(sci)) |
| 1088 | return PTR_ERR(sci); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1089 | } |
| 1090 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1091 | if (!sci) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1092 | dev_err(&pdev->dev, "platform_data missing!\n"); |
| 1093 | return -ENODEV; |
| 1094 | } |
| 1095 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1096 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1097 | if (mem_res == NULL) { |
| 1098 | dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); |
| 1099 | return -ENXIO; |
| 1100 | } |
| 1101 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1102 | irq = platform_get_irq(pdev, 0); |
| 1103 | if (irq < 0) { |
| 1104 | dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); |
| 1105 | return irq; |
| 1106 | } |
| 1107 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1108 | master = spi_alloc_master(&pdev->dev, |
| 1109 | sizeof(struct s3c64xx_spi_driver_data)); |
| 1110 | if (master == NULL) { |
| 1111 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); |
| 1112 | return -ENOMEM; |
| 1113 | } |
| 1114 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1115 | platform_set_drvdata(pdev, master); |
| 1116 | |
| 1117 | sdd = spi_master_get_devdata(master); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1118 | sdd->port_conf = s3c64xx_spi_get_port_config(pdev); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1119 | sdd->master = master; |
| 1120 | sdd->cntrlr_info = sci; |
| 1121 | sdd->pdev = pdev; |
| 1122 | sdd->sfr_start = mem_res->start; |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 1123 | sdd->cs_gpio = true; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1124 | if (pdev->dev.of_node) { |
Girish K S | 3146bee | 2013-06-21 11:26:12 +0530 | [diff] [blame] | 1125 | if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL)) |
| 1126 | sdd->cs_gpio = false; |
| 1127 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1128 | ret = of_alias_get_id(pdev->dev.of_node, "spi"); |
| 1129 | if (ret < 0) { |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 1130 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", |
| 1131 | ret); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1132 | goto err0; |
| 1133 | } |
| 1134 | sdd->port_id = ret; |
| 1135 | } else { |
| 1136 | sdd->port_id = pdev->id; |
| 1137 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1138 | |
| 1139 | sdd->cur_bpw = 8; |
| 1140 | |
Padmavathi Venna | b5be04d | 2013-01-18 17:17:03 +0530 | [diff] [blame] | 1141 | if (!sdd->pdev->dev.of_node) { |
| 1142 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
| 1143 | if (!res) { |
Jingoo Han | db0606e | 2013-07-15 15:11:57 +0900 | [diff] [blame] | 1144 | dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n"); |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 1145 | sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; |
| 1146 | } else |
| 1147 | sdd->tx_dma.dmach = res->start; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1148 | |
Padmavathi Venna | b5be04d | 2013-01-18 17:17:03 +0530 | [diff] [blame] | 1149 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
| 1150 | if (!res) { |
Jingoo Han | db0606e | 2013-07-15 15:11:57 +0900 | [diff] [blame] | 1151 | dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n"); |
Girish K S | 7e99555 | 2013-05-20 12:21:32 +0530 | [diff] [blame] | 1152 | sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; |
| 1153 | } else |
| 1154 | sdd->rx_dma.dmach = res->start; |
Padmavathi Venna | b5be04d | 2013-01-18 17:17:03 +0530 | [diff] [blame] | 1155 | } |
| 1156 | |
| 1157 | sdd->tx_dma.direction = DMA_MEM_TO_DEV; |
| 1158 | sdd->rx_dma.direction = DMA_DEV_TO_MEM; |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1159 | |
| 1160 | master->dev.of_node = pdev->dev.of_node; |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1161 | master->bus_num = sdd->port_id; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1162 | master->setup = s3c64xx_spi_setup; |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1163 | master->cleanup = s3c64xx_spi_cleanup; |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1164 | master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; |
Mark Brown | 6bb9c0e | 2013-10-05 00:42:58 +0100 | [diff] [blame] | 1165 | master->prepare_message = s3c64xx_spi_prepare_message; |
Mark Brown | 0732a9d | 2013-10-05 11:51:14 +0100 | [diff] [blame] | 1166 | master->transfer_one = s3c64xx_spi_transfer_one; |
Mark Brown | 6bb9c0e | 2013-10-05 00:42:58 +0100 | [diff] [blame] | 1167 | master->unprepare_message = s3c64xx_spi_unprepare_message; |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1168 | master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1169 | master->num_chipselect = sci->num_cs; |
| 1170 | master->dma_alignment = 8; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 1171 | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | |
| 1172 | SPI_BPW_MASK(8); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1173 | /* the spi->mode bits understood by this driver: */ |
| 1174 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
Mark Brown | fc0f81b | 2013-07-28 15:24:54 +0100 | [diff] [blame] | 1175 | master->auto_runtime_pm = true; |
Mark Brown | 3f29588 | 2014-01-16 12:25:46 +0000 | [diff] [blame] | 1176 | if (!is_polling(sdd)) |
| 1177 | master->can_dma = s3c64xx_spi_can_dma; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1178 | |
Thierry Reding | b0ee560 | 2013-01-21 11:09:18 +0100 | [diff] [blame] | 1179 | sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); |
| 1180 | if (IS_ERR(sdd->regs)) { |
| 1181 | ret = PTR_ERR(sdd->regs); |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1182 | goto err0; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1183 | } |
| 1184 | |
Thomas Abraham | 00ab539 | 2013-04-15 20:42:57 -0700 | [diff] [blame] | 1185 | if (sci->cfg_gpio && sci->cfg_gpio()) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1186 | dev_err(&pdev->dev, "Unable to config gpio\n"); |
| 1187 | ret = -EBUSY; |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1188 | goto err0; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1189 | } |
| 1190 | |
| 1191 | /* Setup clocks */ |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1192 | sdd->clk = devm_clk_get(&pdev->dev, "spi"); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1193 | if (IS_ERR(sdd->clk)) { |
| 1194 | dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); |
| 1195 | ret = PTR_ERR(sdd->clk); |
Thomas Abraham | 00ab539 | 2013-04-15 20:42:57 -0700 | [diff] [blame] | 1196 | goto err0; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1197 | } |
| 1198 | |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 1199 | if (clk_prepare_enable(sdd->clk)) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1200 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); |
| 1201 | ret = -EBUSY; |
Thomas Abraham | 00ab539 | 2013-04-15 20:42:57 -0700 | [diff] [blame] | 1202 | goto err0; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1203 | } |
| 1204 | |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1205 | sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1206 | sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1207 | if (IS_ERR(sdd->src_clk)) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1208 | dev_err(&pdev->dev, |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1209 | "Unable to acquire clock '%s'\n", clk_name); |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1210 | ret = PTR_ERR(sdd->src_clk); |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1211 | goto err2; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1212 | } |
| 1213 | |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 1214 | if (clk_prepare_enable(sdd->src_clk)) { |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1215 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1216 | ret = -EBUSY; |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1217 | goto err2; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1218 | } |
| 1219 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1220 | /* Setup Deufult Mode */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1221 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1222 | |
| 1223 | spin_lock_init(&sdd->lock); |
| 1224 | init_completion(&sdd->xfer_completion); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1225 | |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1226 | ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, |
| 1227 | "spi-s3c64xx", sdd); |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1228 | if (ret != 0) { |
| 1229 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", |
| 1230 | irq, ret); |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1231 | goto err3; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1232 | } |
| 1233 | |
| 1234 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | |
| 1235 | S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, |
| 1236 | sdd->regs + S3C64XX_SPI_INT_EN); |
| 1237 | |
Krzysztof Kozlowski | 3833825 | 2013-10-17 18:06:46 +0200 | [diff] [blame] | 1238 | pm_runtime_set_active(&pdev->dev); |
Mark Brown | 3e2bd64 | 2013-09-27 11:52:35 +0100 | [diff] [blame] | 1239 | pm_runtime_enable(&pdev->dev); |
| 1240 | |
Mark Brown | 91800f0 | 2013-08-31 18:55:53 +0100 | [diff] [blame] | 1241 | ret = devm_spi_register_master(&pdev->dev, master); |
| 1242 | if (ret != 0) { |
| 1243 | dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1244 | goto err3; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1245 | } |
| 1246 | |
Jingoo Han | 75bf336 | 2013-01-31 15:25:01 +0900 | [diff] [blame] | 1247 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1248 | sdd->port_id, master->num_chipselect); |
Jingoo Han | c65bc4a | 2013-07-16 08:53:33 +0900 | [diff] [blame] | 1249 | dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tDMA=[Rx-%d, Tx-%d]\n", |
| 1250 | mem_res, |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 1251 | sdd->rx_dma.dmach, sdd->tx_dma.dmach); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1252 | |
| 1253 | return 0; |
| 1254 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1255 | err3: |
Jingoo Han | 4eb7700 | 2013-01-10 11:04:21 +0900 | [diff] [blame] | 1256 | clk_disable_unprepare(sdd->src_clk); |
| 1257 | err2: |
| 1258 | clk_disable_unprepare(sdd->clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1259 | err0: |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1260 | spi_master_put(master); |
| 1261 | |
| 1262 | return ret; |
| 1263 | } |
| 1264 | |
| 1265 | static int s3c64xx_spi_remove(struct platform_device *pdev) |
| 1266 | { |
| 1267 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); |
| 1268 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1269 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1270 | pm_runtime_disable(&pdev->dev); |
| 1271 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1272 | writel(0, sdd->regs + S3C64XX_SPI_INT_EN); |
| 1273 | |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 1274 | clk_disable_unprepare(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1275 | |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 1276 | clk_disable_unprepare(sdd->clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1277 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1278 | return 0; |
| 1279 | } |
| 1280 | |
Jingoo Han | 997230d | 2013-03-22 02:09:08 +0000 | [diff] [blame] | 1281 | #ifdef CONFIG_PM_SLEEP |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1282 | static int s3c64xx_spi_suspend(struct device *dev) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1283 | { |
Guenter Roeck | 9a2a524 | 2012-08-16 20:14:25 -0700 | [diff] [blame] | 1284 | struct spi_master *master = dev_get_drvdata(dev); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1285 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1286 | |
Krzysztof Kozlowski | 347de6b | 2013-10-21 15:42:49 +0200 | [diff] [blame] | 1287 | int ret = spi_master_suspend(master); |
| 1288 | if (ret) |
| 1289 | return ret; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1290 | |
Krzysztof Kozlowski | 9d7fd21 | 2013-10-21 15:42:50 +0200 | [diff] [blame] | 1291 | if (!pm_runtime_suspended(dev)) { |
| 1292 | clk_disable_unprepare(sdd->clk); |
| 1293 | clk_disable_unprepare(sdd->src_clk); |
| 1294 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1295 | |
| 1296 | sdd->cur_speed = 0; /* Output Clock is stopped */ |
| 1297 | |
| 1298 | return 0; |
| 1299 | } |
| 1300 | |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1301 | static int s3c64xx_spi_resume(struct device *dev) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1302 | { |
Guenter Roeck | 9a2a524 | 2012-08-16 20:14:25 -0700 | [diff] [blame] | 1303 | struct spi_master *master = dev_get_drvdata(dev); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1304 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1305 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1306 | |
Thomas Abraham | 00ab539 | 2013-04-15 20:42:57 -0700 | [diff] [blame] | 1307 | if (sci->cfg_gpio) |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1308 | sci->cfg_gpio(); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1309 | |
Krzysztof Kozlowski | 9d7fd21 | 2013-10-21 15:42:50 +0200 | [diff] [blame] | 1310 | if (!pm_runtime_suspended(dev)) { |
| 1311 | clk_prepare_enable(sdd->src_clk); |
| 1312 | clk_prepare_enable(sdd->clk); |
| 1313 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1314 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1315 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1316 | |
Krzysztof Kozlowski | 347de6b | 2013-10-21 15:42:49 +0200 | [diff] [blame] | 1317 | return spi_master_resume(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1318 | } |
Jingoo Han | 997230d | 2013-03-22 02:09:08 +0000 | [diff] [blame] | 1319 | #endif /* CONFIG_PM_SLEEP */ |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1320 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1321 | #ifdef CONFIG_PM_RUNTIME |
| 1322 | static int s3c64xx_spi_runtime_suspend(struct device *dev) |
| 1323 | { |
Guenter Roeck | 9a2a524 | 2012-08-16 20:14:25 -0700 | [diff] [blame] | 1324 | struct spi_master *master = dev_get_drvdata(dev); |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1325 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
| 1326 | |
Thomas Abraham | 9f667bf | 2012-10-03 08:30:12 +0900 | [diff] [blame] | 1327 | clk_disable_unprepare(sdd->clk); |
| 1328 | clk_disable_unprepare(sdd->src_clk); |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1329 | |
| 1330 | return 0; |
| 1331 | } |
| 1332 | |
| 1333 | static int s3c64xx_spi_runtime_resume(struct device *dev) |
| 1334 | { |
Guenter Roeck | 9a2a524 | 2012-08-16 20:14:25 -0700 | [diff] [blame] | 1335 | struct spi_master *master = dev_get_drvdata(dev); |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1336 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Mark Brown | 8b06d5b | 2013-09-27 18:44:53 +0100 | [diff] [blame] | 1337 | int ret; |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1338 | |
Mark Brown | 8b06d5b | 2013-09-27 18:44:53 +0100 | [diff] [blame] | 1339 | ret = clk_prepare_enable(sdd->src_clk); |
| 1340 | if (ret != 0) |
| 1341 | return ret; |
| 1342 | |
| 1343 | ret = clk_prepare_enable(sdd->clk); |
| 1344 | if (ret != 0) { |
| 1345 | clk_disable_unprepare(sdd->src_clk); |
| 1346 | return ret; |
| 1347 | } |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1348 | |
| 1349 | return 0; |
| 1350 | } |
| 1351 | #endif /* CONFIG_PM_RUNTIME */ |
| 1352 | |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1353 | static const struct dev_pm_ops s3c64xx_spi_pm = { |
| 1354 | SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1355 | SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, |
| 1356 | s3c64xx_spi_runtime_resume, NULL) |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1357 | }; |
| 1358 | |
Sachin Kamat | 10ce047 | 2012-08-03 10:08:12 +0530 | [diff] [blame] | 1359 | static struct s3c64xx_spi_port_config s3c2443_spi_port_config = { |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1360 | .fifo_lvl_mask = { 0x7f }, |
| 1361 | .rx_lvl_offset = 13, |
| 1362 | .tx_st_done = 21, |
| 1363 | .high_speed = true, |
| 1364 | }; |
| 1365 | |
Sachin Kamat | 10ce047 | 2012-08-03 10:08:12 +0530 | [diff] [blame] | 1366 | static struct s3c64xx_spi_port_config s3c6410_spi_port_config = { |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1367 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
| 1368 | .rx_lvl_offset = 13, |
| 1369 | .tx_st_done = 21, |
| 1370 | }; |
| 1371 | |
Sachin Kamat | 10ce047 | 2012-08-03 10:08:12 +0530 | [diff] [blame] | 1372 | static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = { |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1373 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
| 1374 | .rx_lvl_offset = 15, |
| 1375 | .tx_st_done = 25, |
| 1376 | }; |
| 1377 | |
Sachin Kamat | 10ce047 | 2012-08-03 10:08:12 +0530 | [diff] [blame] | 1378 | static struct s3c64xx_spi_port_config s5pc100_spi_port_config = { |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1379 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
| 1380 | .rx_lvl_offset = 13, |
| 1381 | .tx_st_done = 21, |
| 1382 | .high_speed = true, |
| 1383 | }; |
| 1384 | |
Sachin Kamat | 10ce047 | 2012-08-03 10:08:12 +0530 | [diff] [blame] | 1385 | static struct s3c64xx_spi_port_config s5pv210_spi_port_config = { |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1386 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
| 1387 | .rx_lvl_offset = 15, |
| 1388 | .tx_st_done = 25, |
| 1389 | .high_speed = true, |
| 1390 | }; |
| 1391 | |
Sachin Kamat | 10ce047 | 2012-08-03 10:08:12 +0530 | [diff] [blame] | 1392 | static struct s3c64xx_spi_port_config exynos4_spi_port_config = { |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1393 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, |
| 1394 | .rx_lvl_offset = 15, |
| 1395 | .tx_st_done = 25, |
| 1396 | .high_speed = true, |
| 1397 | .clk_from_cmu = true, |
| 1398 | }; |
| 1399 | |
Girish K S | bff8203 | 2013-06-21 11:26:13 +0530 | [diff] [blame] | 1400 | static struct s3c64xx_spi_port_config exynos5440_spi_port_config = { |
| 1401 | .fifo_lvl_mask = { 0x1ff }, |
| 1402 | .rx_lvl_offset = 15, |
| 1403 | .tx_st_done = 25, |
| 1404 | .high_speed = true, |
| 1405 | .clk_from_cmu = true, |
| 1406 | .quirks = S3C64XX_SPI_QUIRK_POLL, |
| 1407 | }; |
| 1408 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1409 | static struct platform_device_id s3c64xx_spi_driver_ids[] = { |
| 1410 | { |
| 1411 | .name = "s3c2443-spi", |
| 1412 | .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, |
| 1413 | }, { |
| 1414 | .name = "s3c6410-spi", |
| 1415 | .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, |
| 1416 | }, { |
| 1417 | .name = "s5p64x0-spi", |
| 1418 | .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config, |
| 1419 | }, { |
| 1420 | .name = "s5pc100-spi", |
| 1421 | .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config, |
| 1422 | }, { |
| 1423 | .name = "s5pv210-spi", |
| 1424 | .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config, |
| 1425 | }, { |
| 1426 | .name = "exynos4210-spi", |
| 1427 | .driver_data = (kernel_ulong_t)&exynos4_spi_port_config, |
| 1428 | }, |
| 1429 | { }, |
| 1430 | }; |
| 1431 | |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1432 | static const struct of_device_id s3c64xx_spi_dt_match[] = { |
Mateusz Krawczuk | a3b924d | 2013-09-23 11:45:45 +0200 | [diff] [blame] | 1433 | { .compatible = "samsung,s3c2443-spi", |
| 1434 | .data = (void *)&s3c2443_spi_port_config, |
| 1435 | }, |
| 1436 | { .compatible = "samsung,s3c6410-spi", |
| 1437 | .data = (void *)&s3c6410_spi_port_config, |
| 1438 | }, |
| 1439 | { .compatible = "samsung,s5pc100-spi", |
| 1440 | .data = (void *)&s5pc100_spi_port_config, |
| 1441 | }, |
| 1442 | { .compatible = "samsung,s5pv210-spi", |
| 1443 | .data = (void *)&s5pv210_spi_port_config, |
| 1444 | }, |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1445 | { .compatible = "samsung,exynos4210-spi", |
| 1446 | .data = (void *)&exynos4_spi_port_config, |
| 1447 | }, |
Girish K S | bff8203 | 2013-06-21 11:26:13 +0530 | [diff] [blame] | 1448 | { .compatible = "samsung,exynos5440-spi", |
| 1449 | .data = (void *)&exynos5440_spi_port_config, |
| 1450 | }, |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1451 | { }, |
| 1452 | }; |
| 1453 | MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1454 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1455 | static struct platform_driver s3c64xx_spi_driver = { |
| 1456 | .driver = { |
| 1457 | .name = "s3c64xx-spi", |
| 1458 | .owner = THIS_MODULE, |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1459 | .pm = &s3c64xx_spi_pm, |
Thomas Abraham | 2b90807 | 2012-07-13 07:15:15 +0900 | [diff] [blame] | 1460 | .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1461 | }, |
Lukasz Czerwinski | 50c959f | 2013-09-09 16:09:25 +0200 | [diff] [blame] | 1462 | .probe = s3c64xx_spi_probe, |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1463 | .remove = s3c64xx_spi_remove, |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1464 | .id_table = s3c64xx_spi_driver_ids, |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1465 | }; |
| 1466 | MODULE_ALIAS("platform:s3c64xx-spi"); |
| 1467 | |
Lukasz Czerwinski | 50c959f | 2013-09-09 16:09:25 +0200 | [diff] [blame] | 1468 | module_platform_driver(s3c64xx_spi_driver); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1469 | |
| 1470 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); |
| 1471 | MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); |
| 1472 | MODULE_LICENSE("GPL"); |