Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Avionic Design GmbH |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 3 | * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved. |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
Terje Bergstrom | 4231c6b | 2013-03-22 16:34:05 +0200 | [diff] [blame] | 10 | #ifndef HOST1X_DRM_H |
| 11 | #define HOST1X_DRM_H 1 |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 12 | |
Thierry Reding | e1e9064 | 2013-09-24 13:59:01 +0200 | [diff] [blame] | 13 | #include <uapi/drm/tegra_drm.h> |
| 14 | #include <linux/host1x.h> |
| 15 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 16 | #include <drm/drmP.h> |
| 17 | #include <drm/drm_crtc_helper.h> |
| 18 | #include <drm/drm_edid.h> |
| 19 | #include <drm/drm_fb_helper.h> |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 20 | #include <drm/drm_fixed.h> |
| 21 | |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 22 | #include "gem.h" |
| 23 | |
Stephen Warren | ca48080 | 2013-11-06 16:20:54 -0700 | [diff] [blame] | 24 | struct reset_control; |
| 25 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 26 | struct tegra_fb { |
| 27 | struct drm_framebuffer base; |
| 28 | struct tegra_bo **planes; |
| 29 | unsigned int num_planes; |
| 30 | }; |
| 31 | |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 32 | #ifdef CONFIG_DRM_TEGRA_FBDEV |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 33 | struct tegra_fbdev { |
| 34 | struct drm_fb_helper base; |
| 35 | struct tegra_fb *fb; |
| 36 | }; |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 37 | #endif |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 38 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 39 | struct tegra_drm { |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 40 | struct drm_device *drm; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 41 | |
| 42 | struct mutex clients_lock; |
| 43 | struct list_head clients; |
| 44 | |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 45 | #ifdef CONFIG_DRM_TEGRA_FBDEV |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 46 | struct tegra_fbdev *fbdev; |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 47 | #endif |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 48 | |
| 49 | unsigned int pitch_align; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 50 | }; |
| 51 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 52 | struct tegra_drm_client; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 53 | |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 54 | struct tegra_drm_context { |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 55 | struct tegra_drm_client *client; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 56 | struct host1x_channel *channel; |
| 57 | struct list_head list; |
| 58 | }; |
| 59 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 60 | struct tegra_drm_client_ops { |
| 61 | int (*open_channel)(struct tegra_drm_client *client, |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 62 | struct tegra_drm_context *context); |
| 63 | void (*close_channel)(struct tegra_drm_context *context); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 64 | int (*is_addr_reg)(struct device *dev, u32 class, u32 offset); |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 65 | int (*submit)(struct tegra_drm_context *context, |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 66 | struct drm_tegra_submit *args, struct drm_device *drm, |
| 67 | struct drm_file *file); |
| 68 | }; |
| 69 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 70 | int tegra_drm_submit(struct tegra_drm_context *context, |
| 71 | struct drm_tegra_submit *args, struct drm_device *drm, |
| 72 | struct drm_file *file); |
| 73 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 74 | struct tegra_drm_client { |
| 75 | struct host1x_client base; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 76 | struct list_head list; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 77 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 78 | const struct tegra_drm_client_ops *ops; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 79 | }; |
| 80 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 81 | static inline struct tegra_drm_client * |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 82 | host1x_to_drm_client(struct host1x_client *client) |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 83 | { |
| 84 | return container_of(client, struct tegra_drm_client, base); |
| 85 | } |
| 86 | |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 87 | int tegra_drm_register_client(struct tegra_drm *tegra, |
| 88 | struct tegra_drm_client *client); |
| 89 | int tegra_drm_unregister_client(struct tegra_drm *tegra, |
| 90 | struct tegra_drm_client *client); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 91 | |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 92 | int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm); |
| 93 | int tegra_drm_exit(struct tegra_drm *tegra); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 94 | |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 95 | struct tegra_dc_soc_info; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 96 | struct tegra_output; |
| 97 | |
| 98 | struct tegra_dc { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 99 | struct host1x_client client; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 100 | struct device *dev; |
Thierry Reding | d18d303 | 2013-09-26 16:09:19 +0200 | [diff] [blame] | 101 | spinlock_t lock; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 102 | |
| 103 | struct drm_crtc base; |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 104 | int powergate; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 105 | int pipe; |
| 106 | |
| 107 | struct clk *clk; |
Stephen Warren | ca48080 | 2013-11-06 16:20:54 -0700 | [diff] [blame] | 108 | struct reset_control *rst; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 109 | void __iomem *regs; |
| 110 | int irq; |
| 111 | |
| 112 | struct tegra_output *rgb; |
| 113 | |
| 114 | struct list_head list; |
| 115 | |
| 116 | struct drm_info_list *debugfs_files; |
| 117 | struct drm_minor *minor; |
| 118 | struct dentry *debugfs; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 119 | |
| 120 | /* page-flip handling */ |
| 121 | struct drm_pending_vblank_event *event; |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 122 | |
| 123 | const struct tegra_dc_soc_info *soc; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 124 | }; |
| 125 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 126 | static inline struct tegra_dc * |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 127 | host1x_client_to_dc(struct host1x_client *client) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 128 | { |
| 129 | return container_of(client, struct tegra_dc, client); |
| 130 | } |
| 131 | |
| 132 | static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) |
| 133 | { |
Thierry Reding | 3782651 | 2013-11-08 12:30:37 +0100 | [diff] [blame] | 134 | return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long value, |
| 138 | unsigned long reg) |
| 139 | { |
| 140 | writel(value, dc->regs + (reg << 2)); |
| 141 | } |
| 142 | |
| 143 | static inline unsigned long tegra_dc_readl(struct tegra_dc *dc, |
| 144 | unsigned long reg) |
| 145 | { |
| 146 | return readl(dc->regs + (reg << 2)); |
| 147 | } |
| 148 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 149 | struct tegra_dc_window { |
| 150 | struct { |
| 151 | unsigned int x; |
| 152 | unsigned int y; |
| 153 | unsigned int w; |
| 154 | unsigned int h; |
| 155 | } src; |
| 156 | struct { |
| 157 | unsigned int x; |
| 158 | unsigned int y; |
| 159 | unsigned int w; |
| 160 | unsigned int h; |
| 161 | } dst; |
| 162 | unsigned int bits_per_pixel; |
| 163 | unsigned int format; |
Thierry Reding | f925390 | 2014-01-29 20:31:17 +0100 | [diff] [blame] | 164 | unsigned int swap; |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 165 | unsigned int stride[2]; |
| 166 | unsigned long base[3]; |
Thierry Reding | db7fbdf | 2013-10-07 09:47:58 +0200 | [diff] [blame] | 167 | bool bottom_up; |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 168 | |
| 169 | struct tegra_bo_tiling tiling; |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 170 | }; |
| 171 | |
| 172 | /* from dc.c */ |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 173 | void tegra_dc_enable_vblank(struct tegra_dc *dc); |
| 174 | void tegra_dc_disable_vblank(struct tegra_dc *dc); |
| 175 | void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 176 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 177 | struct tegra_output_ops { |
| 178 | int (*enable)(struct tegra_output *output); |
| 179 | int (*disable)(struct tegra_output *output); |
| 180 | int (*setup_clock)(struct tegra_output *output, struct clk *clk, |
Thierry Reding | 91eded9 | 2014-03-26 13:32:21 +0100 | [diff] [blame] | 181 | unsigned long pclk, unsigned int *div); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 182 | int (*check_mode)(struct tegra_output *output, |
| 183 | struct drm_display_mode *mode, |
| 184 | enum drm_mode_status *status); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 185 | enum drm_connector_status (*detect)(struct tegra_output *output); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 186 | }; |
| 187 | |
| 188 | enum tegra_output_type { |
| 189 | TEGRA_OUTPUT_RGB, |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 190 | TEGRA_OUTPUT_HDMI, |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 191 | TEGRA_OUTPUT_DSI, |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 192 | TEGRA_OUTPUT_EDP, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 193 | }; |
| 194 | |
| 195 | struct tegra_output { |
| 196 | struct device_node *of_node; |
| 197 | struct device *dev; |
| 198 | |
| 199 | const struct tegra_output_ops *ops; |
| 200 | enum tegra_output_type type; |
| 201 | |
Thierry Reding | 9be7d86 | 2013-08-30 15:22:36 +0200 | [diff] [blame] | 202 | struct drm_panel *panel; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 203 | struct i2c_adapter *ddc; |
| 204 | const struct edid *edid; |
| 205 | unsigned int hpd_irq; |
| 206 | int hpd_gpio; |
| 207 | |
| 208 | struct drm_encoder encoder; |
| 209 | struct drm_connector connector; |
| 210 | }; |
| 211 | |
| 212 | static inline struct tegra_output *encoder_to_output(struct drm_encoder *e) |
| 213 | { |
| 214 | return container_of(e, struct tegra_output, encoder); |
| 215 | } |
| 216 | |
| 217 | static inline struct tegra_output *connector_to_output(struct drm_connector *c) |
| 218 | { |
| 219 | return container_of(c, struct tegra_output, connector); |
| 220 | } |
| 221 | |
| 222 | static inline int tegra_output_enable(struct tegra_output *output) |
| 223 | { |
| 224 | if (output && output->ops && output->ops->enable) |
| 225 | return output->ops->enable(output); |
| 226 | |
| 227 | return output ? -ENOSYS : -EINVAL; |
| 228 | } |
| 229 | |
| 230 | static inline int tegra_output_disable(struct tegra_output *output) |
| 231 | { |
| 232 | if (output && output->ops && output->ops->disable) |
| 233 | return output->ops->disable(output); |
| 234 | |
| 235 | return output ? -ENOSYS : -EINVAL; |
| 236 | } |
| 237 | |
| 238 | static inline int tegra_output_setup_clock(struct tegra_output *output, |
Thierry Reding | 91eded9 | 2014-03-26 13:32:21 +0100 | [diff] [blame] | 239 | struct clk *clk, unsigned long pclk, |
| 240 | unsigned int *div) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 241 | { |
| 242 | if (output && output->ops && output->ops->setup_clock) |
Thierry Reding | 91eded9 | 2014-03-26 13:32:21 +0100 | [diff] [blame] | 243 | return output->ops->setup_clock(output, clk, pclk, div); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 244 | |
| 245 | return output ? -ENOSYS : -EINVAL; |
| 246 | } |
| 247 | |
| 248 | static inline int tegra_output_check_mode(struct tegra_output *output, |
| 249 | struct drm_display_mode *mode, |
| 250 | enum drm_mode_status *status) |
| 251 | { |
| 252 | if (output && output->ops && output->ops->check_mode) |
| 253 | return output->ops->check_mode(output, mode, status); |
| 254 | |
| 255 | return output ? -ENOSYS : -EINVAL; |
| 256 | } |
| 257 | |
| 258 | /* from rgb.c */ |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 259 | int tegra_dc_rgb_probe(struct tegra_dc *dc); |
| 260 | int tegra_dc_rgb_remove(struct tegra_dc *dc); |
| 261 | int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); |
| 262 | int tegra_dc_rgb_exit(struct tegra_dc *dc); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 263 | |
| 264 | /* from output.c */ |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 265 | int tegra_output_probe(struct tegra_output *output); |
| 266 | int tegra_output_remove(struct tegra_output *output); |
| 267 | int tegra_output_init(struct drm_device *drm, struct tegra_output *output); |
| 268 | int tegra_output_exit(struct tegra_output *output); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 269 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 270 | /* from dpaux.c */ |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 271 | struct tegra_dpaux; |
| 272 | struct drm_dp_link; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 273 | |
| 274 | struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np); |
| 275 | enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux); |
| 276 | int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output); |
| 277 | int tegra_dpaux_detach(struct tegra_dpaux *dpaux); |
| 278 | int tegra_dpaux_enable(struct tegra_dpaux *dpaux); |
| 279 | int tegra_dpaux_disable(struct tegra_dpaux *dpaux); |
| 280 | int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding); |
| 281 | int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link, |
| 282 | u8 pattern); |
| 283 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 284 | /* from fb.c */ |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 285 | struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer, |
| 286 | unsigned int index); |
Thierry Reding | db7fbdf | 2013-10-07 09:47:58 +0200 | [diff] [blame] | 287 | bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer); |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 288 | int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, |
| 289 | struct tegra_bo_tiling *tiling); |
Thierry Reding | e221532 | 2014-06-27 17:19:25 +0200 | [diff] [blame] | 290 | int tegra_drm_fb_prepare(struct drm_device *drm); |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame^] | 291 | void tegra_drm_fb_free(struct drm_device *drm); |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 292 | int tegra_drm_fb_init(struct drm_device *drm); |
| 293 | void tegra_drm_fb_exit(struct drm_device *drm); |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 294 | #ifdef CONFIG_DRM_TEGRA_FBDEV |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 295 | void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev); |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 296 | #endif |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 297 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 298 | extern struct platform_driver tegra_dc_driver; |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 299 | extern struct platform_driver tegra_dsi_driver; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 300 | extern struct platform_driver tegra_sor_driver; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 301 | extern struct platform_driver tegra_hdmi_driver; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 302 | extern struct platform_driver tegra_dpaux_driver; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 303 | extern struct platform_driver tegra_gr2d_driver; |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 304 | extern struct platform_driver tegra_gr3d_driver; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 305 | |
Terje Bergstrom | 4231c6b | 2013-03-22 16:34:05 +0200 | [diff] [blame] | 306 | #endif /* HOST1X_DRM_H */ |