Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * linux/arch/arm/boot/compressed/head-xscale.S |
| 3 | * |
| 4 | * XScale specific tweaks. This is merged into head.S by the linker. |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #include <linux/config.h> |
| 9 | #include <linux/linkage.h> |
| 10 | #include <asm/mach-types.h> |
| 11 | |
| 12 | .section ".start", "ax" |
| 13 | |
| 14 | __XScale_start: |
| 15 | |
| 16 | @ Preserve r8/r7 i.e. kernel entry values |
| 17 | |
| 18 | @ Data cache might be active. |
| 19 | @ Be sure to flush kernel binary out of the cache, |
| 20 | @ whatever state it is, before it is turned off. |
| 21 | @ This is done by fetching through currently executed |
| 22 | @ memory to be sure we hit the same cache. |
| 23 | bic r2, pc, #0x1f |
| 24 | add r3, r2, #0x10000 @ 64 kb is quite enough... |
| 25 | 1: ldr r0, [r2], #32 |
| 26 | teq r2, r3 |
| 27 | bne 1b |
| 28 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
| 29 | mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches |
| 30 | |
| 31 | @ disabling MMU and caches |
| 32 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
| 33 | bic r0, r0, #0x05 @ clear DC, MMU |
| 34 | bic r0, r0, #0x1000 @ clear Icache |
| 35 | mcr p15, 0, r0, c1, c0, 0 |
| 36 | |
| 37 | #ifdef CONFIG_ARCH_LUBBOCK |
| 38 | mov r7, #MACH_TYPE_LUBBOCK |
| 39 | #endif |
| 40 | |
| 41 | #ifdef CONFIG_ARCH_COTULLA_IDP |
| 42 | mov r7, #MACH_TYPE_COTULLA_IDP |
| 43 | #endif |
| 44 | |
| 45 | #ifdef CONFIG_MACH_GTWX5715 |
| 46 | mov r7, #(MACH_TYPE_GTWX5715 & 0xff) |
| 47 | orr r7, r7, #(MACH_TYPE_GTWX5715 & 0xff00) |
| 48 | #endif |
| 49 | |