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gerrit-public.fairphone.software / kernel / msm-5.4 / 1ffb0be3ad6186b421921de91092917f0b3ee3e2 / . / include / linux / mfd / palmas.h
blob: 98058caa7aca9dba5309ca31672e130ee09ba7fc [file] [log] [blame]
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]1/*
2 * TI Palmas
3 *
Ian Lartey654003e2013-03-22 14:55:12 +0000[diff] [blame]4 * Copyright 2011-2013 Texas Instruments Inc.
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
Ian Lartey654003e2013-03-22 14:55:12 +0000[diff] [blame]7 * Author: Ian Lartey <ian@slimlogic.co.uk>
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef __LINUX_MFD_PALMAS_H
17#define __LINUX_MFD_PALMAS_H
18
19#include <linux/usb/otg.h>
20#include <linux/leds.h>
21#include <linux/regmap.h>
22#include <linux/regulator/driver.h>
23
24#define PALMAS_NUM_CLIENTS 3
25
Ian Lartey654003e2013-03-22 14:55:12 +0000[diff] [blame]26/* The ID_REVISION NUMBERS */
27#define PALMAS_CHIP_OLD_ID 0x0000
28#define PALMAS_CHIP_ID 0xC035
29#define PALMAS_CHIP_CHARGER_ID 0xC036
30
31#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
32 ((a) == PALMAS_CHIP_ID))
33#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
34
J Keerthy1ffb0be2013-06-19 11:27:48 +0530[diff] [blame^]35/**
36 * Palmas PMIC feature types
37 *
38 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
39 * regulator.
40 *
41 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
42 * specific feature (above) or not. Return non-zero, if yes.
43 */
44#define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
45#define PALMAS_PMIC_HAS(b, f) \
46 ((b)->features & PALMAS_PMIC_FEATURE_ ## f)
47
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]48struct palmas_pmic;
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]49struct palmas_gpadc;
50struct palmas_resource;
51struct palmas_usb;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]52
53struct palmas {
54 struct device *dev;
55
56 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
57 struct regmap *regmap[PALMAS_NUM_CLIENTS];
58
59 /* Stored chip id */
60 int id;
61
J Keerthy1ffb0be2013-06-19 11:27:48 +0530[diff] [blame^]62 unsigned int features;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]63 /* IRQ Data */
64 int irq;
65 u32 irq_mask;
66 struct mutex irq_lock;
67 struct regmap_irq_chip_data *irq_data;
68
69 /* Child Devices */
70 struct palmas_pmic *pmic;
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]71 struct palmas_gpadc *gpadc;
72 struct palmas_resource *resource;
73 struct palmas_usb *usb;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]74
75 /* GPIO MUXing */
76 u8 gpio_muxed;
77 u8 led_muxed;
78 u8 pwm_muxed;
79};
80
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]81struct palmas_gpadc_platform_data {
82 /* Channel 3 current source is only enabled during conversion */
83 int ch3_current;
84
85 /* Channel 0 current source can be used for battery detection.
86 * If used for battery detection this will cause a permanent current
87 * consumption depending on current level set here.
88 */
89 int ch0_current;
90
91 /* default BAT_REMOVAL_DAT setting on device probe */
92 int bat_removal;
93
94 /* Sets the START_POLARITY bit in the RT_CTRL register */
95 int start_polarity;
96};
97
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]98struct palmas_reg_init {
99 /* warm_rest controls the voltage levels after a warm reset
100 *
101 * 0: reload default values from OTP on warm reset
102 * 1: maintain voltage from VSEL on warm reset
103 */
104 int warm_reset;
105
106 /* roof_floor controls whether the regulator uses the i2c style
107 * of DVS or uses the method where a GPIO or other control method is
108 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
109 *
110 * For SMPS
111 *
112 * 0: i2c selection of voltage
113 * 1: pin selection of voltage.
114 *
115 * For LDO unused
116 */
117 int roof_floor;
118
119 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
120 * the data sheet.
121 *
122 * For SMPS
123 *
124 * 0: Off
125 * 1: AUTO
126 * 2: ECO
127 * 3: Forced PWM
128 *
129 * For LDO
130 *
131 * 0: Off
132 * 1: On
133 */
134 int mode_sleep;
135
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]136 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
137 * register. Set this is the default voltage set in OTP needs
138 * to be overridden.
139 */
140 u8 vsel;
141
142};
143
Graeme Gregory7cc4c922012-08-28 13:47:39 +0200[diff] [blame]144enum palmas_regulators {
145 /* SMPS regulators */
146 PALMAS_REG_SMPS12,
147 PALMAS_REG_SMPS123,
148 PALMAS_REG_SMPS3,
149 PALMAS_REG_SMPS45,
150 PALMAS_REG_SMPS457,
151 PALMAS_REG_SMPS6,
152 PALMAS_REG_SMPS7,
153 PALMAS_REG_SMPS8,
154 PALMAS_REG_SMPS9,
155 PALMAS_REG_SMPS10,
156 /* LDO regulators */
157 PALMAS_REG_LDO1,
158 PALMAS_REG_LDO2,
159 PALMAS_REG_LDO3,
160 PALMAS_REG_LDO4,
161 PALMAS_REG_LDO5,
162 PALMAS_REG_LDO6,
163 PALMAS_REG_LDO7,
164 PALMAS_REG_LDO8,
165 PALMAS_REG_LDO9,
166 PALMAS_REG_LDOLN,
167 PALMAS_REG_LDOUSB,
Laxman Dewanganaa07f022013-04-17 15:13:12 +0530[diff] [blame]168 /* External regulators */
169 PALMAS_REG_REGEN1,
170 PALMAS_REG_REGEN2,
171 PALMAS_REG_REGEN3,
172 PALMAS_REG_SYSEN1,
173 PALMAS_REG_SYSEN2,
Graeme Gregory7cc4c922012-08-28 13:47:39 +0200[diff] [blame]174 /* Total number of regulators */
175 PALMAS_NUM_REGS,
176};
177
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]178struct palmas_pmic_platform_data {
179 /* An array of pointers to regulator init data indexed by regulator
180 * ID
181 */
Graeme Gregory7cc4c922012-08-28 13:47:39 +0200[diff] [blame]182 struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]183
184 /* An array of pointers to structures containing sleep mode and DVS
185 * configuration for regulators indexed by ID
186 */
Graeme Gregory7cc4c922012-08-28 13:47:39 +0200[diff] [blame]187 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]188
189 /* use LDO6 for vibrator control */
190 int ldo6_vibrator;
Laxman Dewangan17c11a72013-04-17 15:13:13 +0530[diff] [blame]191
192 /* Enable tracking mode of LDO8 */
193 bool enable_ldo8_tracking;
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]194};
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]195
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]196struct palmas_usb_platform_data {
197 /* Set this if platform wishes its own vbus control */
198 int no_control_vbus;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]199
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]200 /* Do we enable the wakeup comparator on probe */
201 int wakeup;
202};
203
204struct palmas_resource_platform_data {
205 int regen1_mode_sleep;
206 int regen2_mode_sleep;
207 int sysen1_mode_sleep;
208 int sysen2_mode_sleep;
209
210 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
211 u8 nsleep_res;
212 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
213 u8 nsleep_smps;
214 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
215 u8 nsleep_ldo1;
216 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
217 u8 nsleep_ldo2;
218
219 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
220 u8 enable1_res;
221 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
222 u8 enable1_smps;
223 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
224 u8 enable1_ldo1;
225 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
226 u8 enable1_ldo2;
227
228 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
229 u8 enable2_res;
230 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
231 u8 enable2_smps;
232 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
233 u8 enable2_ldo1;
234 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
235 u8 enable2_ldo2;
236};
237
238struct palmas_clk_platform_data {
239 int clk32kg_mode_sleep;
240 int clk32kgaudio_mode_sleep;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]241};
242
243struct palmas_platform_data {
Laxman Dewangandf545d12013-03-01 20:13:46 +0530[diff] [blame]244 int irq_flags;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]245 int gpio_base;
246
247 /* bit value to be loaded to the POWER_CTRL register */
248 u8 power_ctrl;
249
250 /*
251 * boolean to select if we want to configure muxing here
252 * then the two value to load into the registers if true
253 */
254 int mux_from_pdata;
255 u8 pad1, pad2;
256
257 struct palmas_pmic_platform_data *pmic_pdata;
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]258 struct palmas_gpadc_platform_data *gpadc_pdata;
259 struct palmas_usb_platform_data *usb_pdata;
260 struct palmas_resource_platform_data *resource_pdata;
261 struct palmas_clk_platform_data *clk_pdata;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]262};
263
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]264struct palmas_gpadc_calibration {
265 s32 gain;
266 s32 gain_error;
267 s32 offset_error;
268};
269
270struct palmas_gpadc {
271 struct device *dev;
272 struct palmas *palmas;
273
274 int ch3_current;
275 int ch0_current;
276
277 int gpadc_force;
278
279 int bat_removal;
280
281 struct mutex reading_lock;
282 struct completion irq_complete;
283
284 int eoc_sw_irq;
285
286 struct palmas_gpadc_calibration *palmas_cal_tbl;
287
288 int conv0_channel;
289 int conv1_channel;
290 int rt_channel;
291};
292
293struct palmas_gpadc_result {
294 s32 raw_code;
295 s32 corrected_code;
296 s32 result;
297};
298
299#define PALMAS_MAX_CHANNELS 16
300
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]301/* Define the palmas IRQ numbers */
302enum palmas_irqs {
303 /* INT1 registers */
304 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
305 PALMAS_PWRON_IRQ,
306 PALMAS_LONG_PRESS_KEY_IRQ,
307 PALMAS_RPWRON_IRQ,
308 PALMAS_PWRDOWN_IRQ,
309 PALMAS_HOTDIE_IRQ,
310 PALMAS_VSYS_MON_IRQ,
311 PALMAS_VBAT_MON_IRQ,
312 /* INT2 registers */
313 PALMAS_RTC_ALARM_IRQ,
314 PALMAS_RTC_TIMER_IRQ,
315 PALMAS_WDT_IRQ,
316 PALMAS_BATREMOVAL_IRQ,
317 PALMAS_RESET_IN_IRQ,
318 PALMAS_FBI_BB_IRQ,
319 PALMAS_SHORT_IRQ,
320 PALMAS_VAC_ACOK_IRQ,
321 /* INT3 registers */
322 PALMAS_GPADC_AUTO_0_IRQ,
323 PALMAS_GPADC_AUTO_1_IRQ,
324 PALMAS_GPADC_EOC_SW_IRQ,
325 PALMAS_GPADC_EOC_RT_IRQ,
326 PALMAS_ID_OTG_IRQ,
327 PALMAS_ID_IRQ,
328 PALMAS_VBUS_OTG_IRQ,
329 PALMAS_VBUS_IRQ,
330 /* INT4 registers */
331 PALMAS_GPIO_0_IRQ,
332 PALMAS_GPIO_1_IRQ,
333 PALMAS_GPIO_2_IRQ,
334 PALMAS_GPIO_3_IRQ,
335 PALMAS_GPIO_4_IRQ,
336 PALMAS_GPIO_5_IRQ,
337 PALMAS_GPIO_6_IRQ,
338 PALMAS_GPIO_7_IRQ,
339 /* Total Number IRQs */
340 PALMAS_NUM_IRQ,
341};
342
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]343struct palmas_pmic {
344 struct palmas *palmas;
345 struct device *dev;
346 struct regulator_desc desc[PALMAS_NUM_REGS];
347 struct regulator_dev *rdev[PALMAS_NUM_REGS];
348 struct mutex mutex;
349
350 int smps123;
351 int smps457;
352
353 int range[PALMAS_REG_SMPS10];
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +0530[diff] [blame]354 unsigned int ramp_delay[PALMAS_REG_SMPS10];
Laxman Dewangan51d3a0c2013-04-18 18:32:48 +0530[diff] [blame]355 unsigned int current_reg_mode[PALMAS_REG_SMPS10];
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]356};
357
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]358struct palmas_resource {
359 struct palmas *palmas;
360 struct device *dev;
361};
362
363struct palmas_usb {
364 struct palmas *palmas;
365 struct device *dev;
366
367 /* for vbus reporting with irqs disabled */
368 spinlock_t lock;
369
370 struct regulator *vbus_reg;
371
372 /* used to set vbus, in atomic path */
373 struct work_struct set_vbus_work;
374
375 int irq1;
376 int irq2;
377 int irq3;
378 int irq4;
379
380 int vbus_enable;
381
382 u8 linkstat;
383};
384
385#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
386
387enum usb_irq_events {
388 /* Wakeup events from INT3 */
389 PALMAS_USB_ID_WAKEPUP,
390 PALMAS_USB_VBUS_WAKEUP,
391
392 /* ID_OTG_EVENTS */
393 PALMAS_USB_ID_GND,
394 N_PALMAS_USB_ID_GND,
395 PALMAS_USB_ID_C,
396 N_PALMAS_USB_ID_C,
397 PALMAS_USB_ID_B,
398 N_PALMAS_USB_ID_B,
399 PALMAS_USB_ID_A,
400 N_PALMAS_USB_ID_A,
401 PALMAS_USB_ID_FLOAT,
402 N_PALMAS_USB_ID_FLOAT,
403
404 /* VBUS_OTG_EVENTS */
405 PALMAS_USB_VB_SESS_END,
406 N_PALMAS_USB_VB_SESS_END,
407 PALMAS_USB_VB_SESS_VLD,
408 N_PALMAS_USB_VB_SESS_VLD,
409 PALMAS_USB_VA_SESS_VLD,
410 N_PALMAS_USB_VA_SESS_VLD,
411 PALMAS_USB_VA_VBUS_VLD,
412 N_PALMAS_USB_VA_VBUS_VLD,
413 PALMAS_USB_VADP_SNS,
414 N_PALMAS_USB_VADP_SNS,
415 PALMAS_USB_VADP_PRB,
416 N_PALMAS_USB_VADP_PRB,
417 PALMAS_USB_VOTG_SESS_VLD,
418 N_PALMAS_USB_VOTG_SESS_VLD,
419};
420
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]421/* defines so we can store the mux settings */
422#define PALMAS_GPIO_0_MUXED (1 << 0)
423#define PALMAS_GPIO_1_MUXED (1 << 1)
424#define PALMAS_GPIO_2_MUXED (1 << 2)
425#define PALMAS_GPIO_3_MUXED (1 << 3)
426#define PALMAS_GPIO_4_MUXED (1 << 4)
427#define PALMAS_GPIO_5_MUXED (1 << 5)
428#define PALMAS_GPIO_6_MUXED (1 << 6)
429#define PALMAS_GPIO_7_MUXED (1 << 7)
430
431#define PALMAS_LED1_MUXED (1 << 0)
432#define PALMAS_LED2_MUXED (1 << 1)
433
434#define PALMAS_PWM1_MUXED (1 << 0)
435#define PALMAS_PWM2_MUXED (1 << 1)
436
437/* helper macro to get correct slave number */
438#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
439#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y)
440
441/* Base addresses of IP blocks in Palmas */
442#define PALMAS_SMPS_DVS_BASE 0x20
443#define PALMAS_RTC_BASE 0x100
444#define PALMAS_VALIDITY_BASE 0x118
445#define PALMAS_SMPS_BASE 0x120
446#define PALMAS_LDO_BASE 0x150
447#define PALMAS_DVFS_BASE 0x180
448#define PALMAS_PMU_CONTROL_BASE 0x1A0
449#define PALMAS_RESOURCE_BASE 0x1D4
450#define PALMAS_PU_PD_OD_BASE 0x1F4
451#define PALMAS_LED_BASE 0x200
452#define PALMAS_INTERRUPT_BASE 0x210
453#define PALMAS_USB_OTG_BASE 0x250
454#define PALMAS_VIBRATOR_BASE 0x270
455#define PALMAS_GPIO_BASE 0x280
456#define PALMAS_USB_BASE 0x290
457#define PALMAS_GPADC_BASE 0x2C0
458#define PALMAS_TRIM_GPADC_BASE 0x3CD
459
460/* Registers for function RTC */
461#define PALMAS_SECONDS_REG 0x0
462#define PALMAS_MINUTES_REG 0x1
463#define PALMAS_HOURS_REG 0x2
464#define PALMAS_DAYS_REG 0x3
465#define PALMAS_MONTHS_REG 0x4
466#define PALMAS_YEARS_REG 0x5
467#define PALMAS_WEEKS_REG 0x6
468#define PALMAS_ALARM_SECONDS_REG 0x8
469#define PALMAS_ALARM_MINUTES_REG 0x9
470#define PALMAS_ALARM_HOURS_REG 0xA
471#define PALMAS_ALARM_DAYS_REG 0xB
472#define PALMAS_ALARM_MONTHS_REG 0xC
473#define PALMAS_ALARM_YEARS_REG 0xD
474#define PALMAS_RTC_CTRL_REG 0x10
475#define PALMAS_RTC_STATUS_REG 0x11
476#define PALMAS_RTC_INTERRUPTS_REG 0x12
477#define PALMAS_RTC_COMP_LSB_REG 0x13
478#define PALMAS_RTC_COMP_MSB_REG 0x14
479#define PALMAS_RTC_RES_PROG_REG 0x15
480#define PALMAS_RTC_RESET_STATUS_REG 0x16
481
482/* Bit definitions for SECONDS_REG */
483#define PALMAS_SECONDS_REG_SEC1_MASK 0x70
484#define PALMAS_SECONDS_REG_SEC1_SHIFT 4
485#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f
486#define PALMAS_SECONDS_REG_SEC0_SHIFT 0
487
488/* Bit definitions for MINUTES_REG */
489#define PALMAS_MINUTES_REG_MIN1_MASK 0x70
490#define PALMAS_MINUTES_REG_MIN1_SHIFT 4
491#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f
492#define PALMAS_MINUTES_REG_MIN0_SHIFT 0
493
494/* Bit definitions for HOURS_REG */
495#define PALMAS_HOURS_REG_PM_NAM 0x80
496#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7
497#define PALMAS_HOURS_REG_HOUR1_MASK 0x30
498#define PALMAS_HOURS_REG_HOUR1_SHIFT 4
499#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f
500#define PALMAS_HOURS_REG_HOUR0_SHIFT 0
501
502/* Bit definitions for DAYS_REG */
503#define PALMAS_DAYS_REG_DAY1_MASK 0x30
504#define PALMAS_DAYS_REG_DAY1_SHIFT 4
505#define PALMAS_DAYS_REG_DAY0_MASK 0x0f
506#define PALMAS_DAYS_REG_DAY0_SHIFT 0
507
508/* Bit definitions for MONTHS_REG */
509#define PALMAS_MONTHS_REG_MONTH1 0x10
510#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4
511#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f
512#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0
513
514/* Bit definitions for YEARS_REG */
515#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
516#define PALMAS_YEARS_REG_YEAR1_SHIFT 4
517#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f
518#define PALMAS_YEARS_REG_YEAR0_SHIFT 0
519
520/* Bit definitions for WEEKS_REG */
521#define PALMAS_WEEKS_REG_WEEK_MASK 0x07
522#define PALMAS_WEEKS_REG_WEEK_SHIFT 0
523
524/* Bit definitions for ALARM_SECONDS_REG */
525#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
526#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4
527#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f
528#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0
529
530/* Bit definitions for ALARM_MINUTES_REG */
531#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
532#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4
533#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f
534#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0
535
536/* Bit definitions for ALARM_HOURS_REG */
537#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
538#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7
539#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
540#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4
541#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f
542#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0
543
544/* Bit definitions for ALARM_DAYS_REG */
545#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
546#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4
547#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f
548#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0
549
550/* Bit definitions for ALARM_MONTHS_REG */
551#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
552#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4
553#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f
554#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0
555
556/* Bit definitions for ALARM_YEARS_REG */
557#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
558#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4
559#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f
560#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0
561
562/* Bit definitions for RTC_CTRL_REG */
563#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
564#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7
565#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
566#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6
567#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
568#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5
569#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
570#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4
571#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
572#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3
573#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
574#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2
575#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
576#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1
577#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
578#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0
579
580/* Bit definitions for RTC_STATUS_REG */
581#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
582#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7
583#define PALMAS_RTC_STATUS_REG_ALARM 0x40
584#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6
585#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
586#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5
587#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
588#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4
589#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
590#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3
591#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
592#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2
593#define PALMAS_RTC_STATUS_REG_RUN 0x02
594#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1
595
596/* Bit definitions for RTC_INTERRUPTS_REG */
597#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
598#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4
599#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
600#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3
601#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
602#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2
603#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
604#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0
605
606/* Bit definitions for RTC_COMP_LSB_REG */
607#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff
608#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0
609
610/* Bit definitions for RTC_COMP_MSB_REG */
611#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff
612#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0
613
614/* Bit definitions for RTC_RES_PROG_REG */
615#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f
616#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0
617
618/* Bit definitions for RTC_RESET_STATUS_REG */
619#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
620#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0
621
622/* Registers for function BACKUP */
623#define PALMAS_BACKUP0 0x0
624#define PALMAS_BACKUP1 0x1
625#define PALMAS_BACKUP2 0x2
626#define PALMAS_BACKUP3 0x3
627#define PALMAS_BACKUP4 0x4
628#define PALMAS_BACKUP5 0x5
629#define PALMAS_BACKUP6 0x6
630#define PALMAS_BACKUP7 0x7
631
632/* Bit definitions for BACKUP0 */
633#define PALMAS_BACKUP0_BACKUP_MASK 0xff
634#define PALMAS_BACKUP0_BACKUP_SHIFT 0
635
636/* Bit definitions for BACKUP1 */
637#define PALMAS_BACKUP1_BACKUP_MASK 0xff
638#define PALMAS_BACKUP1_BACKUP_SHIFT 0
639
640/* Bit definitions for BACKUP2 */
641#define PALMAS_BACKUP2_BACKUP_MASK 0xff
642#define PALMAS_BACKUP2_BACKUP_SHIFT 0
643
644/* Bit definitions for BACKUP3 */
645#define PALMAS_BACKUP3_BACKUP_MASK 0xff
646#define PALMAS_BACKUP3_BACKUP_SHIFT 0
647
648/* Bit definitions for BACKUP4 */
649#define PALMAS_BACKUP4_BACKUP_MASK 0xff
650#define PALMAS_BACKUP4_BACKUP_SHIFT 0
651
652/* Bit definitions for BACKUP5 */
653#define PALMAS_BACKUP5_BACKUP_MASK 0xff
654#define PALMAS_BACKUP5_BACKUP_SHIFT 0
655
656/* Bit definitions for BACKUP6 */
657#define PALMAS_BACKUP6_BACKUP_MASK 0xff
658#define PALMAS_BACKUP6_BACKUP_SHIFT 0
659
660/* Bit definitions for BACKUP7 */
661#define PALMAS_BACKUP7_BACKUP_MASK 0xff
662#define PALMAS_BACKUP7_BACKUP_SHIFT 0
663
664/* Registers for function SMPS */
665#define PALMAS_SMPS12_CTRL 0x0
666#define PALMAS_SMPS12_TSTEP 0x1
667#define PALMAS_SMPS12_FORCE 0x2
668#define PALMAS_SMPS12_VOLTAGE 0x3
669#define PALMAS_SMPS3_CTRL 0x4
670#define PALMAS_SMPS3_VOLTAGE 0x7
671#define PALMAS_SMPS45_CTRL 0x8
672#define PALMAS_SMPS45_TSTEP 0x9
673#define PALMAS_SMPS45_FORCE 0xA
674#define PALMAS_SMPS45_VOLTAGE 0xB
675#define PALMAS_SMPS6_CTRL 0xC
676#define PALMAS_SMPS6_TSTEP 0xD
677#define PALMAS_SMPS6_FORCE 0xE
678#define PALMAS_SMPS6_VOLTAGE 0xF
679#define PALMAS_SMPS7_CTRL 0x10
680#define PALMAS_SMPS7_VOLTAGE 0x13
681#define PALMAS_SMPS8_CTRL 0x14
682#define PALMAS_SMPS8_TSTEP 0x15
683#define PALMAS_SMPS8_FORCE 0x16
684#define PALMAS_SMPS8_VOLTAGE 0x17
685#define PALMAS_SMPS9_CTRL 0x18
686#define PALMAS_SMPS9_VOLTAGE 0x1B
687#define PALMAS_SMPS10_CTRL 0x1C
688#define PALMAS_SMPS10_STATUS 0x1F
689#define PALMAS_SMPS_CTRL 0x24
690#define PALMAS_SMPS_PD_CTRL 0x25
691#define PALMAS_SMPS_DITHER_EN 0x26
692#define PALMAS_SMPS_THERMAL_EN 0x27
693#define PALMAS_SMPS_THERMAL_STATUS 0x28
694#define PALMAS_SMPS_SHORT_STATUS 0x29
695#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
696#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
697#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
698
699/* Bit definitions for SMPS12_CTRL */
700#define PALMAS_SMPS12_CTRL_WR_S 0x80
701#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7
702#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
703#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6
704#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
705#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4
706#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
707#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2
708#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
709#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0
710
711/* Bit definitions for SMPS12_TSTEP */
712#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
713#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0
714
715/* Bit definitions for SMPS12_FORCE */
716#define PALMAS_SMPS12_FORCE_CMD 0x80
717#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7
718#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f
719#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0
720
721/* Bit definitions for SMPS12_VOLTAGE */
722#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
723#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7
724#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f
725#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0
726
727/* Bit definitions for SMPS3_CTRL */
728#define PALMAS_SMPS3_CTRL_WR_S 0x80
729#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7
730#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
731#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4
732#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
733#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2
734#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
735#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0
736
737/* Bit definitions for SMPS3_VOLTAGE */
738#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
739#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7
740#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f
741#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0
742
743/* Bit definitions for SMPS45_CTRL */
744#define PALMAS_SMPS45_CTRL_WR_S 0x80
745#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7
746#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
747#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6
748#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
749#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4
750#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
751#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2
752#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
753#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0
754
755/* Bit definitions for SMPS45_TSTEP */
756#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
757#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0
758
759/* Bit definitions for SMPS45_FORCE */
760#define PALMAS_SMPS45_FORCE_CMD 0x80
761#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7
762#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f
763#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0
764
765/* Bit definitions for SMPS45_VOLTAGE */
766#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
767#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7
768#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f
769#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0
770
771/* Bit definitions for SMPS6_CTRL */
772#define PALMAS_SMPS6_CTRL_WR_S 0x80
773#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7
774#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
775#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6
776#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
777#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4
778#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
779#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2
780#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
781#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0
782
783/* Bit definitions for SMPS6_TSTEP */
784#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
785#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0
786
787/* Bit definitions for SMPS6_FORCE */
788#define PALMAS_SMPS6_FORCE_CMD 0x80
789#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7
790#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f
791#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0
792
793/* Bit definitions for SMPS6_VOLTAGE */
794#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
795#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7
796#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f
797#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0
798
799/* Bit definitions for SMPS7_CTRL */
800#define PALMAS_SMPS7_CTRL_WR_S 0x80
801#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7
802#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
803#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4
804#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
805#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2
806#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
807#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0
808
809/* Bit definitions for SMPS7_VOLTAGE */
810#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
811#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7
812#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f
813#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0
814
815/* Bit definitions for SMPS8_CTRL */
816#define PALMAS_SMPS8_CTRL_WR_S 0x80
817#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7
818#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
819#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6
820#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
821#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4
822#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
823#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2
824#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
825#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0
826
827/* Bit definitions for SMPS8_TSTEP */
828#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
829#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0
830
831/* Bit definitions for SMPS8_FORCE */
832#define PALMAS_SMPS8_FORCE_CMD 0x80
833#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7
834#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f
835#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0
836
837/* Bit definitions for SMPS8_VOLTAGE */
838#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
839#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7
840#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f
841#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0
842
843/* Bit definitions for SMPS9_CTRL */
844#define PALMAS_SMPS9_CTRL_WR_S 0x80
845#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7
846#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
847#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4
848#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
849#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2
850#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
851#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0
852
853/* Bit definitions for SMPS9_VOLTAGE */
854#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
855#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7
856#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f
857#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0
858
859/* Bit definitions for SMPS10_CTRL */
860#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
861#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4
862#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f
863#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0
864
865/* Bit definitions for SMPS10_STATUS */
866#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f
867#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0
868
869/* Bit definitions for SMPS_CTRL */
870#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
871#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5
872#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
873#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4
874#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
875#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2
876#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
877#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0
878
879/* Bit definitions for SMPS_PD_CTRL */
880#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
881#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6
882#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
883#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5
884#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
885#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4
886#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
887#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3
888#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
889#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2
890#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
891#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1
892#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
893#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0
894
895/* Bit definitions for SMPS_THERMAL_EN */
896#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
897#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6
898#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
899#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5
900#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
901#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3
902#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
903#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2
904#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
905#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0
906
907/* Bit definitions for SMPS_THERMAL_STATUS */
908#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
909#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6
910#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
911#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5
912#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
913#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3
914#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
915#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2
916#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
917#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0
918
919/* Bit definitions for SMPS_SHORT_STATUS */
920#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
921#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7
922#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
923#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6
924#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
925#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5
926#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
927#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4
928#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
929#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3
930#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
931#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2
932#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
933#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1
934#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
935#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0
936
937/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
938#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
939#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6
940#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
941#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5
942#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
943#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4
944#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
945#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3
946#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
947#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2
948#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
949#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1
950#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
951#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0
952
953/* Bit definitions for SMPS_POWERGOOD_MASK1 */
954#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
955#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7
956#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
957#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6
958#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
959#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5
960#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
961#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4
962#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
963#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3
964#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
965#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2
966#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
967#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1
968#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
969#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0
970
971/* Bit definitions for SMPS_POWERGOOD_MASK2 */
972#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
973#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
974#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
975#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2
976#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
977#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1
978#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
979#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0
980
981/* Registers for function LDO */
982#define PALMAS_LDO1_CTRL 0x0
983#define PALMAS_LDO1_VOLTAGE 0x1
984#define PALMAS_LDO2_CTRL 0x2
985#define PALMAS_LDO2_VOLTAGE 0x3
986#define PALMAS_LDO3_CTRL 0x4
987#define PALMAS_LDO3_VOLTAGE 0x5
988#define PALMAS_LDO4_CTRL 0x6
989#define PALMAS_LDO4_VOLTAGE 0x7
990#define PALMAS_LDO5_CTRL 0x8
991#define PALMAS_LDO5_VOLTAGE 0x9
992#define PALMAS_LDO6_CTRL 0xA
993#define PALMAS_LDO6_VOLTAGE 0xB
994#define PALMAS_LDO7_CTRL 0xC
995#define PALMAS_LDO7_VOLTAGE 0xD
996#define PALMAS_LDO8_CTRL 0xE
997#define PALMAS_LDO8_VOLTAGE 0xF
998#define PALMAS_LDO9_CTRL 0x10
999#define PALMAS_LDO9_VOLTAGE 0x11
1000#define PALMAS_LDOLN_CTRL 0x12
1001#define PALMAS_LDOLN_VOLTAGE 0x13
1002#define PALMAS_LDOUSB_CTRL 0x14
1003#define PALMAS_LDOUSB_VOLTAGE 0x15
1004#define PALMAS_LDO_CTRL 0x1A
1005#define PALMAS_LDO_PD_CTRL1 0x1B
1006#define PALMAS_LDO_PD_CTRL2 0x1C
1007#define PALMAS_LDO_SHORT_STATUS1 0x1D
1008#define PALMAS_LDO_SHORT_STATUS2 0x1E
1009
1010/* Bit definitions for LDO1_CTRL */
1011#define PALMAS_LDO1_CTRL_WR_S 0x80
1012#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7
1013#define PALMAS_LDO1_CTRL_STATUS 0x10
1014#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4
1015#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
1016#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2
1017#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
1018#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0
1019
1020/* Bit definitions for LDO1_VOLTAGE */
1021#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f
1022#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0
1023
1024/* Bit definitions for LDO2_CTRL */
1025#define PALMAS_LDO2_CTRL_WR_S 0x80
1026#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7
1027#define PALMAS_LDO2_CTRL_STATUS 0x10
1028#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4
1029#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
1030#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2
1031#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
1032#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0
1033
1034/* Bit definitions for LDO2_VOLTAGE */
1035#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f
1036#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0
1037
1038/* Bit definitions for LDO3_CTRL */
1039#define PALMAS_LDO3_CTRL_WR_S 0x80
1040#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7
1041#define PALMAS_LDO3_CTRL_STATUS 0x10
1042#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4
1043#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
1044#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2
1045#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
1046#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0
1047
1048/* Bit definitions for LDO3_VOLTAGE */
1049#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f
1050#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0
1051
1052/* Bit definitions for LDO4_CTRL */
1053#define PALMAS_LDO4_CTRL_WR_S 0x80
1054#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7
1055#define PALMAS_LDO4_CTRL_STATUS 0x10
1056#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4
1057#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
1058#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2
1059#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
1060#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0
1061
1062/* Bit definitions for LDO4_VOLTAGE */
1063#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f
1064#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0
1065
1066/* Bit definitions for LDO5_CTRL */
1067#define PALMAS_LDO5_CTRL_WR_S 0x80
1068#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7
1069#define PALMAS_LDO5_CTRL_STATUS 0x10
1070#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4
1071#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
1072#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2
1073#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
1074#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0
1075
1076/* Bit definitions for LDO5_VOLTAGE */
1077#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f
1078#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0
1079
1080/* Bit definitions for LDO6_CTRL */
1081#define PALMAS_LDO6_CTRL_WR_S 0x80
1082#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7
1083#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
1084#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6
1085#define PALMAS_LDO6_CTRL_STATUS 0x10
1086#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4
1087#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
1088#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2
1089#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
1090#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0
1091
1092/* Bit definitions for LDO6_VOLTAGE */
1093#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f
1094#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0
1095
1096/* Bit definitions for LDO7_CTRL */
1097#define PALMAS_LDO7_CTRL_WR_S 0x80
1098#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7
1099#define PALMAS_LDO7_CTRL_STATUS 0x10
1100#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4
1101#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
1102#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2
1103#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
1104#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0
1105
1106/* Bit definitions for LDO7_VOLTAGE */
1107#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f
1108#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0
1109
1110/* Bit definitions for LDO8_CTRL */
1111#define PALMAS_LDO8_CTRL_WR_S 0x80
1112#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7
1113#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
1114#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6
1115#define PALMAS_LDO8_CTRL_STATUS 0x10
1116#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4
1117#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
1118#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2
1119#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
1120#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0
1121
1122/* Bit definitions for LDO8_VOLTAGE */
1123#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f
1124#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0
1125
1126/* Bit definitions for LDO9_CTRL */
1127#define PALMAS_LDO9_CTRL_WR_S 0x80
1128#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7
1129#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
1130#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6
1131#define PALMAS_LDO9_CTRL_STATUS 0x10
1132#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4
1133#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
1134#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2
1135#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
1136#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0
1137
1138/* Bit definitions for LDO9_VOLTAGE */
1139#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f
1140#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0
1141
1142/* Bit definitions for LDOLN_CTRL */
1143#define PALMAS_LDOLN_CTRL_WR_S 0x80
1144#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7
1145#define PALMAS_LDOLN_CTRL_STATUS 0x10
1146#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4
1147#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
1148#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2
1149#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
1150#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0
1151
1152/* Bit definitions for LDOLN_VOLTAGE */
1153#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f
1154#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0
1155
1156/* Bit definitions for LDOUSB_CTRL */
1157#define PALMAS_LDOUSB_CTRL_WR_S 0x80
1158#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7
1159#define PALMAS_LDOUSB_CTRL_STATUS 0x10
1160#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4
1161#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
1162#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2
1163#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
1164#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0
1165
1166/* Bit definitions for LDOUSB_VOLTAGE */
1167#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f
1168#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0
1169
1170/* Bit definitions for LDO_CTRL */
1171#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
1172#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0
1173
1174/* Bit definitions for LDO_PD_CTRL1 */
1175#define PALMAS_LDO_PD_CTRL1_LDO8 0x80
1176#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7
1177#define PALMAS_LDO_PD_CTRL1_LDO7 0x40
1178#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6
1179#define PALMAS_LDO_PD_CTRL1_LDO6 0x20
1180#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5
1181#define PALMAS_LDO_PD_CTRL1_LDO5 0x10
1182#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4
1183#define PALMAS_LDO_PD_CTRL1_LDO4 0x08
1184#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3
1185#define PALMAS_LDO_PD_CTRL1_LDO3 0x04
1186#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2
1187#define PALMAS_LDO_PD_CTRL1_LDO2 0x02
1188#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1
1189#define PALMAS_LDO_PD_CTRL1_LDO1 0x01
1190#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0
1191
1192/* Bit definitions for LDO_PD_CTRL2 */
1193#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
1194#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2
1195#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1196#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1
1197#define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1198#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0
1199
1200/* Bit definitions for LDO_SHORT_STATUS1 */
1201#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1202#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7
1203#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1204#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6
1205#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1206#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5
1207#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1208#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4
1209#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1210#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3
1211#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1212#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2
1213#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1214#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1
1215#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1216#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0
1217
1218/* Bit definitions for LDO_SHORT_STATUS2 */
1219#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1220#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3
1221#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1222#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2
1223#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1224#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1
1225#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1226#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0
1227
1228/* Registers for function PMU_CONTROL */
1229#define PALMAS_DEV_CTRL 0x0
1230#define PALMAS_POWER_CTRL 0x1
1231#define PALMAS_VSYS_LO 0x2
1232#define PALMAS_VSYS_MON 0x3
1233#define PALMAS_VBAT_MON 0x4
1234#define PALMAS_WATCHDOG 0x5
1235#define PALMAS_BOOT_STATUS 0x6
1236#define PALMAS_BATTERY_BOUNCE 0x7
1237#define PALMAS_BACKUP_BATTERY_CTRL 0x8
1238#define PALMAS_LONG_PRESS_KEY 0x9
1239#define PALMAS_OSC_THERM_CTRL 0xA
1240#define PALMAS_BATDEBOUNCING 0xB
1241#define PALMAS_SWOFF_HWRST 0xF
1242#define PALMAS_SWOFF_COLDRST 0x10
1243#define PALMAS_SWOFF_STATUS 0x11
1244#define PALMAS_PMU_CONFIG 0x12
1245#define PALMAS_SPARE 0x14
1246#define PALMAS_PMU_SECONDARY_INT 0x15
1247#define PALMAS_SW_REVISION 0x17
1248#define PALMAS_EXT_CHRG_CTRL 0x18
1249#define PALMAS_PMU_SECONDARY_INT2 0x19
1250
1251/* Bit definitions for DEV_CTRL */
1252#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1253#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2
1254#define PALMAS_DEV_CTRL_SW_RST 0x02
1255#define PALMAS_DEV_CTRL_SW_RST_SHIFT 1
1256#define PALMAS_DEV_CTRL_DEV_ON 0x01
1257#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0
1258
1259/* Bit definitions for POWER_CTRL */
1260#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1261#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2
1262#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1263#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1
1264#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1265#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0
1266
1267/* Bit definitions for VSYS_LO */
1268#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f
1269#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0
1270
1271/* Bit definitions for VSYS_MON */
1272#define PALMAS_VSYS_MON_ENABLE 0x80
1273#define PALMAS_VSYS_MON_ENABLE_SHIFT 7
1274#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f
1275#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0
1276
1277/* Bit definitions for VBAT_MON */
1278#define PALMAS_VBAT_MON_ENABLE 0x80
1279#define PALMAS_VBAT_MON_ENABLE_SHIFT 7
1280#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f
1281#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0
1282
1283/* Bit definitions for WATCHDOG */
1284#define PALMAS_WATCHDOG_LOCK 0x20
1285#define PALMAS_WATCHDOG_LOCK_SHIFT 5
1286#define PALMAS_WATCHDOG_ENABLE 0x10
1287#define PALMAS_WATCHDOG_ENABLE_SHIFT 4
1288#define PALMAS_WATCHDOG_MODE 0x08
1289#define PALMAS_WATCHDOG_MODE_SHIFT 3
1290#define PALMAS_WATCHDOG_TIMER_MASK 0x07
1291#define PALMAS_WATCHDOG_TIMER_SHIFT 0
1292
1293/* Bit definitions for BOOT_STATUS */
1294#define PALMAS_BOOT_STATUS_BOOT1 0x02
1295#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1
1296#define PALMAS_BOOT_STATUS_BOOT0 0x01
1297#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0
1298
1299/* Bit definitions for BATTERY_BOUNCE */
1300#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f
1301#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0
1302
1303/* Bit definitions for BACKUP_BATTERY_CTRL */
1304#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1305#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7
1306#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1307#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6
1308#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1309#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5
1310#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1311#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4
1312#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1313#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3
1314#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1315#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1
1316#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1317#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0
1318
1319/* Bit definitions for LONG_PRESS_KEY */
1320#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1321#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7
1322#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1323#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4
1324#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1325#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2
1326#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1327#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0
1328
1329/* Bit definitions for OSC_THERM_CTRL */
1330#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1331#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7
1332#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1333#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6
1334#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1335#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5
1336#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1337#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4
1338#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1339#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2
1340#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1341#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1
1342#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1343#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0
1344
1345/* Bit definitions for BATDEBOUNCING */
1346#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1347#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7
1348#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1349#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3
1350#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1351#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0
1352
1353/* Bit definitions for SWOFF_HWRST */
1354#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1355#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7
1356#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1357#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6
1358#define PALMAS_SWOFF_HWRST_WTD 0x20
1359#define PALMAS_SWOFF_HWRST_WTD_SHIFT 5
1360#define PALMAS_SWOFF_HWRST_TSHUT 0x10
1361#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4
1362#define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1363#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3
1364#define PALMAS_SWOFF_HWRST_SW_RST 0x04
1365#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2
1366#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1367#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1
1368#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1369#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0
1370
1371/* Bit definitions for SWOFF_COLDRST */
1372#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1373#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7
1374#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1375#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6
1376#define PALMAS_SWOFF_COLDRST_WTD 0x20
1377#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5
1378#define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1379#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4
1380#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1381#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3
1382#define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1383#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2
1384#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1385#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1
1386#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1387#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0
1388
1389/* Bit definitions for SWOFF_STATUS */
1390#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1391#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7
1392#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1393#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6
1394#define PALMAS_SWOFF_STATUS_WTD 0x20
1395#define PALMAS_SWOFF_STATUS_WTD_SHIFT 5
1396#define PALMAS_SWOFF_STATUS_TSHUT 0x10
1397#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4
1398#define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1399#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3
1400#define PALMAS_SWOFF_STATUS_SW_RST 0x04
1401#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2
1402#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1403#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1
1404#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1405#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0
1406
1407/* Bit definitions for PMU_CONFIG */
1408#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1409#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6
1410#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1411#define PALMAS_PMU_CONFIG_SPARE_SHIFT 4
1412#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1413#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2
1414#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1415#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1
1416#define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1417#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0
1418
1419/* Bit definitions for SPARE */
1420#define PALMAS_SPARE_SPARE_MASK 0xf8
1421#define PALMAS_SPARE_SPARE_SHIFT 3
1422#define PALMAS_SPARE_REGEN3_OD 0x04
1423#define PALMAS_SPARE_REGEN3_OD_SHIFT 2
1424#define PALMAS_SPARE_REGEN2_OD 0x02
1425#define PALMAS_SPARE_REGEN2_OD_SHIFT 1
1426#define PALMAS_SPARE_REGEN1_OD 0x01
1427#define PALMAS_SPARE_REGEN1_OD_SHIFT 0
1428
1429/* Bit definitions for PMU_SECONDARY_INT */
1430#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1431#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7
1432#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1433#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6
1434#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1435#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5
1436#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1437#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4
1438#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1439#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3
1440#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1441#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2
1442#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1443#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1
1444#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1445#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0
1446
1447/* Bit definitions for SW_REVISION */
1448#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff
1449#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0
1450
1451/* Bit definitions for EXT_CHRG_CTRL */
1452#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1453#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7
1454#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1455#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6
1456#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1457#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3
1458#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1459#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2
1460#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1461#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1
1462#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1463#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0
1464
1465/* Bit definitions for PMU_SECONDARY_INT2 */
1466#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1467#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5
1468#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1469#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4
1470#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1471#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1
1472#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1473#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0
1474
1475/* Registers for function RESOURCE */
1476#define PALMAS_CLK32KG_CTRL 0x0
1477#define PALMAS_CLK32KGAUDIO_CTRL 0x1
1478#define PALMAS_REGEN1_CTRL 0x2
1479#define PALMAS_REGEN2_CTRL 0x3
1480#define PALMAS_SYSEN1_CTRL 0x4
1481#define PALMAS_SYSEN2_CTRL 0x5
1482#define PALMAS_NSLEEP_RES_ASSIGN 0x6
1483#define PALMAS_NSLEEP_SMPS_ASSIGN 0x7
1484#define PALMAS_NSLEEP_LDO_ASSIGN1 0x8
1485#define PALMAS_NSLEEP_LDO_ASSIGN2 0x9
1486#define PALMAS_ENABLE1_RES_ASSIGN 0xA
1487#define PALMAS_ENABLE1_SMPS_ASSIGN 0xB
1488#define PALMAS_ENABLE1_LDO_ASSIGN1 0xC
1489#define PALMAS_ENABLE1_LDO_ASSIGN2 0xD
1490#define PALMAS_ENABLE2_RES_ASSIGN 0xE
1491#define PALMAS_ENABLE2_SMPS_ASSIGN 0xF
1492#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1493#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1494#define PALMAS_REGEN3_CTRL 0x12
1495
1496/* Bit definitions for CLK32KG_CTRL */
1497#define PALMAS_CLK32KG_CTRL_STATUS 0x10
1498#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4
1499#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1500#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2
1501#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1502#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0
1503
1504/* Bit definitions for CLK32KGAUDIO_CTRL */
1505#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1506#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4
1507#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1508#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3
1509#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1510#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2
1511#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1512#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0
1513
1514/* Bit definitions for REGEN1_CTRL */
1515#define PALMAS_REGEN1_CTRL_STATUS 0x10
1516#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4
1517#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1518#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2
1519#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1520#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0
1521
1522/* Bit definitions for REGEN2_CTRL */
1523#define PALMAS_REGEN2_CTRL_STATUS 0x10
1524#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4
1525#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1526#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2
1527#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1528#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0
1529
1530/* Bit definitions for SYSEN1_CTRL */
1531#define PALMAS_SYSEN1_CTRL_STATUS 0x10
1532#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4
1533#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1534#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2
1535#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1536#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0
1537
1538/* Bit definitions for SYSEN2_CTRL */
1539#define PALMAS_SYSEN2_CTRL_STATUS 0x10
1540#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4
1541#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1542#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2
1543#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1544#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0
1545
1546/* Bit definitions for NSLEEP_RES_ASSIGN */
1547#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1548#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6
1549#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1550#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1551#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1552#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4
1553#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1554#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3
1555#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1556#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2
1557#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1558#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1
1559#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1560#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0
1561
1562/* Bit definitions for NSLEEP_SMPS_ASSIGN */
1563#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1564#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7
1565#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1566#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6
1567#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1568#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5
1569#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1570#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4
1571#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1572#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3
1573#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1574#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2
1575#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1576#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1
1577#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1578#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0
1579
1580/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1581#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1582#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7
1583#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1584#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6
1585#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1586#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5
1587#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1588#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4
1589#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1590#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3
1591#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1592#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2
1593#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1594#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1
1595#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1596#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0
1597
1598/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1599#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1600#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2
1601#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1602#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1
1603#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1604#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0
1605
1606/* Bit definitions for ENABLE1_RES_ASSIGN */
1607#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1608#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6
1609#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1610#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1611#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1612#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4
1613#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1614#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3
1615#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1616#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2
1617#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1618#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1
1619#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1620#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0
1621
1622/* Bit definitions for ENABLE1_SMPS_ASSIGN */
1623#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1624#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7
1625#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1626#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6
1627#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1628#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5
1629#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1630#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4
1631#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1632#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3
1633#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1634#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2
1635#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1636#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1
1637#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1638#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0
1639
1640/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1641#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1642#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7
1643#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1644#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6
1645#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1646#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5
1647#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1648#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4
1649#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1650#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3
1651#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1652#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2
1653#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1654#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1
1655#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1656#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0
1657
1658/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1659#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1660#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2
1661#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1662#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1
1663#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1664#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0
1665
1666/* Bit definitions for ENABLE2_RES_ASSIGN */
1667#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1668#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6
1669#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1670#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1671#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1672#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4
1673#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1674#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3
1675#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1676#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2
1677#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1678#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1
1679#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1680#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0
1681
1682/* Bit definitions for ENABLE2_SMPS_ASSIGN */
1683#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1684#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7
1685#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1686#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6
1687#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1688#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5
1689#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1690#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4
1691#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1692#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3
1693#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1694#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2
1695#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1696#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1
1697#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1698#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0
1699
1700/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1701#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1702#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7
1703#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1704#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6
1705#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1706#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5
1707#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1708#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4
1709#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1710#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3
1711#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1712#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2
1713#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1714#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1
1715#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1716#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0
1717
1718/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1719#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1720#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2
1721#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1722#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1
1723#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1724#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0
1725
1726/* Bit definitions for REGEN3_CTRL */
1727#define PALMAS_REGEN3_CTRL_STATUS 0x10
1728#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4
1729#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1730#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2
1731#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1732#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0
1733
1734/* Registers for function PAD_CONTROL */
1735#define PALMAS_PU_PD_INPUT_CTRL1 0x0
1736#define PALMAS_PU_PD_INPUT_CTRL2 0x1
1737#define PALMAS_PU_PD_INPUT_CTRL3 0x2
1738#define PALMAS_OD_OUTPUT_CTRL 0x4
1739#define PALMAS_POLARITY_CTRL 0x5
1740#define PALMAS_PRIMARY_SECONDARY_PAD1 0x6
1741#define PALMAS_PRIMARY_SECONDARY_PAD2 0x7
1742#define PALMAS_I2C_SPI 0x8
1743#define PALMAS_PU_PD_INPUT_CTRL4 0x9
1744#define PALMAS_PRIMARY_SECONDARY_PAD3 0xA
1745
1746/* Bit definitions for PU_PD_INPUT_CTRL1 */
1747#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1748#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6
1749#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1750#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5
1751#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1752#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4
1753#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1754#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2
1755#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1756#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1
1757
1758/* Bit definitions for PU_PD_INPUT_CTRL2 */
1759#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1760#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5
1761#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1762#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4
1763#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1764#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3
1765#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1766#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2
1767#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1768#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1
1769#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1770#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0
1771
1772/* Bit definitions for PU_PD_INPUT_CTRL3 */
1773#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1774#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6
1775#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1776#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4
1777#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1778#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2
1779#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1780#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0
1781
1782/* Bit definitions for OD_OUTPUT_CTRL */
1783#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
1784#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7
1785#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
1786#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6
1787#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
1788#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5
1789#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
1790#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3
1791
1792/* Bit definitions for POLARITY_CTRL */
1793#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
1794#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7
1795#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
1796#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6
1797#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
1798#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5
1799#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
1800#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4
1801#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
1802#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3
1803#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
1804#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2
1805#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
1806#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1
1807#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
1808#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0
1809
1810/* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1811#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
1812#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7
1813#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
1814#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5
1815#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
1816#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3
1817#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
1818#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2
1819#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
1820#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1
1821#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
1822#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0
1823
1824/* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1825#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
1826#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4
1827#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
1828#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3
1829#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
1830#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1
1831#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
1832#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0
1833
1834/* Bit definitions for I2C_SPI */
1835#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
1836#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7
1837#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
1838#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6
1839#define PALMAS_I2C_SPI_ID_I2C2 0x20
1840#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5
1841#define PALMAS_I2C_SPI_I2C_SPI 0x10
1842#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4
1843#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f
1844#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0
1845
1846/* Bit definitions for PU_PD_INPUT_CTRL4 */
1847#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
1848#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6
1849#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
1850#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4
1851#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
1852#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2
1853#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
1854#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0
1855
1856/* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1857#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
1858#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1
1859#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
1860#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0
1861
1862/* Registers for function LED_PWM */
1863#define PALMAS_LED_PERIOD_CTRL 0x0
1864#define PALMAS_LED_CTRL 0x1
1865#define PALMAS_PWM_CTRL1 0x2
1866#define PALMAS_PWM_CTRL2 0x3
1867
1868/* Bit definitions for LED_PERIOD_CTRL */
1869#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
1870#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3
1871#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
1872#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0
1873
1874/* Bit definitions for LED_CTRL */
1875#define PALMAS_LED_CTRL_LED_2_SEQ 0x20
1876#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5
1877#define PALMAS_LED_CTRL_LED_1_SEQ 0x10
1878#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4
1879#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
1880#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2
1881#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
1882#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0
1883
1884/* Bit definitions for PWM_CTRL1 */
1885#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
1886#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1
1887#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
1888#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0
1889
1890/* Bit definitions for PWM_CTRL2 */
1891#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff
1892#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0
1893
1894/* Registers for function INTERRUPT */
1895#define PALMAS_INT1_STATUS 0x0
1896#define PALMAS_INT1_MASK 0x1
1897#define PALMAS_INT1_LINE_STATE 0x2
1898#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3
1899#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4
1900#define PALMAS_INT2_STATUS 0x5
1901#define PALMAS_INT2_MASK 0x6
1902#define PALMAS_INT2_LINE_STATE 0x7
1903#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8
1904#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9
1905#define PALMAS_INT3_STATUS 0xA
1906#define PALMAS_INT3_MASK 0xB
1907#define PALMAS_INT3_LINE_STATE 0xC
1908#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD
1909#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE
1910#define PALMAS_INT4_STATUS 0xF
1911#define PALMAS_INT4_MASK 0x10
1912#define PALMAS_INT4_LINE_STATE 0x11
1913#define PALMAS_INT4_EDGE_DETECT1 0x12
1914#define PALMAS_INT4_EDGE_DETECT2 0x13
1915#define PALMAS_INT_CTRL 0x14
1916
1917/* Bit definitions for INT1_STATUS */
1918#define PALMAS_INT1_STATUS_VBAT_MON 0x80
1919#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7
1920#define PALMAS_INT1_STATUS_VSYS_MON 0x40
1921#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6
1922#define PALMAS_INT1_STATUS_HOTDIE 0x20
1923#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5
1924#define PALMAS_INT1_STATUS_PWRDOWN 0x10
1925#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4
1926#define PALMAS_INT1_STATUS_RPWRON 0x08
1927#define PALMAS_INT1_STATUS_RPWRON_SHIFT 3
1928#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
1929#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2
1930#define PALMAS_INT1_STATUS_PWRON 0x02
1931#define PALMAS_INT1_STATUS_PWRON_SHIFT 1
1932#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
1933#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0
1934
1935/* Bit definitions for INT1_MASK */
1936#define PALMAS_INT1_MASK_VBAT_MON 0x80
1937#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7
1938#define PALMAS_INT1_MASK_VSYS_MON 0x40
1939#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6
1940#define PALMAS_INT1_MASK_HOTDIE 0x20
1941#define PALMAS_INT1_MASK_HOTDIE_SHIFT 5
1942#define PALMAS_INT1_MASK_PWRDOWN 0x10
1943#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4
1944#define PALMAS_INT1_MASK_RPWRON 0x08
1945#define PALMAS_INT1_MASK_RPWRON_SHIFT 3
1946#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
1947#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2
1948#define PALMAS_INT1_MASK_PWRON 0x02
1949#define PALMAS_INT1_MASK_PWRON_SHIFT 1
1950#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
1951#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0
1952
1953/* Bit definitions for INT1_LINE_STATE */
1954#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
1955#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7
1956#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
1957#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6
1958#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
1959#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5
1960#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
1961#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4
1962#define PALMAS_INT1_LINE_STATE_RPWRON 0x08
1963#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3
1964#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
1965#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2
1966#define PALMAS_INT1_LINE_STATE_PWRON 0x02
1967#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1
1968#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
1969#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0
1970
1971/* Bit definitions for INT2_STATUS */
1972#define PALMAS_INT2_STATUS_VAC_ACOK 0x80
1973#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7
1974#define PALMAS_INT2_STATUS_SHORT 0x40
1975#define PALMAS_INT2_STATUS_SHORT_SHIFT 6
1976#define PALMAS_INT2_STATUS_FBI_BB 0x20
1977#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5
1978#define PALMAS_INT2_STATUS_RESET_IN 0x10
1979#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4
1980#define PALMAS_INT2_STATUS_BATREMOVAL 0x08
1981#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3
1982#define PALMAS_INT2_STATUS_WDT 0x04
1983#define PALMAS_INT2_STATUS_WDT_SHIFT 2
1984#define PALMAS_INT2_STATUS_RTC_TIMER 0x02
1985#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1
1986#define PALMAS_INT2_STATUS_RTC_ALARM 0x01
1987#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0
1988
1989/* Bit definitions for INT2_MASK */
1990#define PALMAS_INT2_MASK_VAC_ACOK 0x80
1991#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7
1992#define PALMAS_INT2_MASK_SHORT 0x40
1993#define PALMAS_INT2_MASK_SHORT_SHIFT 6
1994#define PALMAS_INT2_MASK_FBI_BB 0x20
1995#define PALMAS_INT2_MASK_FBI_BB_SHIFT 5
1996#define PALMAS_INT2_MASK_RESET_IN 0x10
1997#define PALMAS_INT2_MASK_RESET_IN_SHIFT 4
1998#define PALMAS_INT2_MASK_BATREMOVAL 0x08
1999#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3
2000#define PALMAS_INT2_MASK_WDT 0x04
2001#define PALMAS_INT2_MASK_WDT_SHIFT 2
2002#define PALMAS_INT2_MASK_RTC_TIMER 0x02
2003#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1
2004#define PALMAS_INT2_MASK_RTC_ALARM 0x01
2005#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0
2006
2007/* Bit definitions for INT2_LINE_STATE */
2008#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
2009#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7
2010#define PALMAS_INT2_LINE_STATE_SHORT 0x40
2011#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6
2012#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
2013#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5
2014#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
2015#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4
2016#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
2017#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3
2018#define PALMAS_INT2_LINE_STATE_WDT 0x04
2019#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2
2020#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
2021#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1
2022#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
2023#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0
2024
2025/* Bit definitions for INT3_STATUS */
2026#define PALMAS_INT3_STATUS_VBUS 0x80
2027#define PALMAS_INT3_STATUS_VBUS_SHIFT 7
2028#define PALMAS_INT3_STATUS_VBUS_OTG 0x40
2029#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6
2030#define PALMAS_INT3_STATUS_ID 0x20
2031#define PALMAS_INT3_STATUS_ID_SHIFT 5
2032#define PALMAS_INT3_STATUS_ID_OTG 0x10
2033#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4
2034#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
2035#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3
2036#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
2037#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2
2038#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
2039#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1
2040#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
2041#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0
2042
2043/* Bit definitions for INT3_MASK */
2044#define PALMAS_INT3_MASK_VBUS 0x80
2045#define PALMAS_INT3_MASK_VBUS_SHIFT 7
2046#define PALMAS_INT3_MASK_VBUS_OTG 0x40
2047#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6
2048#define PALMAS_INT3_MASK_ID 0x20
2049#define PALMAS_INT3_MASK_ID_SHIFT 5
2050#define PALMAS_INT3_MASK_ID_OTG 0x10
2051#define PALMAS_INT3_MASK_ID_OTG_SHIFT 4
2052#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
2053#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3
2054#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
2055#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2
2056#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
2057#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1
2058#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
2059#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0
2060
2061/* Bit definitions for INT3_LINE_STATE */
2062#define PALMAS_INT3_LINE_STATE_VBUS 0x80
2063#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7
2064#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
2065#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6
2066#define PALMAS_INT3_LINE_STATE_ID 0x20
2067#define PALMAS_INT3_LINE_STATE_ID_SHIFT 5
2068#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
2069#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4
2070#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
2071#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3
2072#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
2073#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2
2074#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
2075#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1
2076#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
2077#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0
2078
2079/* Bit definitions for INT4_STATUS */
2080#define PALMAS_INT4_STATUS_GPIO_7 0x80
2081#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7
2082#define PALMAS_INT4_STATUS_GPIO_6 0x40
2083#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6
2084#define PALMAS_INT4_STATUS_GPIO_5 0x20
2085#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5
2086#define PALMAS_INT4_STATUS_GPIO_4 0x10
2087#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4
2088#define PALMAS_INT4_STATUS_GPIO_3 0x08
2089#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3
2090#define PALMAS_INT4_STATUS_GPIO_2 0x04
2091#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2
2092#define PALMAS_INT4_STATUS_GPIO_1 0x02
2093#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1
2094#define PALMAS_INT4_STATUS_GPIO_0 0x01
2095#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0
2096
2097/* Bit definitions for INT4_MASK */
2098#define PALMAS_INT4_MASK_GPIO_7 0x80
2099#define PALMAS_INT4_MASK_GPIO_7_SHIFT 7
2100#define PALMAS_INT4_MASK_GPIO_6 0x40
2101#define PALMAS_INT4_MASK_GPIO_6_SHIFT 6
2102#define PALMAS_INT4_MASK_GPIO_5 0x20
2103#define PALMAS_INT4_MASK_GPIO_5_SHIFT 5
2104#define PALMAS_INT4_MASK_GPIO_4 0x10
2105#define PALMAS_INT4_MASK_GPIO_4_SHIFT 4
2106#define PALMAS_INT4_MASK_GPIO_3 0x08
2107#define PALMAS_INT4_MASK_GPIO_3_SHIFT 3
2108#define PALMAS_INT4_MASK_GPIO_2 0x04
2109#define PALMAS_INT4_MASK_GPIO_2_SHIFT 2
2110#define PALMAS_INT4_MASK_GPIO_1 0x02
2111#define PALMAS_INT4_MASK_GPIO_1_SHIFT 1
2112#define PALMAS_INT4_MASK_GPIO_0 0x01
2113#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0
2114
2115/* Bit definitions for INT4_LINE_STATE */
2116#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
2117#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7
2118#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
2119#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6
2120#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
2121#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5
2122#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
2123#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4
2124#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
2125#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3
2126#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
2127#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2
2128#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
2129#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1
2130#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
2131#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0
2132
2133/* Bit definitions for INT4_EDGE_DETECT1 */
2134#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
2135#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7
2136#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
2137#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6
2138#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
2139#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5
2140#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
2141#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4
2142#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
2143#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3
2144#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
2145#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2
2146#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
2147#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1
2148#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
2149#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0
2150
2151/* Bit definitions for INT4_EDGE_DETECT2 */
2152#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
2153#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7
2154#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
2155#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6
2156#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
2157#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5
2158#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
2159#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4
2160#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
2161#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3
2162#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
2163#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2
2164#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
2165#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1
2166#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
2167#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0
2168
2169/* Bit definitions for INT_CTRL */
2170#define PALMAS_INT_CTRL_INT_PENDING 0x04
2171#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2
2172#define PALMAS_INT_CTRL_INT_CLEAR 0x01
2173#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0
2174
2175/* Registers for function USB_OTG */
2176#define PALMAS_USB_WAKEUP 0x3
2177#define PALMAS_USB_VBUS_CTRL_SET 0x4
2178#define PALMAS_USB_VBUS_CTRL_CLR 0x5
2179#define PALMAS_USB_ID_CTRL_SET 0x6
2180#define PALMAS_USB_ID_CTRL_CLEAR 0x7
2181#define PALMAS_USB_VBUS_INT_SRC 0x8
2182#define PALMAS_USB_VBUS_INT_LATCH_SET 0x9
2183#define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA
2184#define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB
2185#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC
2186#define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD
2187#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE
2188#define PALMAS_USB_ID_INT_SRC 0xF
2189#define PALMAS_USB_ID_INT_LATCH_SET 0x10
2190#define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2191#define PALMAS_USB_ID_INT_EN_LO_SET 0x12
2192#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
2193#define PALMAS_USB_ID_INT_EN_HI_SET 0x14
2194#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2195#define PALMAS_USB_OTG_ADP_CTRL 0x16
2196#define PALMAS_USB_OTG_ADP_HIGH 0x17
2197#define PALMAS_USB_OTG_ADP_LOW 0x18
2198#define PALMAS_USB_OTG_ADP_RISE 0x19
2199#define PALMAS_USB_OTG_REVISION 0x1A
2200
2201/* Bit definitions for USB_WAKEUP */
2202#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2203#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0
2204
2205/* Bit definitions for USB_VBUS_CTRL_SET */
2206#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2207#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7
2208#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2209#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5
2210#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2211#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4
2212#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2213#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3
2214#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2215#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2
2216
2217/* Bit definitions for USB_VBUS_CTRL_CLR */
2218#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2219#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7
2220#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2221#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5
2222#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2223#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4
2224#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2225#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3
2226#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2227#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2
2228
2229/* Bit definitions for USB_ID_CTRL_SET */
2230#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2231#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7
2232#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2233#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6
2234#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2235#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5
2236#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2237#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4
2238#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2239#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3
2240#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2241#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2
2242
2243/* Bit definitions for USB_ID_CTRL_CLEAR */
2244#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2245#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7
2246#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2247#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6
2248#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2249#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5
2250#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2251#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4
2252#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2253#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3
2254#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2255#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2
2256
2257/* Bit definitions for USB_VBUS_INT_SRC */
2258#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2259#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7
2260#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2261#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6
2262#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2263#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5
2264#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2265#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3
2266#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2267#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2
2268#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2269#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1
2270#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2271#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0
2272
2273/* Bit definitions for USB_VBUS_INT_LATCH_SET */
2274#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2275#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7
2276#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2277#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6
2278#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2279#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5
2280#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2281#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4
2282#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2283#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3
2284#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2285#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2
2286#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2287#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1
2288#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2289#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0
2290
2291/* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2292#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2293#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7
2294#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2295#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6
2296#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2297#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5
2298#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2299#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4
2300#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2301#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3
2302#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2303#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2
2304#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2305#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1
2306#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2307#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0
2308
2309/* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2310#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2311#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7
2312#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2313#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6
2314#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2315#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5
2316#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2317#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3
2318#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2319#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2
2320#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2321#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1
2322#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2323#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0
2324
2325/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2326#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2327#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7
2328#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2329#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6
2330#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2331#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5
2332#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2333#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3
2334#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2335#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2
2336#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2337#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1
2338#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2339#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0
2340
2341/* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2342#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2343#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7
2344#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2345#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6
2346#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2347#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5
2348#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2349#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4
2350#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2351#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3
2352#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2353#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2
2354#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2355#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1
2356#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2357#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0
2358
2359/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2360#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2361#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7
2362#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2363#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6
2364#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2365#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5
2366#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2367#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4
2368#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2369#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3
2370#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2371#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2
2372#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2373#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1
2374#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2375#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0
2376
2377/* Bit definitions for USB_ID_INT_SRC */
2378#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2379#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4
2380#define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2381#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3
2382#define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2383#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2
2384#define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2385#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1
2386#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2387#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0
2388
2389/* Bit definitions for USB_ID_INT_LATCH_SET */
2390#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2391#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4
2392#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2393#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3
2394#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2395#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2
2396#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2397#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1
2398#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2399#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0
2400
2401/* Bit definitions for USB_ID_INT_LATCH_CLR */
2402#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2403#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4
2404#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2405#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3
2406#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2407#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2
2408#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2409#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1
2410#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2411#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0
2412
2413/* Bit definitions for USB_ID_INT_EN_LO_SET */
2414#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2415#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4
2416#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2417#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3
2418#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2419#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2
2420#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2421#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1
2422#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2423#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0
2424
2425/* Bit definitions for USB_ID_INT_EN_LO_CLR */
2426#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2427#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4
2428#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2429#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3
2430#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2431#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2
2432#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2433#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1
2434#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2435#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0
2436
2437/* Bit definitions for USB_ID_INT_EN_HI_SET */
2438#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2439#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4
2440#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2441#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3
2442#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2443#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2
2444#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2445#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1
2446#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2447#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0
2448
2449/* Bit definitions for USB_ID_INT_EN_HI_CLR */
2450#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2451#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4
2452#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2453#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3
2454#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2455#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2
2456#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2457#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1
2458#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2459#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0
2460
2461/* Bit definitions for USB_OTG_ADP_CTRL */
2462#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2463#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2
2464#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2465#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0
2466
2467/* Bit definitions for USB_OTG_ADP_HIGH */
2468#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff
2469#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0
2470
2471/* Bit definitions for USB_OTG_ADP_LOW */
2472#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff
2473#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0
2474
2475/* Bit definitions for USB_OTG_ADP_RISE */
2476#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff
2477#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0
2478
2479/* Bit definitions for USB_OTG_REVISION */
2480#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2481#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0
2482
2483/* Registers for function VIBRATOR */
2484#define PALMAS_VIBRA_CTRL 0x0
2485
2486/* Bit definitions for VIBRA_CTRL */
2487#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2488#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1
2489#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2490#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0
2491
2492/* Registers for function GPIO */
2493#define PALMAS_GPIO_DATA_IN 0x0
2494#define PALMAS_GPIO_DATA_DIR 0x1
2495#define PALMAS_GPIO_DATA_OUT 0x2
2496#define PALMAS_GPIO_DEBOUNCE_EN 0x3
2497#define PALMAS_GPIO_CLEAR_DATA_OUT 0x4
2498#define PALMAS_GPIO_SET_DATA_OUT 0x5
2499#define PALMAS_PU_PD_GPIO_CTRL1 0x6
2500#define PALMAS_PU_PD_GPIO_CTRL2 0x7
2501#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8
2502
2503/* Bit definitions for GPIO_DATA_IN */
2504#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2505#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7
2506#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2507#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6
2508#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2509#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5
2510#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2511#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4
2512#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2513#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3
2514#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2515#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2
2516#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2517#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1
2518#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2519#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0
2520
2521/* Bit definitions for GPIO_DATA_DIR */
2522#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2523#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7
2524#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2525#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6
2526#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2527#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5
2528#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2529#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4
2530#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2531#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3
2532#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2533#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2
2534#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2535#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1
2536#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2537#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0
2538
2539/* Bit definitions for GPIO_DATA_OUT */
2540#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2541#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7
2542#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2543#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6
2544#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2545#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5
2546#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2547#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4
2548#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2549#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3
2550#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2551#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2
2552#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2553#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1
2554#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2555#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0
2556
2557/* Bit definitions for GPIO_DEBOUNCE_EN */
2558#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2559#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7
2560#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2561#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6
2562#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2563#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5
2564#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2565#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4
2566#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2567#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3
2568#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2569#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2
2570#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2571#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1
2572#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2573#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0
2574
2575/* Bit definitions for GPIO_CLEAR_DATA_OUT */
2576#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2577#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7
2578#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2579#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6
2580#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2581#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5
2582#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2583#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4
2584#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2585#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3
2586#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2587#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2
2588#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2589#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1
2590#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2591#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0
2592
2593/* Bit definitions for GPIO_SET_DATA_OUT */
2594#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2595#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7
2596#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2597#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6
2598#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2599#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5
2600#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2601#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4
2602#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2603#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3
2604#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2605#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2
2606#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2607#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1
2608#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2609#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0
2610
2611/* Bit definitions for PU_PD_GPIO_CTRL1 */
2612#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2613#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6
2614#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2615#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5
2616#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2617#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4
2618#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2619#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3
2620#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2621#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2
2622#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2623#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0
2624
2625/* Bit definitions for PU_PD_GPIO_CTRL2 */
2626#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2627#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6
2628#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2629#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5
2630#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2631#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4
2632#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2633#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3
2634#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2635#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2
2636#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2637#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1
2638#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2639#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0
2640
2641/* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2642#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2643#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5
2644#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2645#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2
2646#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2647#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1
2648
2649/* Registers for function GPADC */
2650#define PALMAS_GPADC_CTRL1 0x0
2651#define PALMAS_GPADC_CTRL2 0x1
2652#define PALMAS_GPADC_RT_CTRL 0x2
2653#define PALMAS_GPADC_AUTO_CTRL 0x3
2654#define PALMAS_GPADC_STATUS 0x4
2655#define PALMAS_GPADC_RT_SELECT 0x5
2656#define PALMAS_GPADC_RT_CONV0_LSB 0x6
2657#define PALMAS_GPADC_RT_CONV0_MSB 0x7
2658#define PALMAS_GPADC_AUTO_SELECT 0x8
2659#define PALMAS_GPADC_AUTO_CONV0_LSB 0x9
2660#define PALMAS_GPADC_AUTO_CONV0_MSB 0xA
2661#define PALMAS_GPADC_AUTO_CONV1_LSB 0xB
2662#define PALMAS_GPADC_AUTO_CONV1_MSB 0xC
2663#define PALMAS_GPADC_SW_SELECT 0xD
2664#define PALMAS_GPADC_SW_CONV0_LSB 0xE
2665#define PALMAS_GPADC_SW_CONV0_MSB 0xF
2666#define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2667#define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2668#define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2669#define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2670#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2671#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2672
2673/* Bit definitions for GPADC_CTRL1 */
2674#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2675#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6
2676#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2677#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4
2678#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2679#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2
2680#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2681#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1
2682#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2683#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0
2684
2685/* Bit definitions for GPADC_CTRL2 */
2686#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2687#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1
2688
2689/* Bit definitions for GPADC_RT_CTRL */
2690#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2691#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1
2692#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2693#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0
2694
2695/* Bit definitions for GPADC_AUTO_CTRL */
2696#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2697#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7
2698#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2699#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6
2700#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2701#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5
2702#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2703#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4
2704#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f
2705#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0
2706
2707/* Bit definitions for GPADC_STATUS */
2708#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2709#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4
2710
2711/* Bit definitions for GPADC_RT_SELECT */
2712#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2713#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7
2714#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f
2715#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0
2716
2717/* Bit definitions for GPADC_RT_CONV0_LSB */
2718#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff
2719#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0
2720
2721/* Bit definitions for GPADC_RT_CONV0_MSB */
2722#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f
2723#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0
2724
2725/* Bit definitions for GPADC_AUTO_SELECT */
2726#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0
2727#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4
2728#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f
2729#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0
2730
2731/* Bit definitions for GPADC_AUTO_CONV0_LSB */
2732#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff
2733#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0
2734
2735/* Bit definitions for GPADC_AUTO_CONV0_MSB */
2736#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f
2737#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0
2738
2739/* Bit definitions for GPADC_AUTO_CONV1_LSB */
2740#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff
2741#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0
2742
2743/* Bit definitions for GPADC_AUTO_CONV1_MSB */
2744#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f
2745#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0
2746
2747/* Bit definitions for GPADC_SW_SELECT */
2748#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2749#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7
2750#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2751#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4
2752#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f
2753#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0
2754
2755/* Bit definitions for GPADC_SW_CONV0_LSB */
2756#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff
2757#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0
2758
2759/* Bit definitions for GPADC_SW_CONV0_MSB */
2760#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f
2761#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0
2762
2763/* Bit definitions for GPADC_THRES_CONV0_LSB */
2764#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff
2765#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0
2766
2767/* Bit definitions for GPADC_THRES_CONV0_MSB */
2768#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2769#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7
2770#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f
2771#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0
2772
2773/* Bit definitions for GPADC_THRES_CONV1_LSB */
2774#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff
2775#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0
2776
2777/* Bit definitions for GPADC_THRES_CONV1_MSB */
2778#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
2779#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7
2780#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f
2781#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0
2782
2783/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2784#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
2785#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5
2786#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
2787#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4
2788#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f
2789#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0
2790
2791/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2792#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
2793#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7
2794#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f
2795#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0
2796
2797/* Registers for function GPADC */
2798#define PALMAS_GPADC_TRIM1 0x0
2799#define PALMAS_GPADC_TRIM2 0x1
2800#define PALMAS_GPADC_TRIM3 0x2
2801#define PALMAS_GPADC_TRIM4 0x3
2802#define PALMAS_GPADC_TRIM5 0x4
2803#define PALMAS_GPADC_TRIM6 0x5
2804#define PALMAS_GPADC_TRIM7 0x6
2805#define PALMAS_GPADC_TRIM8 0x7
2806#define PALMAS_GPADC_TRIM9 0x8
2807#define PALMAS_GPADC_TRIM10 0x9
2808#define PALMAS_GPADC_TRIM11 0xA
2809#define PALMAS_GPADC_TRIM12 0xB
2810#define PALMAS_GPADC_TRIM13 0xC
2811#define PALMAS_GPADC_TRIM14 0xD
2812#define PALMAS_GPADC_TRIM15 0xE
2813#define PALMAS_GPADC_TRIM16 0xF
2814
Laxman Dewangan60c185f2013-01-03 16:16:58 +0530[diff] [blame]2815static inline int palmas_read(struct palmas *palmas, unsigned int base,
2816 unsigned int reg, unsigned int *val)
2817{
2818 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2819 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2820
2821 return regmap_read(palmas->regmap[slave_id], addr, val);
2822}
2823
2824static inline int palmas_write(struct palmas *palmas, unsigned int base,
2825 unsigned int reg, unsigned int value)
2826{
2827 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2828 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2829
2830 return regmap_write(palmas->regmap[slave_id], addr, value);
2831}
2832
2833static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
2834 unsigned int reg, const void *val, size_t val_count)
2835{
2836 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2837 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2838
2839 return regmap_bulk_write(palmas->regmap[slave_id], addr,
2840 val, val_count);
2841}
2842
2843static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
2844 unsigned int reg, void *val, size_t val_count)
2845{
2846 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2847 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2848
2849 return regmap_bulk_read(palmas->regmap[slave_id], addr,
2850 val, val_count);
2851}
2852
2853static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
2854 unsigned int reg, unsigned int mask, unsigned int val)
2855{
2856 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2857 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2858
2859 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
2860}
2861
2862static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
2863{
2864 return regmap_irq_get_virq(palmas->irq_data, irq);
2865}
2866
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]2867#endif /* __LINUX_MFD_PALMAS_H */