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gerrit-public.fairphone.software / kernel / msm-5.4 / 2076eb6ab8339bf09620a0160be3607bbbb61a50 / . / drivers / message / fusion / lsi / mpi_cnfg.h
blob: 47e13e360c10aea30975a44c18e4f9ca36319288 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2 * Copyright (c) 2000-2005 LSI Logic Corporation.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3 *
4 *
5 * Name: mpi_cnfg.h
6 * Title: MPI Config message, structures, and Pages
7 * Creation Date: July 27, 2000
8 *
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]9 * mpi_cnfg.h Version: 01.05.12
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
17 * 06-06-00 01.00.01 Update version number for 1.0 release.
18 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages.
19 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2
20 * fields to FC_DEVICE_0 page, updated the page version.
21 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in
22 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages
23 * and updated the page versions.
24 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1
25 * page and updated the page version.
26 * Added Information field and _INFO_PARAMS_NEGOTIATED
27 * definitionto SCSI_DEVICE_0 page.
28 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the
29 * page version.
30 * Added BucketsRemaining to LAN_1 page, redefined the
31 * state values, and updated the page version.
32 * Revised bus width definitions in SCSI_PORT_0,
33 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages.
34 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page
35 * version.
36 * Moved FC_DEVICE_0 PageAddress description to spec.
37 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field
38 * widths in IOC_0 page and updated the page version.
39 * 11-02-00 01.01.01 Original release for post 1.0 work
40 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI
41 * Port Page 2, FC Port Page 4, FC Port Page 5
42 * 11-15-00 01.01.02 Interim changes to match proposals
43 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01.
44 * 12-05-00 01.01.04 Modified config page actions.
45 * 01-09-01 01.01.05 Added defines for page address formats.
46 * Data size for Manufacturing pages 2 and 3 no longer
47 * defined here.
48 * Io Unit Page 2 size is fixed at 4 adapters and some
49 * flags were changed.
50 * SCSI Port Page 2 Device Settings modified.
51 * New fields added to FC Port Page 0 and some flags
52 * cleaned up.
53 * Removed impedance flash from FC Port Page 1.
54 * Added FC Port pages 6 and 7.
55 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0.
56 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique.
57 * Added some LinkType defines for FcPortPage0.
58 * 02-20-01 01.01.08 Started using MPI_POINTER.
59 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with
60 * MPI_CONFIG_PAGETYPE_RAID_VOLUME.
61 * Added definitions and structures for IOC Page 2 and
62 * RAID Volume Page 2.
63 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9.
64 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID.
65 * Added VendorId and ProductRevLevel fields to
66 * RAIDVOL2_IM_PHYS_ID struct.
67 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_
68 * defines to make them compatible to MPI version 1.0.
69 * Added structure offset comments.
70 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and
71 * removed some obsolete ones.
72 * Added IO Unit Page 3.
73 * Modified defines for Scsi Port Page 2.
74 * Modified RAID Volume Pages.
75 * 08-08-01 01.02.01 Original release for v1.2 work.
76 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct.
77 * Added defines for the SEP bits in RVP2 VolumeSettings.
78 * Modified the DeviceSettings field in RVP2 to use the
79 * proper structure.
80 * Added defines for SES, SAF-TE, and cross channel for
81 * IOCPage2 CapabilitiesFlags.
82 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE.
83 * Removed define for
84 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE.
85 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT.
86 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035.
87 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY
88 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY.
89 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS,
90 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and
91 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and
92 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED.
93 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED
94 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED.
95 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1.
96 * Added rejected bits to SCSI Device Page 0 Information.
97 * Increased size of ALPA array in FC Port Page 2 by one
98 * and removed a one byte reserved field.
99 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in
100 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering.
101 * Added structures for Manufacturing Page 4, IO Unit
102 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and
103 * RAID PhysDisk Page 0.
104 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.
105 * Modified some of the new defines to make them 32
106 * character unique.
107 * Modified how variable length pages (arrays) are defined.
108 * Added generic defines for hot spare pools and RAID
109 * volume types.
110 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR.
111 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with
112 * related define, and bumped the page version define.
113 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a
114 * reserved byte and added a define.
115 * Added define for
116 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE.
117 * Added new config page: CONFIG_PAGE_IOC_5.
118 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases
119 * fields to CONFIG_PAGE_FC_PORT_0.
120 * Added AltConnector and NumRequestedAliases fields to
121 * CONFIG_PAGE_FC_PORT_1.
122 * Added new config page: CONFIG_PAGE_FC_PORT_10.
123 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines.
124 * Added additional MPI_SCSIDEVPAGE0_NP_ defines.
125 * Added more MPI_SCSIDEVPAGE1_RP_ defines.
126 * Added define for
127 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE.
128 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3.
129 * Modified MPI_FCPORTPAGE5_FLAGS_ defines.
130 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define.
131 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0.
132 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
133 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0.
134 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for
135 * CONFIG_PAGE_FC_PORT_1.
136 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable
137 * an alias.
138 * Added more device id defines.
139 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define.
140 * Added TargetConfig and IDConfig fields to
141 * CONFIG_PAGE_SCSI_PORT_1.
142 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2
143 * to control DV.
144 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
145 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field
146 * with ADISCHardALPA.
147 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define.
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]148 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout
149 * fields and related defines to CONFIG_PAGE_FC_PORT_1.
150 * Added define for
151 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK.
152 * Added new fields to the substructures of
153 * CONFIG_PAGE_FC_PORT_10.
154 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0,
155 * CONFIG_PAGE_SCSI_DEVICE_0, and
156 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for
157 * these pages.
158 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0.
159 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config
160 * pages.
161 * Added a new structure for extended config page header.
162 * Added new extended config pages types and structures for
163 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY.
164 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4
165 * to add a Flags field.
166 * Two new Manufacturing config pages (5 and 6).
167 * Two new bits defined for IO Unit Page 1 Flags field.
168 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields
169 * to specify the BIOS boot device.
170 * Four new Flags bits defined for IO Unit Page 2.
171 * Added IO Unit Page 4.
172 * Added EEDP Flags settings to IOC Page 1.
173 * Added new BIOS Page 1 config page.
174 * 10-05-04 01.05.02 Added define for
175 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE.
176 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and
177 * associated defines.
178 * Added more defines for SAS IO Unit Page 0
179 * DiscoveryStatus field.
180 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK
181 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK.
182 * Added defines for Physical Mapping Modes to SAS IO Unit
183 * Page 2.
184 * Added define for
185 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH.
186 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode.
187 * Added defines for MaxTargetSpinUp to BIOS Page 1.
188 * Added 5 new ControlFlags defines for SAS IO Unit
189 * Page 1.
190 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit
191 * Page 2.
192 * Added AccessStatus field to SAS Device Page 0 and added
193 * new Flags bits for supported SATA features.
194 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID
195 * Volume Page 1, and RAID Physical Disk Page 1.
196 * Replaced IO Unit Page 1 BootTargetID,BootBus, and
197 * BootAdapterNum with reserved field.
198 * Added DataScrubRate and ResyncRate to RAID Volume
199 * Page 0.
200 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT
201 * define.
202 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1
203 * Flags field.
204 * Added Auto Port Config flag define for SAS IOUNIT
205 * Page 1 ControlFlags.
206 * Added Disabled bad Phy define to Expander Page 1
207 * Discovery Info field.
208 * Added SAS/SATA device support to SAS IOUnit Page 1
209 * ControlFlags.
210 * Added Unsupported device to SAS Dev Page 0 Flags field
211 * Added disable use SATA Hash Address for SAS IOUNIT
212 * page 1 in ControlFields.
213 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to
214 * Manufacturing Page 4.
215 * Added new defines for BIOS Page 1 IOCSettings field.
216 * Added ExtDiskIdentifier field to RAID Physical Disk
217 * Page 0.
218 * Added new defines for SAS IO Unit Page 1 ControlFlags
219 * and to SAS Device Page 0 Flags to control SATA devices.
220 * Added defines and structures for the new Log Page 0, a
221 * new type of configuration page.
222 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0.
223 * Added WWID field to RAID Volume Page 1.
224 * Added PhysicalPort field to SAS Expander pages 0 and 1.
225 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1.
226 * Added Enclosure/Slot boot device format to BIOS Page 2.
227 * New status value for RAID Volume Page 0 VolumeStatus
228 * (VolumeState subfield).
229 * New value for RAID Physical Page 0 InactiveStatus.
230 * Added Inactive Volume Member flag RAID Physical Disk
231 * Page 0 PhysDiskStatus field.
232 * New physical mapping mode in SAS IO Unit Page 2.
233 * Added CONFIG_PAGE_SAS_ENCLOSURE_0.
234 * Added Slot and Enclosure fields to SAS Device Page 0.
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]235 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1.
236 * Added more RAID type defines to IOC Page 2.
237 * Added Port Enable Delay settings to BIOS Page 1.
238 * Added Bad Block Table Full define to RAID Volume Page 0.
239 * Added Previous State defines to RAID Physical Disk
240 * Page 0.
241 * Added Max Sata Targets define for DiscoveryStatus field
242 * of SAS IO Unit Page 0.
243 * Added Device Self Test to Control Flags of SAS IO Unit
244 * Page 1.
245 * Added Direct Attach Starting Slot Number define for SAS
246 * IO Unit Page 2.
247 * Added new fields in SAS Device Page 2 for enclosure
248 * mapping.
249 * Added OwnerDevHandle and Flags field to SAS PHY Page 0.
250 * Added IOC GPIO Flags define to SAS Enclosure Page 0.
251 * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT.
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]252 * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from
253 * Manufacturing Page 4.
254 * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit.
255 * Added NumDevsPerEnclosure field to SAS IO Unit page 2.
256 * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP
257 * define.
258 * Added EnclosureHandle field to SAS Expander page 0.
259 * Removed redundant NumTableEntriesProg field from SAS
260 * Expander Page 1.
261 * 08-30-05 01.05.11 Added DeviceID for FC949E and changed the DeviceID for
262 * SAS1078.
263 * Added more defines for Manufacturing Page 4 Flags field.
264 * Added more defines for IOCSettings and added
265 * ExpanderSpinup field to Bios Page 1.
266 * Added postpone SATA Init bit to SAS IO Unit Page 1
267 * ControlFlags.
268 * Changed LogEntry format for Log Page 0.
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]269 * 03-27-06 01.05.12 Added two new Flags defines for Manufacturing Page 4.
270 * Added Manufacturing Page 7.
271 * Added MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING.
272 * Added IOC Page 6.
273 * Added PrevBootDeviceForm field to CONFIG_PAGE_BIOS_2.
274 * Added MaxLBAHigh field to RAID Volume Page 0.
275 * Added Nvdata version fields to SAS IO Unit Page 0.
276 * Added AdditionalControlFlags, MaxTargetPortConnectTime,
277 * ReportDeviceMissingDelay, and IODeviceMissingDelay
278 * fields to SAS IO Unit Page 1.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]279 * --------------------------------------------------------------------------
280 */
281
282#ifndef MPI_CNFG_H
283#define MPI_CNFG_H
284
285
286/*****************************************************************************
287*
288* C o n f i g M e s s a g e a n d S t r u c t u r e s
289*
290*****************************************************************************/
291
292typedef struct _CONFIG_PAGE_HEADER
293{
294 U8 PageVersion; /* 00h */
295 U8 PageLength; /* 01h */
296 U8 PageNumber; /* 02h */
297 U8 PageType; /* 03h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]298} CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]299 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;
300
301typedef union _CONFIG_PAGE_HEADER_UNION
302{
303 ConfigPageHeader_t Struct;
304 U8 Bytes[4];
305 U16 Word16[2];
306 U32 Word32;
307} ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]308 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]309
310typedef struct _CONFIG_EXTENDED_PAGE_HEADER
311{
312 U8 PageVersion; /* 00h */
313 U8 Reserved1; /* 01h */
314 U8 PageNumber; /* 02h */
315 U8 PageType; /* 03h */
316 U16 ExtPageLength; /* 04h */
317 U8 ExtPageType; /* 06h */
318 U8 Reserved2; /* 07h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]319} CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]320 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t;
321
322
323
324/****************************************************************************
325* PageType field values
326****************************************************************************/
327#define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)
328#define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)
329#define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)
330#define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30)
331#define MPI_CONFIG_PAGEATTR_MASK (0xF0)
332
333#define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00)
334#define MPI_CONFIG_PAGETYPE_IOC (0x01)
335#define MPI_CONFIG_PAGETYPE_BIOS (0x02)
336#define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03)
337#define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04)
338#define MPI_CONFIG_PAGETYPE_FC_PORT (0x05)
339#define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06)
340#define MPI_CONFIG_PAGETYPE_LAN (0x07)
341#define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
342#define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09)
343#define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
344#define MPI_CONFIG_PAGETYPE_INBAND (0x0B)
345#define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F)
346#define MPI_CONFIG_PAGETYPE_MASK (0x0F)
347
348#define MPI_CONFIG_TYPENUM_MASK (0x0FFF)
349
350
351/****************************************************************************
352* ExtPageType field values
353****************************************************************************/
354#define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
355#define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
356#define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
357#define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]358#define MPI_CONFIG_EXTPAGETYPE_LOG (0x14)
359#define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]360
361
362/****************************************************************************
363* PageAddress field values
364****************************************************************************/
365#define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF)
366
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]367#define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000)
368#define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]369#define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF)
370#define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0)
371#define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00)
372#define MPI_SCSI_DEVICE_BUS_SHIFT (8)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]373#define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000)
374#define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF)
375#define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0)
376#define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00)
377#define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8)
378#define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000)
379#define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]380
381#define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000)
382#define MPI_FC_PORT_PGAD_PORT_SHIFT (28)
383#define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000)
384#define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000)
385#define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF)
386#define MPI_FC_PORT_PGAD_INDEX_SHIFT (0)
387
388#define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000)
389#define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28)
390#define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000)
391#define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000)
392#define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000)
393#define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28)
394#define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF)
395#define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0)
396#define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000)
397#define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
398#define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8)
399#define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
400#define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0)
401
402#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
403#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0)
404
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]405#define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
406#define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28)
407#define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
408#define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001)
409#define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002)
410#define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF)
411#define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0)
412#define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000)
413#define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16)
414#define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF)
415#define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0)
416#define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF)
417#define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0)
418
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]419#define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
420#define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28)
421#define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
422#define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001)
423#define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002)
424#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
425#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0)
426#define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
427#define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8)
428#define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
429#define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0)
430#define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF)
431#define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0)
432
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]433#define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
434#define MPI_SAS_PHY_PGAD_FORM_SHIFT (28)
435#define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0)
436#define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1)
437#define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
438#define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0)
439#define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
440#define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0)
441
442#define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
443#define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28)
444#define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
445#define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001)
446#define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
447#define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0)
448#define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF)
449#define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0)
450
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]451
452
453/****************************************************************************
454* Config Request Message
455****************************************************************************/
456typedef struct _MSG_CONFIG
457{
458 U8 Action; /* 00h */
459 U8 Reserved; /* 01h */
460 U8 ChainOffset; /* 02h */
461 U8 Function; /* 03h */
462 U16 ExtPageLength; /* 04h */
463 U8 ExtPageType; /* 06h */
464 U8 MsgFlags; /* 07h */
465 U32 MsgContext; /* 08h */
466 U8 Reserved2[8]; /* 0Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]467 CONFIG_PAGE_HEADER Header; /* 14h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]468 U32 PageAddress; /* 18h */
469 SGE_IO_UNION PageBufferSGE; /* 1Ch */
470} MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
471 Config_t, MPI_POINTER pConfig_t;
472
473
474/****************************************************************************
475* Action field values
476****************************************************************************/
477#define MPI_CONFIG_ACTION_PAGE_HEADER (0x00)
478#define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
479#define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
480#define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03)
481#define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
482#define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
483#define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
484
485
486/* Config Reply Message */
487typedef struct _MSG_CONFIG_REPLY
488{
489 U8 Action; /* 00h */
490 U8 Reserved; /* 01h */
491 U8 MsgLength; /* 02h */
492 U8 Function; /* 03h */
493 U16 ExtPageLength; /* 04h */
494 U8 ExtPageType; /* 06h */
495 U8 MsgFlags; /* 07h */
496 U32 MsgContext; /* 08h */
497 U8 Reserved2[2]; /* 0Ch */
498 U16 IOCStatus; /* 0Eh */
499 U32 IOCLogInfo; /* 10h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]500 CONFIG_PAGE_HEADER Header; /* 14h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]501} MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
502 ConfigReply_t, MPI_POINTER pConfigReply_t;
503
504
505
506/*****************************************************************************
507*
508* C o n f i g u r a t i o n P a g e s
509*
510*****************************************************************************/
511
512/****************************************************************************
513* Manufacturing Config pages
514****************************************************************************/
515#define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)
516/* Fibre Channel */
517#define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
518#define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
519#define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
520#define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
521#define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]522#define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642)
523#define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640)
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]524#define MPI_MANUFACTPAGE_DEVICEID_FC949E (0x0646)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]525/* SCSI */
526#define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
527#define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
528#define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
529#define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
530#define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
531#define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
532/* SAS */
533#define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]534#define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C)
535#define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056)
536#define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E)
537#define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A)
538#define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054)
539#define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058)
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]540#define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0062)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]541
542
543typedef struct _CONFIG_PAGE_MANUFACTURING_0
544{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]545 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]546 U8 ChipName[16]; /* 04h */
547 U8 ChipRevision[8]; /* 14h */
548 U8 BoardName[16]; /* 1Ch */
549 U8 BoardAssembly[16]; /* 2Ch */
550 U8 BoardTracerNumber[16]; /* 3Ch */
551
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]552} CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]553 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;
554
555#define MPI_MANUFACTURING0_PAGEVERSION (0x00)
556
557
558typedef struct _CONFIG_PAGE_MANUFACTURING_1
559{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]560 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]561 U8 VPD[256]; /* 04h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]562} CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]563 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;
564
565#define MPI_MANUFACTURING1_PAGEVERSION (0x00)
566
567
568typedef struct _MPI_CHIP_REVISION_ID
569{
570 U16 DeviceID; /* 00h */
571 U8 PCIRevisionID; /* 02h */
572 U8 Reserved; /* 03h */
573} MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID,
574 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t;
575
576
577/*
578 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
579 * one and check Header.PageLength at runtime.
580 */
581#ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
582#define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
583#endif
584
585typedef struct _CONFIG_PAGE_MANUFACTURING_2
586{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]587 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]588 MPI_CHIP_REVISION_ID ChipId; /* 04h */
589 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]590} CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]591 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;
592
593#define MPI_MANUFACTURING2_PAGEVERSION (0x00)
594
595
596/*
597 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
598 * one and check Header.PageLength at runtime.
599 */
600#ifndef MPI_MAN_PAGE_3_INFO_WORDS
601#define MPI_MAN_PAGE_3_INFO_WORDS (1)
602#endif
603
604typedef struct _CONFIG_PAGE_MANUFACTURING_3
605{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]606 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]607 MPI_CHIP_REVISION_ID ChipId; /* 04h */
608 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]609} CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]610 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;
611
612#define MPI_MANUFACTURING3_PAGEVERSION (0x00)
613
614
615typedef struct _CONFIG_PAGE_MANUFACTURING_4
616{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]617 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]618 U32 Reserved1; /* 04h */
619 U8 InfoOffset0; /* 08h */
620 U8 InfoSize0; /* 09h */
621 U8 InfoOffset1; /* 0Ah */
622 U8 InfoSize1; /* 0Bh */
623 U8 InquirySize; /* 0Ch */
624 U8 Flags; /* 0Dh */
625 U16 Reserved2; /* 0Eh */
626 U8 InquiryData[56]; /* 10h */
627 U32 ISVolumeSettings; /* 48h */
628 U32 IMEVolumeSettings; /* 4Ch */
629 U32 IMVolumeSettings; /* 50h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]630 U32 Reserved3; /* 54h */
631 U32 Reserved4; /* 58h */
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]632 U32 Reserved5; /* 5Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]633 U8 IMEDataScrubRate; /* 60h */
634 U8 IMEResyncRate; /* 61h */
635 U16 Reserved6; /* 62h */
636 U8 IMDataScrubRate; /* 64h */
637 U8 IMResyncRate; /* 65h */
638 U16 Reserved7; /* 66h */
639 U32 Reserved8; /* 68h */
640 U32 Reserved9; /* 6Ch */
641} CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]642 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
643
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]644#define MPI_MANUFACTURING4_PAGEVERSION (0x04)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]645
646/* defines for the Flags field */
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]647#define MPI_MANPAGE4_FORCE_BAD_BLOCK_TABLE (0x80)
648#define MPI_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x40)
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]649#define MPI_MANPAGE4_IME_DISABLE (0x20)
650#define MPI_MANPAGE4_IM_DISABLE (0x10)
651#define MPI_MANPAGE4_IS_DISABLE (0x08)
652#define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE (0x04)
653#define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x02)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]654#define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01)
655
656
657typedef struct _CONFIG_PAGE_MANUFACTURING_5
658{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]659 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]660 U64 BaseWWID; /* 04h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]661 U8 Flags; /* 0Ch */
662 U8 Reserved1; /* 0Dh */
663 U16 Reserved2; /* 0Eh */
664} CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]665 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t;
666
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]667#define MPI_MANUFACTURING5_PAGEVERSION (0x01)
668
669/* defines for the Flags field */
670#define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]671
672
673typedef struct _CONFIG_PAGE_MANUFACTURING_6
674{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]675 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]676 U32 ProductSpecificInfo;/* 04h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]677} CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]678 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t;
679
680#define MPI_MANUFACTURING6_PAGEVERSION (0x00)
681
682
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]683typedef struct _MPI_MANPAGE7_CONNECTOR_INFO
684{
685 U32 Pinout; /* 00h */
686 U8 Connector[16]; /* 04h */
687 U8 Location; /* 14h */
688 U8 Reserved1; /* 15h */
689 U16 Slot; /* 16h */
690 U32 Reserved2; /* 18h */
691} MPI_MANPAGE7_CONNECTOR_INFO, MPI_POINTER PTR_MPI_MANPAGE7_CONNECTOR_INFO,
692 MpiManPage7ConnectorInfo_t, MPI_POINTER pMpiManPage7ConnectorInfo_t;
693
694/* defines for the Pinout field */
695#define MPI_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
696#define MPI_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
697#define MPI_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
698#define MPI_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
699#define MPI_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
700#define MPI_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
701#define MPI_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
702#define MPI_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
703#define MPI_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
704#define MPI_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
705
706/* defines for the Location field */
707#define MPI_MANPAGE7_LOCATION_UNKNOWN (0x01)
708#define MPI_MANPAGE7_LOCATION_INTERNAL (0x02)
709#define MPI_MANPAGE7_LOCATION_EXTERNAL (0x04)
710#define MPI_MANPAGE7_LOCATION_SWITCHABLE (0x08)
711#define MPI_MANPAGE7_LOCATION_AUTO (0x10)
712#define MPI_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
713#define MPI_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
714
715/*
716 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
717 * one and check NumPhys at runtime.
718 */
719#ifndef MPI_MANPAGE7_CONNECTOR_INFO_MAX
720#define MPI_MANPAGE7_CONNECTOR_INFO_MAX (1)
721#endif
722
723typedef struct _CONFIG_PAGE_MANUFACTURING_7
724{
725 CONFIG_PAGE_HEADER Header; /* 00h */
726 U32 Reserved1; /* 04h */
727 U32 Reserved2; /* 08h */
728 U32 Flags; /* 0Ch */
729 U8 EnclosureName[16]; /* 10h */
730 U8 NumPhys; /* 20h */
731 U8 Reserved3; /* 21h */
732 U16 Reserved4; /* 22h */
733 MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */
734} CONFIG_PAGE_MANUFACTURING_7, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_7,
735 ManufacturingPage7_t, MPI_POINTER pManufacturingPage7_t;
736
737#define MPI_MANUFACTURING7_PAGEVERSION (0x00)
738
739/* defines for the Flags field */
740#define MPI_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
741
742
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]743/****************************************************************************
744* IO Unit Config Pages
745****************************************************************************/
746
747typedef struct _CONFIG_PAGE_IO_UNIT_0
748{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]749 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]750 U64 UniqueValue; /* 04h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]751} CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]752 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;
753
754#define MPI_IOUNITPAGE0_PAGEVERSION (0x00)
755
756
757typedef struct _CONFIG_PAGE_IO_UNIT_1
758{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]759 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]760 U32 Flags; /* 04h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]761} CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]762 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
763
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]764#define MPI_IOUNITPAGE1_PAGEVERSION (0x02)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]765
766/* IO Unit Page 1 Flags defines */
767#define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
768#define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)
769#define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)
770#define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
771#define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
772#define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020)
773#define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)
774#define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)
775#define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]776#define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]777
778typedef struct _MPI_ADAPTER_INFO
779{
780 U8 PciBusNumber; /* 00h */
781 U8 PciDeviceAndFunctionNumber; /* 01h */
782 U16 AdapterFlags; /* 02h */
783} MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
784 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
785
786#define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
787#define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
788
789typedef struct _CONFIG_PAGE_IO_UNIT_2
790{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]791 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]792 U32 Flags; /* 04h */
793 U32 BiosVersion; /* 08h */
794 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]795 U32 Reserved1; /* 1Ch */
796} CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]797 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
798
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]799#define MPI_IOUNITPAGE2_PAGEVERSION (0x02)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]800
801#define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)
802#define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)
803#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
804#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)
805
806#define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
807#define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
808#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020)
809#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
810
811
812/*
813 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
814 * one and check Header.PageLength at runtime.
815 */
816#ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
817#define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
818#endif
819
820typedef struct _CONFIG_PAGE_IO_UNIT_3
821{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]822 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]823 U8 GPIOCount; /* 04h */
824 U8 Reserved1; /* 05h */
825 U16 Reserved2; /* 06h */
826 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]827} CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]828 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;
829
830#define MPI_IOUNITPAGE3_PAGEVERSION (0x01)
831
832#define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)
833#define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
834#define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)
835#define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)
836
837
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]838typedef struct _CONFIG_PAGE_IO_UNIT_4
839{
840 CONFIG_PAGE_HEADER Header; /* 00h */
841 U32 Reserved1; /* 04h */
842 SGE_SIMPLE_UNION FWImageSGE; /* 08h */
843} CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4,
844 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t;
845
846#define MPI_IOUNITPAGE4_PAGEVERSION (0x00)
847
848
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]849/****************************************************************************
850* IOC Config Pages
851****************************************************************************/
852
853typedef struct _CONFIG_PAGE_IOC_0
854{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]855 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]856 U32 TotalNVStore; /* 04h */
857 U32 FreeNVStore; /* 08h */
858 U16 VendorID; /* 0Ch */
859 U16 DeviceID; /* 0Eh */
860 U8 RevisionID; /* 10h */
861 U8 Reserved[3]; /* 11h */
862 U32 ClassCode; /* 14h */
863 U16 SubsystemVendorID; /* 18h */
864 U16 SubsystemID; /* 1Ah */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]865} CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]866 IOCPage0_t, MPI_POINTER pIOCPage0_t;
867
868#define MPI_IOCPAGE0_PAGEVERSION (0x01)
869
870
871typedef struct _CONFIG_PAGE_IOC_1
872{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]873 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]874 U32 Flags; /* 04h */
875 U32 CoalescingTimeout; /* 08h */
876 U8 CoalescingDepth; /* 0Ch */
877 U8 PCISlotNum; /* 0Dh */
878 U8 Reserved[2]; /* 0Eh */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]879} CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]880 IOCPage1_t, MPI_POINTER pIOCPage1_t;
881
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]882#define MPI_IOCPAGE1_PAGEVERSION (0x03)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]883
884/* defines for the Flags field */
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]885#define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000)
886#define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000)
887#define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000)
888#define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]889#define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]890#define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
891
892#define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
893
894
895typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
896{
897 U8 VolumeID; /* 00h */
898 U8 VolumeBus; /* 01h */
899 U8 VolumeIOC; /* 02h */
900 U8 VolumePageNumber; /* 03h */
901 U8 VolumeType; /* 04h */
902 U8 Flags; /* 05h */
903 U16 Reserved3; /* 06h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]904} CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]905 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
906
907/* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
908
909#define MPI_RAID_VOL_TYPE_IS (0x00)
910#define MPI_RAID_VOL_TYPE_IME (0x01)
911#define MPI_RAID_VOL_TYPE_IM (0x02)
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]912#define MPI_RAID_VOL_TYPE_RAID_5 (0x03)
913#define MPI_RAID_VOL_TYPE_RAID_6 (0x04)
914#define MPI_RAID_VOL_TYPE_RAID_10 (0x05)
915#define MPI_RAID_VOL_TYPE_RAID_50 (0x06)
916#define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]917
918/* IOC Page 2 Volume Flags values */
919
920#define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)
921
922/*
923 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
924 * one and check Header.PageLength at runtime.
925 */
926#ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
927#define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1)
928#endif
929
930typedef struct _CONFIG_PAGE_IOC_2
931{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]932 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]933 U32 CapabilitiesFlags; /* 04h */
934 U8 NumActiveVolumes; /* 08h */
935 U8 MaxVolumes; /* 09h */
936 U8 NumActivePhysDisks; /* 0Ah */
937 U8 MaxPhysDisks; /* 0Bh */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]938 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
939} CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]940 IOCPage2_t, MPI_POINTER pIOCPage2_t;
941
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]942#define MPI_IOCPAGE2_PAGEVERSION (0x04)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]943
944/* IOC Page 2 Capabilities flags */
945
946#define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)
947#define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)
948#define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]949#define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008)
950#define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010)
951#define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020)
952#define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040)
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]953#define MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING (0x10000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]954#define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)
955#define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)
956#define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)
957
958
959typedef struct _IOC_3_PHYS_DISK
960{
961 U8 PhysDiskID; /* 00h */
962 U8 PhysDiskBus; /* 01h */
963 U8 PhysDiskIOC; /* 02h */
964 U8 PhysDiskNum; /* 03h */
965} IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,
966 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;
967
968/*
969 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
970 * one and check Header.PageLength at runtime.
971 */
972#ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
973#define MPI_IOC_PAGE_3_PHYSDISK_MAX (1)
974#endif
975
976typedef struct _CONFIG_PAGE_IOC_3
977{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]978 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]979 U8 NumPhysDisks; /* 04h */
980 U8 Reserved1; /* 05h */
981 U16 Reserved2; /* 06h */
982 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]983} CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]984 IOCPage3_t, MPI_POINTER pIOCPage3_t;
985
986#define MPI_IOCPAGE3_PAGEVERSION (0x00)
987
988
989typedef struct _IOC_4_SEP
990{
991 U8 SEPTargetID; /* 00h */
992 U8 SEPBus; /* 01h */
993 U16 Reserved; /* 02h */
994} IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP,
995 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t;
996
997/*
998 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
999 * one and check Header.PageLength at runtime.
1000 */
1001#ifndef MPI_IOC_PAGE_4_SEP_MAX
1002#define MPI_IOC_PAGE_4_SEP_MAX (1)
1003#endif
1004
1005typedef struct _CONFIG_PAGE_IOC_4
1006{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1007 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1008 U8 ActiveSEP; /* 04h */
1009 U8 MaxSEP; /* 05h */
1010 U16 Reserved1; /* 06h */
1011 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1012} CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1013 IOCPage4_t, MPI_POINTER pIOCPage4_t;
1014
1015#define MPI_IOCPAGE4_PAGEVERSION (0x00)
1016
1017
1018typedef struct _IOC_5_HOT_SPARE
1019{
1020 U8 PhysDiskNum; /* 00h */
1021 U8 Reserved; /* 01h */
1022 U8 HotSparePool; /* 02h */
1023 U8 Flags; /* 03h */
1024} IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE,
1025 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t;
1026
1027/* IOC Page 5 HotSpare Flags */
1028#define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01)
1029
1030/*
1031 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1032 * one and check Header.PageLength at runtime.
1033 */
1034#ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX
1035#define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1)
1036#endif
1037
1038typedef struct _CONFIG_PAGE_IOC_5
1039{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1040 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1041 U32 Reserved1; /* 04h */
1042 U8 NumHotSpares; /* 08h */
1043 U8 Reserved2; /* 09h */
1044 U16 Reserved3; /* 0Ah */
1045 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1046} CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1047 IOCPage5_t, MPI_POINTER pIOCPage5_t;
1048
1049#define MPI_IOCPAGE5_PAGEVERSION (0x00)
1050
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]1051typedef struct _CONFIG_PAGE_IOC_6
1052{
1053 CONFIG_PAGE_HEADER Header; /* 00h */
1054 U32 CapabilitiesFlags; /* 04h */
1055 U8 MaxDrivesIS; /* 08h */
1056 U8 MaxDrivesIM; /* 09h */
1057 U8 MaxDrivesIME; /* 0Ah */
1058 U8 Reserved1; /* 0Bh */
1059 U8 MinDrivesIS; /* 0Ch */
1060 U8 MinDrivesIM; /* 0Dh */
1061 U8 MinDrivesIME; /* 0Eh */
1062 U8 Reserved2; /* 0Fh */
1063 U8 MaxGlobalHotSpares; /* 10h */
1064 U8 Reserved3; /* 11h */
1065 U16 Reserved4; /* 12h */
1066 U32 Reserved5; /* 14h */
1067 U32 SupportedStripeSizeMapIS; /* 18h */
1068 U32 SupportedStripeSizeMapIME; /* 1Ch */
1069 U32 Reserved6; /* 20h */
1070 U8 MetadataSize; /* 24h */
1071 U8 Reserved7; /* 25h */
1072 U16 Reserved8; /* 26h */
1073 U16 MaxBadBlockTableEntries; /* 28h */
1074 U16 Reserved9; /* 2Ah */
1075 U16 IRNvsramUsage; /* 2Ch */
1076 U16 Reserved10; /* 2Eh */
1077 U32 IRNvsramVersion; /* 30h */
1078 U32 Reserved11; /* 34h */
1079 U32 Reserved12; /* 38h */
1080} CONFIG_PAGE_IOC_6, MPI_POINTER PTR_CONFIG_PAGE_IOC_6,
1081 IOCPage6_t, MPI_POINTER pIOCPage6_t;
1082
1083#define MPI_IOCPAGE6_PAGEVERSION (0x00)
1084
1085/* IOC Page 6 Capabilities Flags */
1086
1087#define MPI_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1088
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1089
1090/****************************************************************************
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1091* BIOS Config Pages
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1092****************************************************************************/
1093
1094typedef struct _CONFIG_PAGE_BIOS_1
1095{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1096 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1097 U32 BiosOptions; /* 04h */
1098 U32 IOCSettings; /* 08h */
1099 U32 Reserved1; /* 0Ch */
1100 U32 DeviceSettings; /* 10h */
1101 U16 NumberOfDevices; /* 14h */
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]1102 U8 ExpanderSpinup; /* 16h */
1103 U8 Reserved2; /* 17h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1104 U16 IOTimeoutBlockDevicesNonRM; /* 18h */
1105 U16 IOTimeoutSequential; /* 1Ah */
1106 U16 IOTimeoutOther; /* 1Ch */
1107 U16 IOTimeoutBlockDevicesRM; /* 1Eh */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1108} CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1109 BIOSPage1_t, MPI_POINTER pBIOSPage1_t;
1110
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]1111#define MPI_BIOSPAGE1_PAGEVERSION (0x03)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1112
1113/* values for the BiosOptions field */
1114#define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400)
1115#define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200)
1116#define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100)
1117#define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1118
1119/* values for the IOCSettings field */
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]1120#define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY (0x0F000000)
1121#define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24)
1122
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]1123#define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000)
1124#define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20)
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]1125
1126#define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE (0x00080000)
1127#define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE (0x00040000)
1128
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1129#define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1130#define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1131#define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1132
1133#define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000)
1134#define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12)
1135
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1136#define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00)
1137#define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8)
1138
1139#define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1140#define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1141#define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1142#define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1143
1144#define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1145#define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1146#define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1147#define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1148#define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1149
1150#define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1151
1152/* values for the DeviceSettings field */
1153#define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1154#define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1155#define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1156#define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1157
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]1158/* defines for the ExpanderSpinup field */
1159#define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET (0xF0)
1160#define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET (4)
1161#define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY (0x0F)
1162
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1163typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER
1164{
1165 U32 Reserved1; /* 00h */
1166 U32 Reserved2; /* 04h */
1167 U32 Reserved3; /* 08h */
1168 U32 Reserved4; /* 0Ch */
1169 U32 Reserved5; /* 10h */
1170 U32 Reserved6; /* 14h */
1171 U32 Reserved7; /* 18h */
1172 U32 Reserved8; /* 1Ch */
1173 U32 Reserved9; /* 20h */
1174 U32 Reserved10; /* 24h */
1175 U32 Reserved11; /* 28h */
1176 U32 Reserved12; /* 2Ch */
1177 U32 Reserved13; /* 30h */
1178 U32 Reserved14; /* 34h */
1179 U32 Reserved15; /* 38h */
1180 U32 Reserved16; /* 3Ch */
1181 U32 Reserved17; /* 40h */
1182} MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER;
1183
1184typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER
1185{
1186 U8 TargetID; /* 00h */
1187 U8 Bus; /* 01h */
1188 U8 AdapterNumber; /* 02h */
1189 U8 Reserved1; /* 03h */
1190 U32 Reserved2; /* 04h */
1191 U32 Reserved3; /* 08h */
1192 U32 Reserved4; /* 0Ch */
1193 U8 LUN[8]; /* 10h */
1194 U32 Reserved5; /* 18h */
1195 U32 Reserved6; /* 1Ch */
1196 U32 Reserved7; /* 20h */
1197 U32 Reserved8; /* 24h */
1198 U32 Reserved9; /* 28h */
1199 U32 Reserved10; /* 2Ch */
1200 U32 Reserved11; /* 30h */
1201 U32 Reserved12; /* 34h */
1202 U32 Reserved13; /* 38h */
1203 U32 Reserved14; /* 3Ch */
1204 U32 Reserved15; /* 40h */
1205} MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER;
1206
1207typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS
1208{
1209 U8 TargetID; /* 00h */
1210 U8 Bus; /* 01h */
1211 U16 PCIAddress; /* 02h */
1212 U32 Reserved1; /* 04h */
1213 U32 Reserved2; /* 08h */
1214 U32 Reserved3; /* 0Ch */
1215 U8 LUN[8]; /* 10h */
1216 U32 Reserved4; /* 18h */
1217 U32 Reserved5; /* 1Ch */
1218 U32 Reserved6; /* 20h */
1219 U32 Reserved7; /* 24h */
1220 U32 Reserved8; /* 28h */
1221 U32 Reserved9; /* 2Ch */
1222 U32 Reserved10; /* 30h */
1223 U32 Reserved11; /* 34h */
1224 U32 Reserved12; /* 38h */
1225 U32 Reserved13; /* 3Ch */
1226 U32 Reserved14; /* 40h */
1227} MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS;
1228
1229typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER
1230{
1231 U8 TargetID; /* 00h */
1232 U8 Bus; /* 01h */
1233 U8 PCISlotNumber; /* 02h */
1234 U8 Reserved1; /* 03h */
1235 U32 Reserved2; /* 04h */
1236 U32 Reserved3; /* 08h */
1237 U32 Reserved4; /* 0Ch */
1238 U8 LUN[8]; /* 10h */
1239 U32 Reserved5; /* 18h */
1240 U32 Reserved6; /* 1Ch */
1241 U32 Reserved7; /* 20h */
1242 U32 Reserved8; /* 24h */
1243 U32 Reserved9; /* 28h */
1244 U32 Reserved10; /* 2Ch */
1245 U32 Reserved11; /* 30h */
1246 U32 Reserved12; /* 34h */
1247 U32 Reserved13; /* 38h */
1248 U32 Reserved14; /* 3Ch */
1249 U32 Reserved15; /* 40h */
1250} MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER;
1251
1252typedef struct _MPI_BOOT_DEVICE_FC_WWN
1253{
1254 U64 WWPN; /* 00h */
1255 U32 Reserved1; /* 08h */
1256 U32 Reserved2; /* 0Ch */
1257 U8 LUN[8]; /* 10h */
1258 U32 Reserved3; /* 18h */
1259 U32 Reserved4; /* 1Ch */
1260 U32 Reserved5; /* 20h */
1261 U32 Reserved6; /* 24h */
1262 U32 Reserved7; /* 28h */
1263 U32 Reserved8; /* 2Ch */
1264 U32 Reserved9; /* 30h */
1265 U32 Reserved10; /* 34h */
1266 U32 Reserved11; /* 38h */
1267 U32 Reserved12; /* 3Ch */
1268 U32 Reserved13; /* 40h */
1269} MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN;
1270
1271typedef struct _MPI_BOOT_DEVICE_SAS_WWN
1272{
1273 U64 SASAddress; /* 00h */
1274 U32 Reserved1; /* 08h */
1275 U32 Reserved2; /* 0Ch */
1276 U8 LUN[8]; /* 10h */
1277 U32 Reserved3; /* 18h */
1278 U32 Reserved4; /* 1Ch */
1279 U32 Reserved5; /* 20h */
1280 U32 Reserved6; /* 24h */
1281 U32 Reserved7; /* 28h */
1282 U32 Reserved8; /* 2Ch */
1283 U32 Reserved9; /* 30h */
1284 U32 Reserved10; /* 34h */
1285 U32 Reserved11; /* 38h */
1286 U32 Reserved12; /* 3Ch */
1287 U32 Reserved13; /* 40h */
1288} MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN;
1289
1290typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT
1291{
1292 U64 EnclosureLogicalID; /* 00h */
1293 U32 Reserved1; /* 08h */
1294 U32 Reserved2; /* 0Ch */
1295 U8 LUN[8]; /* 10h */
1296 U16 SlotNumber; /* 18h */
1297 U16 Reserved3; /* 1Ah */
1298 U32 Reserved4; /* 1Ch */
1299 U32 Reserved5; /* 20h */
1300 U32 Reserved6; /* 24h */
1301 U32 Reserved7; /* 28h */
1302 U32 Reserved8; /* 2Ch */
1303 U32 Reserved9; /* 30h */
1304 U32 Reserved10; /* 34h */
1305 U32 Reserved11; /* 38h */
1306 U32 Reserved12; /* 3Ch */
1307 U32 Reserved13; /* 40h */
1308} MPI_BOOT_DEVICE_ENCLOSURE_SLOT,
1309 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT;
1310
1311typedef union _MPI_BIOSPAGE2_BOOT_DEVICE
1312{
1313 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1314 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber;
1315 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress;
1316 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber;
1317 MPI_BOOT_DEVICE_FC_WWN FcWwn;
1318 MPI_BOOT_DEVICE_SAS_WWN SasWwn;
1319 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1320} MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE;
1321
1322typedef struct _CONFIG_PAGE_BIOS_2
1323{
1324 CONFIG_PAGE_HEADER Header; /* 00h */
1325 U32 Reserved1; /* 04h */
1326 U32 Reserved2; /* 08h */
1327 U32 Reserved3; /* 0Ch */
1328 U32 Reserved4; /* 10h */
1329 U32 Reserved5; /* 14h */
1330 U32 Reserved6; /* 18h */
1331 U8 BootDeviceForm; /* 1Ch */
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]1332 U8 PrevBootDeviceForm; /* 1Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1333 U16 Reserved8; /* 1Eh */
1334 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */
1335} CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2,
1336 BIOSPage2_t, MPI_POINTER pBIOSPage2_t;
1337
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]1338#define MPI_BIOSPAGE2_PAGEVERSION (0x02)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1339
1340#define MPI_BIOSPAGE2_FORM_MASK (0x0F)
1341#define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00)
1342#define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01)
1343#define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02)
1344#define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03)
1345#define MPI_BIOSPAGE2_FORM_FC_WWN (0x04)
1346#define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05)
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]1347#define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1348
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1349
1350/****************************************************************************
1351* SCSI Port Config Pages
1352****************************************************************************/
1353
1354typedef struct _CONFIG_PAGE_SCSI_PORT_0
1355{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1356 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1357 U32 Capabilities; /* 04h */
1358 U32 PhysicalInterface; /* 08h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1359} CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1360 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
1361
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1362#define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1363
1364#define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)
1365#define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
1366#define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
1367#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1368#define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00)
1369#define MPI_SCSIPORTPAGE0_SYNC_5 (0x32)
1370#define MPI_SCSIPORTPAGE0_SYNC_10 (0x19)
1371#define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C)
1372#define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B)
1373#define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A)
1374#define MPI_SCSIPORTPAGE0_SYNC_80 (0x09)
1375#define MPI_SCSIPORTPAGE0_SYNC_160 (0x08)
1376#define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF)
1377
1378#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8)
1379#define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]1380 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1381 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \
1382 )
1383#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1384#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16)
1385#define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]1386 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1387 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \
1388 )
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1389#define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1390#define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
1391#define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
1392
1393#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)
1394#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)
1395#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)
1396#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)
1397#define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)
1398#define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24)
1399#define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE)
1400#define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF)
1401
1402
1403typedef struct _CONFIG_PAGE_SCSI_PORT_1
1404{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1405 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1406 U32 Configuration; /* 04h */
1407 U32 OnBusTimerValue; /* 08h */
1408 U8 TargetConfig; /* 0Ch */
1409 U8 Reserved1; /* 0Dh */
1410 U16 IDConfig; /* 0Eh */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1411} CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1412 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
1413
1414#define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)
1415
1416/* Configuration values */
1417#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
1418#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
1419#define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16)
1420
1421/* TargetConfig values */
1422#define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01)
1423#define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02)
1424
1425
1426typedef struct _MPI_DEVICE_INFO
1427{
1428 U8 Timeout; /* 00h */
1429 U8 SyncFactor; /* 01h */
1430 U16 DeviceFlags; /* 02h */
1431} MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,
1432 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;
1433
1434typedef struct _CONFIG_PAGE_SCSI_PORT_2
1435{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1436 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1437 U32 PortFlags; /* 04h */
1438 U32 PortSettings; /* 08h */
1439 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1440} CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1441 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;
1442
1443#define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02)
1444
1445/* PortFlags values */
1446#define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001)
1447#define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004)
1448#define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1449#define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)
1450
1451#define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060)
1452#define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000)
1453#define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020)
1454#define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060)
1455
1456
1457/* PortSettings values */
1458#define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)
1459#define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)
1460#define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000)
1461#define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010)
1462#define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)
1463#define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)
1464#define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)
1465#define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000)
1466#define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040)
1467#define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080)
1468#define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)
1469#define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8)
1470#define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)
1471#define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)
1472#define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)
1473#define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000)
1474
1475#define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001)
1476#define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002)
1477#define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004)
1478#define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008)
1479#define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010)
1480#define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020)
1481
1482
1483/****************************************************************************
1484* SCSI Target Device Config Pages
1485****************************************************************************/
1486
1487typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
1488{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1489 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1490 U32 NegotiatedParameters; /* 04h */
1491 U32 Information; /* 08h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1492} CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1493 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
1494
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1495#define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1496
1497#define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)
1498#define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)
1499#define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)
1500#define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)
1501#define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)
1502#define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)
1503#define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)
1504#define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)
1505#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
1506#define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8)
1507#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
1508#define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1509#define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1510#define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
1511#define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
1512
1513#define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)
1514#define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)
1515#define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)
1516#define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)
1517
1518
1519typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
1520{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1521 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1522 U32 RequestedParameters; /* 04h */
1523 U32 Reserved; /* 08h */
1524 U32 Configuration; /* 0Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1525} CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1526 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
1527
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1528#define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1529
1530#define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)
1531#define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)
1532#define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)
1533#define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)
1534#define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)
1535#define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)
1536#define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)
1537#define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)
1538#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1539#define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8)
1540#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1541#define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1542#define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1543#define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
1544#define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
1545
1546#define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)
1547#define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)
1548#define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)
1549#define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)
1550
1551
1552typedef struct _CONFIG_PAGE_SCSI_DEVICE_2
1553{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1554 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1555 U32 DomainValidation; /* 04h */
1556 U32 ParityPipeSelect; /* 08h */
1557 U32 DataPipeSelect; /* 0Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1558} CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1559 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;
1560
1561#define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01)
1562
1563#define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010)
1564#define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020)
1565#define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380)
1566#define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00)
1567#define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000)
1568#define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000)
1569#define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000)
1570#define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000)
1571#define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000)
1572
1573#define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003)
1574
1575#define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003)
1576#define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C)
1577#define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030)
1578#define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0)
1579#define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300)
1580#define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00)
1581#define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000)
1582#define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000)
1583#define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000)
1584#define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000)
1585#define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000)
1586#define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000)
1587#define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000)
1588#define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000)
1589#define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000)
1590#define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000)
1591
1592
1593typedef struct _CONFIG_PAGE_SCSI_DEVICE_3
1594{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1595 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1596 U16 MsgRejectCount; /* 04h */
1597 U16 PhaseErrorCount; /* 06h */
1598 U16 ParityErrorCount; /* 08h */
1599 U16 Reserved; /* 0Ah */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1600} CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1601 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t;
1602
1603#define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00)
1604
1605#define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE)
1606#define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF)
1607
1608
1609/****************************************************************************
1610* FC Port Config Pages
1611****************************************************************************/
1612
1613typedef struct _CONFIG_PAGE_FC_PORT_0
1614{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1615 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1616 U32 Flags; /* 04h */
1617 U8 MPIPortNumber; /* 08h */
1618 U8 LinkType; /* 09h */
1619 U8 PortState; /* 0Ah */
1620 U8 Reserved; /* 0Bh */
1621 U32 PortIdentifier; /* 0Ch */
1622 U64 WWNN; /* 10h */
1623 U64 WWPN; /* 18h */
1624 U32 SupportedServiceClass; /* 20h */
1625 U32 SupportedSpeeds; /* 24h */
1626 U32 CurrentSpeed; /* 28h */
1627 U32 MaxFrameSize; /* 2Ch */
1628 U64 FabricWWNN; /* 30h */
1629 U64 FabricWWPN; /* 38h */
1630 U32 DiscoveredPortsCount; /* 40h */
1631 U32 MaxInitiators; /* 44h */
1632 U8 MaxAliasesSupported; /* 48h */
1633 U8 MaxHardAliasesSupported; /* 49h */
1634 U8 NumCurrentAliases; /* 4Ah */
1635 U8 Reserved1; /* 4Bh */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1636} CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1637 FCPortPage0_t, MPI_POINTER pFCPortPage0_t;
1638
1639#define MPI_FCPORTPAGE0_PAGEVERSION (0x02)
1640
1641#define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F)
1642#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR)
1643#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET)
1644#define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN)
1645#define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)
1646
1647#define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010)
1648#define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020)
1649#define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040)
1650
1651#define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00)
1652#define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000)
1653#define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100)
1654#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200)
1655#define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400)
1656#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800)
1657
1658#define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00)
1659#define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01)
1660#define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02)
1661#define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03)
1662#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04)
1663#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05)
1664#define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06)
1665#define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07)
1666#define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08)
1667#define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09)
1668#define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A)
1669#define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B)
1670#define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C)
1671#define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D)
1672#define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E)
1673#define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F)
1674
1675#define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */
1676#define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */
1677#define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */
1678#define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */
1679#define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */
1680#define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */
1681#define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */
1682#define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */
1683
1684#define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001)
1685#define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002)
1686#define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004)
1687
1688#define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */
1689#define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */
1690#define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */
1691#define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */
1692#define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */
1693
1694#define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN
1695#define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
1696#define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
1697#define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
1698#define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED
1699#define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */
1700
1701
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1702typedef struct _CONFIG_PAGE_FC_PORT_1
1703{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1704 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1705 U32 Flags; /* 04h */
1706 U64 NoSEEPROMWWNN; /* 08h */
1707 U64 NoSEEPROMWWPN; /* 10h */
1708 U8 HardALPA; /* 18h */
1709 U8 LinkConfig; /* 19h */
1710 U8 TopologyConfig; /* 1Ah */
1711 U8 AltConnector; /* 1Bh */
1712 U8 NumRequestedAliases; /* 1Ch */
1713 U8 RR_TOV; /* 1Dh */
1714 U8 InitiatorDeviceTimeout; /* 1Eh */
1715 U8 InitiatorIoPendTimeout; /* 1Fh */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1716} CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1717 FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
1718
1719#define MPI_FCPORTPAGE1_PAGEVERSION (0x06)
1720
1721#define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
1722#define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
1723#define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000)
1724#define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)
1725#define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)
1726#define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000)
1727#define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1728#define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1729#define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)
1730#define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008)
1731#define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004)
1732#define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002)
1733#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)
1734#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)
1735
1736#define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)
1737#define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28)
1738#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1739#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1740#define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1741#define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1742
1743#define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000)
1744#define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010)
1745#define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030)
1746#define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050)
1747
1748#define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF)
1749
1750#define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F)
1751#define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00)
1752#define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01)
1753#define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02)
1754#define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03)
1755#define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F)
1756
1757#define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F)
1758#define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01)
1759#define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02)
1760#define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F)
1761
1762#define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00)
1763
1764#define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1765#define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1766
1767
1768typedef struct _CONFIG_PAGE_FC_PORT_2
1769{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1770 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1771 U8 NumberActive; /* 04h */
1772 U8 ALPA[127]; /* 05h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1773} CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1774 FCPortPage2_t, MPI_POINTER pFCPortPage2_t;
1775
1776#define MPI_FCPORTPAGE2_PAGEVERSION (0x01)
1777
1778
1779typedef struct _WWN_FORMAT
1780{
1781 U64 WWNN; /* 00h */
1782 U64 WWPN; /* 08h */
1783} WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT,
1784 WWNFormat, MPI_POINTER pWWNFormat;
1785
1786typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID
1787{
1788 WWN_FORMAT WWN;
1789 U32 Did;
1790} FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID,
1791 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t;
1792
1793typedef struct _FC_PORT_PERSISTENT
1794{
1795 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */
1796 U8 TargetID; /* 10h */
1797 U8 Bus; /* 11h */
1798 U16 Flags; /* 12h */
1799} FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT,
1800 PersistentData_t, MPI_POINTER pPersistentData_t;
1801
1802#define MPI_PERSISTENT_FLAGS_SHIFT (16)
1803#define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001)
1804#define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002)
1805#define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004)
1806#define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008)
1807#define MPI_PERSISTENT_FLAGS_BY_DID (0x0080)
1808
1809/*
1810 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1811 * one and check Header.PageLength at runtime.
1812 */
1813#ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
1814#define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1)
1815#endif
1816
1817typedef struct _CONFIG_PAGE_FC_PORT_3
1818{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1819 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1820 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1821} CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1822 FCPortPage3_t, MPI_POINTER pFCPortPage3_t;
1823
1824#define MPI_FCPORTPAGE3_PAGEVERSION (0x01)
1825
1826
1827typedef struct _CONFIG_PAGE_FC_PORT_4
1828{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1829 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1830 U32 PortFlags; /* 04h */
1831 U32 PortSettings; /* 08h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1832} CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1833 FCPortPage4_t, MPI_POINTER pFCPortPage4_t;
1834
1835#define MPI_FCPORTPAGE4_PAGEVERSION (0x00)
1836
1837#define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1838
1839#define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030)
1840#define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000)
1841#define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010)
1842#define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020)
1843#define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030)
1844#define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0)
1845#define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00)
1846
1847
1848typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
1849{
1850 U8 Flags; /* 00h */
1851 U8 AliasAlpa; /* 01h */
1852 U16 Reserved; /* 02h */
1853 U64 AliasWWNN; /* 04h */
1854 U64 AliasWWPN; /* 0Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1855} CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1856 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1857 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;
1858
1859typedef struct _CONFIG_PAGE_FC_PORT_5
1860{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1861 CONFIG_PAGE_HEADER Header; /* 00h */
1862 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */
1863} CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1864 FCPortPage5_t, MPI_POINTER pFCPortPage5_t;
1865
1866#define MPI_FCPORTPAGE5_PAGEVERSION (0x02)
1867
1868#define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01)
1869#define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02)
1870#define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04)
1871#define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08)
1872#define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10)
1873
1874typedef struct _CONFIG_PAGE_FC_PORT_6
1875{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1876 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1877 U32 Reserved; /* 04h */
1878 U64 TimeSinceReset; /* 08h */
1879 U64 TxFrames; /* 10h */
1880 U64 RxFrames; /* 18h */
1881 U64 TxWords; /* 20h */
1882 U64 RxWords; /* 28h */
1883 U64 LipCount; /* 30h */
1884 U64 NosCount; /* 38h */
1885 U64 ErrorFrames; /* 40h */
1886 U64 DumpedFrames; /* 48h */
1887 U64 LinkFailureCount; /* 50h */
1888 U64 LossOfSyncCount; /* 58h */
1889 U64 LossOfSignalCount; /* 60h */
1890 U64 PrimativeSeqErrCount; /* 68h */
1891 U64 InvalidTxWordCount; /* 70h */
1892 U64 InvalidCrcCount; /* 78h */
1893 U64 FcpInitiatorIoCount; /* 80h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1894} CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1895 FCPortPage6_t, MPI_POINTER pFCPortPage6_t;
1896
1897#define MPI_FCPORTPAGE6_PAGEVERSION (0x00)
1898
1899
1900typedef struct _CONFIG_PAGE_FC_PORT_7
1901{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1902 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1903 U32 Reserved; /* 04h */
1904 U8 PortSymbolicName[256]; /* 08h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1905} CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1906 FCPortPage7_t, MPI_POINTER pFCPortPage7_t;
1907
1908#define MPI_FCPORTPAGE7_PAGEVERSION (0x00)
1909
1910
1911typedef struct _CONFIG_PAGE_FC_PORT_8
1912{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1913 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1914 U32 BitVector[8]; /* 04h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1915} CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1916 FCPortPage8_t, MPI_POINTER pFCPortPage8_t;
1917
1918#define MPI_FCPORTPAGE8_PAGEVERSION (0x00)
1919
1920
1921typedef struct _CONFIG_PAGE_FC_PORT_9
1922{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1923 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1924 U32 Reserved; /* 04h */
1925 U64 GlobalWWPN; /* 08h */
1926 U64 GlobalWWNN; /* 10h */
1927 U32 UnitType; /* 18h */
1928 U32 PhysicalPortNumber; /* 1Ch */
1929 U32 NumAttachedNodes; /* 20h */
1930 U16 IPVersion; /* 24h */
1931 U16 UDPPortNumber; /* 26h */
1932 U8 IPAddress[16]; /* 28h */
1933 U16 Reserved1; /* 38h */
1934 U16 TopologyDiscoveryFlags; /* 3Ah */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1935} CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1936 FCPortPage9_t, MPI_POINTER pFCPortPage9_t;
1937
1938#define MPI_FCPORTPAGE9_PAGEVERSION (0x00)
1939
1940
1941typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA
1942{
1943 U8 Id; /* 10h */
1944 U8 ExtId; /* 11h */
1945 U8 Connector; /* 12h */
1946 U8 Transceiver[8]; /* 13h */
1947 U8 Encoding; /* 1Bh */
1948 U8 BitRate_100mbs; /* 1Ch */
1949 U8 Reserved1; /* 1Dh */
1950 U8 Length9u_km; /* 1Eh */
1951 U8 Length9u_100m; /* 1Fh */
1952 U8 Length50u_10m; /* 20h */
1953 U8 Length62p5u_10m; /* 21h */
1954 U8 LengthCopper_m; /* 22h */
1955 U8 Reseverved2; /* 22h */
1956 U8 VendorName[16]; /* 24h */
1957 U8 Reserved3; /* 34h */
1958 U8 VendorOUI[3]; /* 35h */
1959 U8 VendorPN[16]; /* 38h */
1960 U8 VendorRev[4]; /* 48h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1961 U16 Wavelength; /* 4Ch */
1962 U8 Reserved4; /* 4Eh */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1963 U8 CC_BASE; /* 4Fh */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]1964} CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1965 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
1966 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t;
1967
1968#define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00)
1969#define MPI_FCPORT10_BASE_ID_GBIC (0x01)
1970#define MPI_FCPORT10_BASE_ID_FIXED (0x02)
1971#define MPI_FCPORT10_BASE_ID_SFP (0x03)
1972#define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04)
1973#define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F)
1974#define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80)
1975
1976#define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00)
1977#define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01)
1978#define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02)
1979#define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03)
1980#define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04)
1981#define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05)
1982#define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06)
1983#define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07)
1984#define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80)
1985
1986#define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00)
1987#define MPI_FCPORT10_BASE_CONN_SC (0x01)
1988#define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02)
1989#define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03)
1990#define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04)
1991#define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05)
1992#define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06)
1993#define MPI_FCPORT10_BASE_CONN_LC (0x07)
1994#define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08)
1995#define MPI_FCPORT10_BASE_CONN_MU (0x09)
1996#define MPI_FCPORT10_BASE_CONN_SG (0x0A)
1997#define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B)
1998#define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C)
1999#define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F)
2000#define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20)
2001#define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21)
2002#define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22)
2003#define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F)
2004#define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80)
2005
2006#define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00)
2007#define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01)
2008#define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02)
2009#define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03)
2010#define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04)
2011
2012
2013typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA
2014{
2015 U8 Options[2]; /* 50h */
2016 U8 BitRateMax; /* 52h */
2017 U8 BitRateMin; /* 53h */
2018 U8 VendorSN[16]; /* 54h */
2019 U8 DateCode[8]; /* 64h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2020 U8 DiagMonitoringType; /* 6Ch */
2021 U8 EnhancedOptions; /* 6Dh */
2022 U8 SFF8472Compliance; /* 6Eh */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2023 U8 CC_EXT; /* 6Fh */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2024} CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2025 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
2026 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t;
2027
2028#define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20)
2029#define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10)
2030#define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08)
2031#define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04)
2032#define MPI_FCPORT10_EXT_OPTION1_LOS (0x02)
2033
2034
2035typedef struct _CONFIG_PAGE_FC_PORT_10
2036{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2037 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2038 U8 Flags; /* 04h */
2039 U8 Reserved1; /* 05h */
2040 U16 Reserved2; /* 06h */
2041 U32 HwConfig1; /* 08h */
2042 U32 HwConfig2; /* 0Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2043 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */
2044 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2045 U8 VendorSpecific[32]; /* 70h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2046} CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2047 FCPortPage10_t, MPI_POINTER pFCPortPage10_t;
2048
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2049#define MPI_FCPORTPAGE10_PAGEVERSION (0x01)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2050
2051/* standard MODDEF pin definitions (from GBIC spec.) */
2052#define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007)
2053#define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001)
2054#define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002)
2055#define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004)
2056#define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007)
2057#define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006)
2058#define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005)
2059#define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004)
2060#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003)
2061#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002)
2062#define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001)
2063#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000)
2064
2065#define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010)
2066#define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020)
2067
2068
2069/****************************************************************************
2070* FC Device Config Pages
2071****************************************************************************/
2072
2073typedef struct _CONFIG_PAGE_FC_DEVICE_0
2074{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2075 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2076 U64 WWNN; /* 04h */
2077 U64 WWPN; /* 0Ch */
2078 U32 PortIdentifier; /* 14h */
2079 U8 Protocol; /* 18h */
2080 U8 Flags; /* 19h */
2081 U16 BBCredit; /* 1Ah */
2082 U16 MaxRxFrameSize; /* 1Ch */
2083 U8 ADISCHardALPA; /* 1Eh */
2084 U8 PortNumber; /* 1Fh */
2085 U8 FcPhLowestVersion; /* 20h */
2086 U8 FcPhHighestVersion; /* 21h */
2087 U8 CurrentTargetID; /* 22h */
2088 U8 CurrentBus; /* 23h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2089} CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2090 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;
2091
2092#define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03)
2093
2094#define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01)
2095#define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02)
2096#define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04)
2097
2098#define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01)
2099#define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02)
2100#define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04)
2101#define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08)
2102
2103#define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK)
2104#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK)
2105#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
2106#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)
2107#define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK)
2108#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)
2109#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)
2110#define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK)
2111
2112#define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF)
2113
2114/****************************************************************************
2115* RAID Volume Config Pages
2116****************************************************************************/
2117
2118typedef struct _RAID_VOL0_PHYS_DISK
2119{
2120 U16 Reserved; /* 00h */
2121 U8 PhysDiskMap; /* 02h */
2122 U8 PhysDiskNum; /* 03h */
2123} RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK,
2124 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t;
2125
2126#define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
2127#define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
2128
2129typedef struct _RAID_VOL0_STATUS
2130{
2131 U8 Flags; /* 00h */
2132 U8 State; /* 01h */
2133 U16 Reserved; /* 02h */
2134} RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
2135 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
2136
2137/* RAID Volume Page 0 VolumeStatus defines */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2138#define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)
2139#define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)
2140#define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)
2141#define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08)
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]2142#define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2143
2144#define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)
2145#define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)
2146#define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2147#define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2148
2149typedef struct _RAID_VOL0_SETTINGS
2150{
2151 U16 Settings; /* 00h */
2152 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2153 U8 Reserved; /* 02h */
2154} RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,
2155 RaidVol0Settings, MPI_POINTER pRaidVol0Settings;
2156
2157/* RAID Volume Page 0 VolumeSettings defines */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2158#define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001)
2159#define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002)
2160#define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004)
2161#define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2162#define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2163#define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010)
2164#define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000)
2165
2166/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
2167#define MPI_RAID_HOT_SPARE_POOL_0 (0x01)
2168#define MPI_RAID_HOT_SPARE_POOL_1 (0x02)
2169#define MPI_RAID_HOT_SPARE_POOL_2 (0x04)
2170#define MPI_RAID_HOT_SPARE_POOL_3 (0x08)
2171#define MPI_RAID_HOT_SPARE_POOL_4 (0x10)
2172#define MPI_RAID_HOT_SPARE_POOL_5 (0x20)
2173#define MPI_RAID_HOT_SPARE_POOL_6 (0x40)
2174#define MPI_RAID_HOT_SPARE_POOL_7 (0x80)
2175
2176/*
2177 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2178 * one and check Header.PageLength at runtime.
2179 */
2180#ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
2181#define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
2182#endif
2183
2184typedef struct _CONFIG_PAGE_RAID_VOL_0
2185{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2186 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2187 U8 VolumeID; /* 04h */
2188 U8 VolumeBus; /* 05h */
2189 U8 VolumeIOC; /* 06h */
2190 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */
2191 RAID_VOL0_STATUS VolumeStatus; /* 08h */
2192 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */
2193 U32 MaxLBA; /* 10h */
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]2194 U32 MaxLBAHigh; /* 14h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2195 U32 StripeSize; /* 18h */
2196 U32 Reserved2; /* 1Ch */
2197 U32 Reserved3; /* 20h */
2198 U8 NumPhysDisks; /* 24h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2199 U8 DataScrubRate; /* 25h */
2200 U8 ResyncRate; /* 26h */
2201 U8 InactiveStatus; /* 27h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2202 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2203} CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2204 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
2205
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]2206#define MPI_RAIDVOLPAGE0_PAGEVERSION (0x06)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2207
2208/* values for RAID Volume Page 0 InactiveStatus field */
2209#define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
2210#define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
2211#define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
2212#define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
2213#define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
2214#define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
2215#define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
2216
2217
2218typedef struct _CONFIG_PAGE_RAID_VOL_1
2219{
2220 CONFIG_PAGE_HEADER Header; /* 00h */
2221 U8 VolumeID; /* 01h */
2222 U8 VolumeBus; /* 02h */
2223 U8 VolumeIOC; /* 03h */
2224 U8 Reserved0; /* 04h */
2225 U8 GUID[24]; /* 05h */
2226 U8 Name[32]; /* 20h */
2227 U64 WWID; /* 40h */
2228 U32 Reserved1; /* 48h */
2229 U32 Reserved2; /* 4Ch */
2230} CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1,
2231 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t;
2232
2233#define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2234
2235
2236/****************************************************************************
2237* RAID Physical Disk Config Pages
2238****************************************************************************/
2239
2240typedef struct _RAID_PHYS_DISK0_ERROR_DATA
2241{
2242 U8 ErrorCdbByte; /* 00h */
2243 U8 ErrorSenseKey; /* 01h */
2244 U16 Reserved; /* 02h */
2245 U16 ErrorCount; /* 04h */
2246 U8 ErrorASC; /* 06h */
2247 U8 ErrorASCQ; /* 07h */
2248 U16 SmartCount; /* 08h */
2249 U8 SmartASC; /* 0Ah */
2250 U8 SmartASCQ; /* 0Bh */
2251} RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA,
2252 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t;
2253
2254typedef struct _RAID_PHYS_DISK_INQUIRY_DATA
2255{
2256 U8 VendorID[8]; /* 00h */
2257 U8 ProductID[16]; /* 08h */
2258 U8 ProductRevLevel[4]; /* 18h */
2259 U8 Info[32]; /* 1Ch */
2260} RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA,
2261 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData;
2262
2263typedef struct _RAID_PHYS_DISK0_SETTINGS
2264{
2265 U8 SepID; /* 00h */
2266 U8 SepBus; /* 01h */
2267 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2268 U8 PhysDiskSettings; /* 03h */
2269} RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS,
2270 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t;
2271
2272typedef struct _RAID_PHYS_DISK0_STATUS
2273{
2274 U8 Flags; /* 00h */
2275 U8 State; /* 01h */
2276 U16 Reserved; /* 02h */
2277} RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,
2278 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;
2279
2280/* RAID Volume 2 IM Physical Disk DiskStatus flags */
2281
2282#define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01)
2283#define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2284#define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04)
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]2285#define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00)
2286#define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2287
2288#define MPI_PHYSDISK0_STATUS_ONLINE (0x00)
2289#define MPI_PHYSDISK0_STATUS_MISSING (0x01)
2290#define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02)
2291#define MPI_PHYSDISK0_STATUS_FAILED (0x03)
2292#define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)
2293#define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)
2294#define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)
2295#define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)
2296
2297typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
2298{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2299 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2300 U8 PhysDiskID; /* 04h */
2301 U8 PhysDiskBus; /* 05h */
2302 U8 PhysDiskIOC; /* 06h */
2303 U8 PhysDiskNum; /* 07h */
2304 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */
2305 U32 Reserved1; /* 0Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2306 U8 ExtDiskIdentifier[8]; /* 10h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2307 U8 DiskIdentifier[16]; /* 18h */
2308 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */
2309 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */
2310 U32 MaxLBA; /* 68h */
2311 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2312} CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2313 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
2314
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]2315#define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2316
2317
2318typedef struct _RAID_PHYS_DISK1_PATH
2319{
2320 U8 PhysDiskID; /* 00h */
2321 U8 PhysDiskBus; /* 01h */
2322 U16 Reserved1; /* 02h */
2323 U64 WWID; /* 04h */
2324 U64 OwnerWWID; /* 0Ch */
2325 U8 OwnerIdentifier; /* 14h */
2326 U8 Reserved2; /* 15h */
2327 U16 Flags; /* 16h */
2328} RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH,
2329 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t;
2330
2331/* RAID Physical Disk Page 1 Flags field defines */
2332#define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
2333#define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
2334
2335typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1
2336{
2337 CONFIG_PAGE_HEADER Header; /* 00h */
2338 U8 NumPhysDiskPaths; /* 04h */
2339 U8 PhysDiskNum; /* 05h */
2340 U16 Reserved2; /* 06h */
2341 U32 Reserved1; /* 08h */
2342 RAID_PHYS_DISK1_PATH Path[1]; /* 0Ch */
2343} CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1,
2344 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t;
2345
2346#define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2347
2348
2349/****************************************************************************
2350* LAN Config Pages
2351****************************************************************************/
2352
2353typedef struct _CONFIG_PAGE_LAN_0
2354{
2355 ConfigPageHeader_t Header; /* 00h */
2356 U16 TxRxModes; /* 04h */
2357 U16 Reserved; /* 06h */
2358 U32 PacketPrePad; /* 08h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2359} CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2360 LANPage0_t, MPI_POINTER pLANPage0_t;
2361
2362#define MPI_LAN_PAGE0_PAGEVERSION (0x01)
2363
2364#define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000)
2365#define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001)
2366#define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001)
2367
2368typedef struct _CONFIG_PAGE_LAN_1
2369{
2370 ConfigPageHeader_t Header; /* 00h */
2371 U16 Reserved; /* 04h */
2372 U8 CurrentDeviceState; /* 06h */
2373 U8 Reserved1; /* 07h */
2374 U32 MinPacketSize; /* 08h */
2375 U32 MaxPacketSize; /* 0Ch */
2376 U32 HardwareAddressLow; /* 10h */
2377 U32 HardwareAddressHigh; /* 14h */
2378 U32 MaxWireSpeedLow; /* 18h */
2379 U32 MaxWireSpeedHigh; /* 1Ch */
2380 U32 BucketsRemaining; /* 20h */
2381 U32 MaxReplySize; /* 24h */
2382 U32 NegWireSpeedLow; /* 28h */
2383 U32 NegWireSpeedHigh; /* 2Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2384} CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2385 LANPage1_t, MPI_POINTER pLANPage1_t;
2386
2387#define MPI_LAN_PAGE1_PAGEVERSION (0x03)
2388
2389#define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
2390#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
2391
2392
2393/****************************************************************************
2394* Inband Config Pages
2395****************************************************************************/
2396
2397typedef struct _CONFIG_PAGE_INBAND_0
2398{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2399 CONFIG_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2400 MPI_VERSION_FORMAT InbandVersion; /* 04h */
2401 U16 MaximumBuffers; /* 08h */
2402 U16 Reserved1; /* 0Ah */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2403} CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2404 InbandPage0_t, MPI_POINTER pInbandPage0_t;
2405
2406#define MPI_INBAND_PAGEVERSION (0x00)
2407
2408
2409
2410/****************************************************************************
2411* SAS IO Unit Config Pages
2412****************************************************************************/
2413
2414typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA
2415{
2416 U8 Port; /* 00h */
2417 U8 PortFlags; /* 01h */
2418 U8 PhyFlags; /* 02h */
2419 U8 NegotiatedLinkRate; /* 03h */
2420 U32 ControllerPhyDeviceInfo;/* 04h */
2421 U16 AttachedDeviceHandle; /* 08h */
2422 U16 ControllerDevHandle; /* 0Ah */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2423 U32 DiscoveryStatus; /* 0Ch */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2424} MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA,
2425 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData;
2426
2427/*
2428 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2429 * one and check Header.PageLength at runtime.
2430 */
2431#ifndef MPI_SAS_IOUNIT0_PHY_MAX
2432#define MPI_SAS_IOUNIT0_PHY_MAX (1)
2433#endif
2434
2435typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0
2436{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2437 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]2438 U16 NvdataVersionDefault; /* 08h */
2439 U16 NvdataVersionPersistent; /* 0Ah */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2440 U8 NumPhys; /* 0Ch */
2441 U8 Reserved2; /* 0Dh */
2442 U16 Reserved3; /* 0Eh */
2443 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2444} CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2445 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t;
2446
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]2447#define MPI_SASIOUNITPAGE0_PAGEVERSION (0x04)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2448
2449/* values for SAS IO Unit Page 0 PortFlags */
2450#define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08)
2451#define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2452#define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2453#define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2454
2455/* values for SAS IO Unit Page 0 PhyFlags */
2456#define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04)
2457#define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02)
2458#define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01)
2459
2460/* values for SAS IO Unit Page 0 NegotiatedLinkRate */
2461#define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00)
2462#define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01)
2463#define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02)
2464#define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03)
2465#define MPI_SAS_IOUNIT0_RATE_1_5 (0x08)
2466#define MPI_SAS_IOUNIT0_RATE_3_0 (0x09)
2467
2468/* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2469
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2470/* values for SAS IO Unit Page 0 DiscoveryStatus */
2471#define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001)
2472#define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2473#define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2474#define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008)
2475#define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2476#define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2477#define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2478#define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2479#define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2480#define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2481#define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400)
2482#define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]2483#define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2484
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2485
2486typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA
2487{
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]2488 U8 Port; /* 00h */
2489 U8 PortFlags; /* 01h */
2490 U8 PhyFlags; /* 02h */
2491 U8 MaxMinLinkRate; /* 03h */
2492 U32 ControllerPhyDeviceInfo; /* 04h */
2493 U16 MaxTargetPortConnectTime; /* 08h */
2494 U16 Reserved1; /* 0Ah */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2495} MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA,
2496 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData;
2497
2498/*
2499 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2500 * one and check Header.PageLength at runtime.
2501 */
2502#ifndef MPI_SAS_IOUNIT1_PHY_MAX
2503#define MPI_SAS_IOUNIT1_PHY_MAX (1)
2504#endif
2505
2506typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1
2507{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2508 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2509 U16 ControlFlags; /* 08h */
2510 U16 MaxNumSATATargets; /* 0Ah */
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]2511 U16 AdditionalControlFlags; /* 0Ch */
2512 U16 Reserved1; /* 0Eh */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2513 U8 NumPhys; /* 10h */
2514 U8 SATAMaxQDepth; /* 11h */
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]2515 U8 ReportDeviceMissingDelay; /* 12h */
2516 U8 IODeviceMissingDelay; /* 13h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2517 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */
2518} CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2519 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t;
2520
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]2521#define MPI_SASIOUNITPAGE1_PAGEVERSION (0x06)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2522
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2523/* values for SAS IO Unit Page 1 ControlFlags */
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2524#define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2525#define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2526#define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2527#define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2528#define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2529
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2530#define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2531#define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2532#define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00)
2533#define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01)
2534#define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2535
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2536#define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT (0x0100)
2537#define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2538#define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2539#define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2540#define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2541#define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008)
2542#define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2543#define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2544#define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2545
Eric Moore2076eb62006-06-27 14:39:06 -0600[diff] [blame^]2546/* values for SAS IO Unit Page 1 AdditionalControlFlags */
2547#define MPI_SAS_IOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2548
2549/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2550#define MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2551#define MPI_SAS_IOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2552
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2553/* values for SAS IO Unit Page 1 PortFlags */
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2554#define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2555#define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2556#define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2557
2558/* values for SAS IO Unit Page 0 PhyFlags */
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2559#define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04)
2560#define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02)
2561#define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2562
2563/* values for SAS IO Unit Page 0 MaxMinLinkRate */
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2564#define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0)
2565#define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80)
2566#define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90)
2567#define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F)
2568#define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08)
2569#define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2570
2571/* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2572
2573
2574typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2
2575{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2576 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2577 U8 NumDevsPerEnclosure; /* 08h */
2578 U8 Reserved1; /* 09h */
2579 U16 Reserved2; /* 0Ah */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2580 U16 MaxPersistentIDs; /* 0Ch */
2581 U16 NumPersistentIDsUsed; /* 0Eh */
2582 U8 Status; /* 10h */
2583 U8 Flags; /* 11h */
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2584 U16 MaxNumPhysicalMappedIDs;/* 12h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2585} CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2586 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t;
2587
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2588#define MPI_SASIOUNITPAGE2_PAGEVERSION (0x05)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2589
2590/* values for SAS IO Unit Page 2 Status field */
2591#define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02)
2592#define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01)
2593
2594/* values for SAS IO Unit Page 2 Flags field */
2595#define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2596/* Physical Mapping Modes */
2597#define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E)
2598#define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1)
2599#define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00)
2600#define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01)
2601#define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02)
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2602#define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2603
2604#define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10)
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]2605#define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2606
2607
2608typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3
2609{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2610 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2611 U32 Reserved1; /* 08h */
2612 U32 MaxInvalidDwordCount; /* 0Ch */
2613 U32 InvalidDwordCountTime; /* 10h */
2614 U32 MaxRunningDisparityErrorCount; /* 14h */
2615 U32 RunningDisparityErrorTime; /* 18h */
2616 U32 MaxLossDwordSynchCount; /* 1Ch */
2617 U32 LossDwordSynchCountTime; /* 20h */
2618 U32 MaxPhyResetProblemCount; /* 24h */
2619 U32 PhyResetProblemTime; /* 28h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2620} CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2621 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t;
2622
2623#define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00)
2624
2625
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2626/****************************************************************************
2627* SAS Expander Config Pages
2628****************************************************************************/
2629
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2630typedef struct _CONFIG_PAGE_SAS_EXPANDER_0
2631{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2632 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2633 U8 PhysicalPort; /* 08h */
2634 U8 Reserved1; /* 09h */
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2635 U16 EnclosureHandle; /* 0Ah */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2636 U64 SASAddress; /* 0Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2637 U32 DiscoveryStatus; /* 14h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2638 U16 DevHandle; /* 18h */
2639 U16 ParentDevHandle; /* 1Ah */
2640 U16 ExpanderChangeCount; /* 1Ch */
2641 U16 ExpanderRouteIndexes; /* 1Eh */
2642 U8 NumPhys; /* 20h */
2643 U8 SASLevel; /* 21h */
2644 U8 Flags; /* 22h */
2645 U8 Reserved3; /* 23h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2646} CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2647 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t;
2648
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2649#define MPI_SASEXPANDER0_PAGEVERSION (0x03)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2650
2651/* values for SAS Expander Page 0 DiscoveryStatus field */
2652#define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2653#define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2654#define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2655#define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008)
2656#define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2657#define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2658#define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2659#define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2660#define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2661#define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2662#define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2663#define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2664
2665/* values for SAS Expander Page 0 Flags field */
2666#define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02)
2667#define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01)
2668
2669
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2670typedef struct _CONFIG_PAGE_SAS_EXPANDER_1
2671{
2672 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2673 U8 PhysicalPort; /* 08h */
2674 U8 Reserved1; /* 09h */
2675 U16 Reserved2; /* 0Ah */
2676 U8 NumPhys; /* 0Ch */
2677 U8 Phy; /* 0Dh */
2678 U16 NumTableEntriesProgrammed; /* 0Eh */
2679 U8 ProgrammedLinkRate; /* 10h */
2680 U8 HwLinkRate; /* 11h */
2681 U16 AttachedDevHandle; /* 12h */
2682 U32 PhyInfo; /* 14h */
2683 U32 AttachedDeviceInfo; /* 18h */
2684 U16 OwnerDevHandle; /* 1Ch */
2685 U8 ChangeCount; /* 1Eh */
2686 U8 NegotiatedLinkRate; /* 1Fh */
2687 U8 PhyIdentifier; /* 20h */
2688 U8 AttachedPhyIdentifier; /* 21h */
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2689 U8 Reserved3; /* 22h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2690 U8 DiscoveryInfo; /* 23h */
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2691 U32 Reserved4; /* 24h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2692} CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1,
2693 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t;
2694
2695#define MPI_SASEXPANDER1_PAGEVERSION (0x01)
2696
2697/* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */
2698
2699/* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */
2700
2701/* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */
2702
2703/* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */
2704
2705/* values for SAS Expander Page 1 DiscoveryInfo field */
2706#define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY DISABLED (0x04)
2707#define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2708#define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2709
2710/* values for SAS Expander Page 1 NegotiatedLinkRate field */
2711#define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00)
2712#define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01)
2713#define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02)
2714#define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03)
2715#define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08)
2716#define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09)
2717
2718
2719/****************************************************************************
2720* SAS Device Config Pages
2721****************************************************************************/
2722
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2723typedef struct _CONFIG_PAGE_SAS_DEVICE_0
2724{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2725 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2726 U16 Slot; /* 08h */
2727 U16 EnclosureHandle; /* 0Ah */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2728 U64 SASAddress; /* 0Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2729 U16 ParentDevHandle; /* 14h */
2730 U8 PhyNum; /* 16h */
2731 U8 AccessStatus; /* 17h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2732 U16 DevHandle; /* 18h */
2733 U8 TargetID; /* 1Ah */
2734 U8 Bus; /* 1Bh */
2735 U32 DeviceInfo; /* 1Ch */
2736 U16 Flags; /* 20h */
2737 U8 PhysicalPort; /* 22h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2738 U8 Reserved2; /* 23h */
2739} CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2740 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t;
2741
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2742#define MPI_SASDEVICE0_PAGEVERSION (0x04)
2743
2744/* values for SAS Device Page 0 AccessStatus field */
2745#define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2746#define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2747#define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2748
2749/* values for SAS Device Page 0 Flags field */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2750#define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2751#define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2752#define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2753#define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2754#define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2755#define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2756#define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2757#define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004)
2758#define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002)
2759#define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2760
2761/* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */
2762
2763
2764typedef struct _CONFIG_PAGE_SAS_DEVICE_1
2765{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2766 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2767 U32 Reserved1; /* 08h */
2768 U64 SASAddress; /* 0Ch */
2769 U32 Reserved2; /* 14h */
2770 U16 DevHandle; /* 18h */
2771 U8 TargetID; /* 1Ah */
2772 U8 Bus; /* 1Bh */
2773 U8 InitialRegDeviceFIS[20];/* 1Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2774} CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2775 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t;
2776
2777#define MPI_SASDEVICE1_PAGEVERSION (0x00)
2778
2779
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2780typedef struct _CONFIG_PAGE_SAS_DEVICE_2
2781{
2782 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2783 U64 PhysicalIdentifier; /* 08h */
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]2784 U32 EnclosureMapping; /* 10h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2785} CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2,
2786 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t;
2787
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]2788#define MPI_SASDEVICE2_PAGEVERSION (0x01)
2789
2790/* defines for SAS Device Page 2 EnclosureMapping field */
2791#define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F)
2792#define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0)
2793#define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0)
2794#define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4)
2795#define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800)
2796#define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2797
2798
2799/****************************************************************************
2800* SAS PHY Config Pages
2801****************************************************************************/
2802
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2803typedef struct _CONFIG_PAGE_SAS_PHY_0
2804{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2805 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]2806 U16 OwnerDevHandle; /* 08h */
2807 U16 Reserved1; /* 0Ah */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2808 U64 SASAddress; /* 0Ch */
2809 U16 AttachedDevHandle; /* 14h */
2810 U8 AttachedPhyIdentifier; /* 16h */
2811 U8 Reserved2; /* 17h */
2812 U32 AttachedDeviceInfo; /* 18h */
2813 U8 ProgrammedLinkRate; /* 20h */
2814 U8 HwLinkRate; /* 21h */
2815 U8 ChangeCount; /* 22h */
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]2816 U8 Flags; /* 23h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2817 U32 PhyInfo; /* 24h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2818} CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2819 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t;
2820
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]2821#define MPI_SASPHY0_PAGEVERSION (0x01)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2822
2823/* values for SAS PHY Page 0 ProgrammedLinkRate field */
2824#define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0)
2825#define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
2826#define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80)
2827#define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90)
2828#define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F)
2829#define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
2830#define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08)
2831#define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09)
2832
2833/* values for SAS PHY Page 0 HwLinkRate field */
2834#define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0)
2835#define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80)
2836#define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90)
2837#define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F)
2838#define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08)
2839#define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09)
2840
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]2841/* values for SAS PHY Page 0 Flags field */
2842#define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2843
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2844/* values for SAS PHY Page 0 PhyInfo field */
2845#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
2846#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000)
2847#define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000)
2848
2849#define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
2850#define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
2851
2852#define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
2853#define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000)
2854#define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
2855#define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020)
2856
2857#define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F)
2858#define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000)
2859#define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001)
2860#define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002)
2861#define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003)
2862#define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008)
2863#define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009)
2864
2865
2866typedef struct _CONFIG_PAGE_SAS_PHY_1
2867{
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2868 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2869 U32 Reserved1; /* 08h */
2870 U32 InvalidDwordCount; /* 0Ch */
2871 U32 RunningDisparityErrorCount; /* 10h */
2872 U32 LossDwordSynchCount; /* 14h */
2873 U32 PhyResetProblemCount; /* 18h */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2874} CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2875 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t;
2876
2877#define MPI_SASPHY1_PAGEVERSION (0x00)
2878
2879
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2880/****************************************************************************
2881* SAS Enclosure Config Pages
2882****************************************************************************/
2883
2884typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0
2885{
2886 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2887 U32 Reserved1; /* 08h */
2888 U64 EnclosureLogicalID; /* 0Ch */
2889 U16 Flags; /* 14h */
2890 U16 EnclosureHandle; /* 16h */
2891 U16 NumSlots; /* 18h */
2892 U16 StartSlot; /* 1Ah */
2893 U8 StartTargetID; /* 1Ch */
2894 U8 StartBus; /* 1Dh */
2895 U8 SEPTargetID; /* 1Eh */
2896 U8 SEPBus; /* 1Fh */
2897 U32 Reserved2; /* 20h */
2898 U32 Reserved3; /* 24h */
2899} CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0,
2900 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t;
2901
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]2902#define MPI_SASENCLOSURE0_PAGEVERSION (0x01)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2903
2904/* values for SAS Enclosure Page 0 Flags field */
2905#define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020)
2906#define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010)
2907
2908#define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2909#define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2910#define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2911#define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2912#define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2913#define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
Christoph Hellwigccf3b7b2005-08-18 16:24:26 +0200[diff] [blame]2914#define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2915
2916
2917/****************************************************************************
2918* Log Config Pages
2919****************************************************************************/
2920/*
2921 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2922 * one and check NumLogEntries at runtime.
2923 */
2924#ifndef MPI_LOG_0_NUM_LOG_ENTRIES
2925#define MPI_LOG_0_NUM_LOG_ENTRIES (1)
2926#endif
2927
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2928#define MPI_LOG_0_LOG_DATA_LENGTH (0x1C)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2929
2930typedef struct _MPI_LOG_0_ENTRY
2931{
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2932 U32 TimeStamp; /* 00h */
2933 U32 Reserved1; /* 04h */
2934 U16 LogSequence; /* 08h */
2935 U16 LogEntryQualifier; /* 0Ah */
2936 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2937} MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY,
2938 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t;
2939
2940/* values for Log Page 0 LogEntry LogEntryQualifier field */
2941#define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2942#define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2943
2944typedef struct _CONFIG_PAGE_LOG_0
2945{
2946 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2947 U32 Reserved1; /* 08h */
2948 U32 Reserved2; /* 0Ch */
2949 U16 NumLogEntries; /* 10h */
2950 U16 Reserved3; /* 12h */
2951 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */
2952} CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0,
2953 LogPage0_t, MPI_POINTER pLogPage0_t;
2954
Moore, Eric4b915a72006-01-13 16:25:23 -0700[diff] [blame]2955#define MPI_LOG_0_PAGEVERSION (0x01)
Moore, Eric Dean c1a71d12005-05-11 17:37:38 -0600[diff] [blame]2956
2957
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2958#endif
2959