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Kumar Gala0bbaf062005-06-20 10:54:21 -05001/*
Paul Gortmaker3396c782012-01-27 13:36:01 +00002 * drivers/net/ethernet/freescale/gianfar.h
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Gianfar Ethernet Driver
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
Kumar Gala4c8d3d92005-11-13 16:06:30 -08009 * Maintainer: Kumar Gala
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +000010 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 *
Claudiu Manoil20862782014-02-17 12:53:14 +020012 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 * Still left to do:
20 * -Add support for module parameters
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 * -Add patch for ethtool phys id
22 */
23#ifndef __GIANFAR_H
24#define __GIANFAR_H
25
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <linux/kernel.h>
27#include <linux/sched.h>
28#include <linux/string.h>
29#include <linux/errno.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070032#include <linux/delay.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
36#include <linux/spinlock.h>
37#include <linux/mm.h>
Andy Flemingbb40dcb2005-09-23 22:54:21 -040038#include <linux/mii.h>
39#include <linux/phy.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040
41#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/uaccess.h>
44#include <linux/module.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <linux/crc32.h>
46#include <linux/workqueue.h>
47#include <linux/ethtool.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
Sebastian Poehn4aa3a712011-06-20 13:57:59 -070049struct ethtool_flow_spec_container {
50 struct ethtool_rx_flow_spec fs;
51 struct list_head list;
52};
53
54struct ethtool_rx_list {
55 struct list_head list;
56 unsigned int count;
57};
58
Linus Torvalds1da177e2005-04-16 15:20:36 -070059/* The maximum number of packets to be handled in one call of gfar_poll */
60#define GFAR_DEV_WEIGHT 64
61
Kumar Gala0bbaf062005-06-20 10:54:21 -050062/* Length for FCB */
63#define GMAC_FCB_LEN 8
64
Manfred Rudigier9c4886e2012-01-09 23:26:51 +000065/* Length for TxPAL */
66#define GMAC_TXPAL_LEN 16
67
Kumar Gala0bbaf062005-06-20 10:54:21 -050068/* Default padding amount */
69#define DEFAULT_PADDING 2
70
Linus Torvalds1da177e2005-04-16 15:20:36 -070071/* Number of bytes to align the rx bufs to */
72#define RXBUF_ALIGNMENT 64
73
74/* The number of bytes which composes a unit for the purpose of
75 * allocating data buffers. ie-for any given MTU, the data buffer
76 * will be the next highest multiple of 512 bytes. */
77#define INCREMENTAL_BUFFER_SIZE 512
78
Linus Torvalds1da177e2005-04-16 15:20:36 -070079#define PHY_INIT_TIMEOUT 100000
Linus Torvalds1da177e2005-04-16 15:20:36 -070080
Linus Torvalds1da177e2005-04-16 15:20:36 -070081#define DRV_NAME "gfar-enet"
Linus Torvalds1da177e2005-04-16 15:20:36 -070082extern const char gfar_driver_version[];
83
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +000084/* MAXIMUM NUMBER OF QUEUES SUPPORTED */
85#define MAX_TX_QS 0x8
86#define MAX_RX_QS 0x8
87
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +000088/* MAXIMUM NUMBER OF GROUPS SUPPORTED */
89#define MAXGROUPS 0x2
90
Linus Torvalds1da177e2005-04-16 15:20:36 -070091/* These need to be powers of 2 for this driver */
Linus Torvalds1da177e2005-04-16 15:20:36 -070092#define DEFAULT_TX_RING_SIZE 256
93#define DEFAULT_RX_RING_SIZE 256
Linus Torvalds1da177e2005-04-16 15:20:36 -070094
95#define GFAR_RX_MAX_RING_SIZE 256
96#define GFAR_TX_MAX_RING_SIZE 256
97
Andy Fleming7f7f5312005-11-11 12:38:59 -060098#define GFAR_MAX_FIFO_THRESHOLD 511
99#define GFAR_MAX_FIFO_STARVE 511
100#define GFAR_MAX_FIFO_STARVE_OFF 511
101
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102#define DEFAULT_RX_BUFFER_SIZE 1536
103#define TX_RING_MOD_MASK(size) (size-1)
104#define RX_RING_MOD_MASK(size) (size-1)
105#define JUMBO_BUFFER_SIZE 9728
106#define JUMBO_FRAME_SIZE 9600
107
Andy Fleming7f7f5312005-11-11 12:38:59 -0600108#define DEFAULT_FIFO_TX_THR 0x100
109#define DEFAULT_FIFO_TX_STARVE 0x40
110#define DEFAULT_FIFO_TX_STARVE_OFF 0x80
111#define DEFAULT_BD_STASH 1
Dai Harukia3cb96a2008-03-24 10:53:29 -0500112#define DEFAULT_STASH_LENGTH 96
Andy Fleming7f7f5312005-11-11 12:38:59 -0600113#define DEFAULT_STASH_INDEX 0
114
115/* The number of Exact Match registers */
116#define GFAR_EM_NUM 15
117
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118/* Latency of interface clock in nanoseconds */
Kumar Gala0bbaf062005-06-20 10:54:21 -0500119/* Interface clock latency , in this case, means the
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 * time described by a value of 1 in the interrupt
121 * coalescing registers' time fields. Since those fields
122 * refer to the time it takes for 64 clocks to pass, the
123 * latencies are as such:
124 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
125 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
126 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
127 */
128#define GFAR_GBIT_TIME 512
129#define GFAR_100_TIME 2560
130#define GFAR_10_TIME 25600
131
132#define DEFAULT_TX_COALESCE 1
133#define DEFAULT_TXCOUNT 16
Andy Fleming2f448912008-03-24 10:53:28 -0500134#define DEFAULT_TXTIME 21
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135
Dai Harukid080cd62008-04-09 19:37:51 -0500136#define DEFAULT_RXTIME 21
137
Dai Harukid080cd62008-04-09 19:37:51 -0500138#define DEFAULT_RX_COALESCE 0
139#define DEFAULT_RXCOUNT 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140
Andy Fleming1577ece2009-02-04 16:42:12 -0800141#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
142 | SUPPORTED_10baseT_Full \
143 | SUPPORTED_100baseT_Half \
144 | SUPPORTED_100baseT_Full \
145 | SUPPORTED_Autoneg \
146 | SUPPORTED_MII)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147
Claudiu Manoil23402bd2013-08-12 13:53:26 +0300148#define GFAR_SUPPORTED_GBIT (SUPPORTED_1000baseT_Full \
149 | SUPPORTED_Pause \
150 | SUPPORTED_Asym_Pause)
151
Kapil Junejad3c12872007-05-11 18:25:11 -0500152/* TBI register addresses */
153#define MII_TBICON 0x11
154
155/* TBICON register bit fields */
156#define TBICON_CLK_SELECT 0x0020
157
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158/* MAC register bits */
159#define MACCFG1_SOFT_RESET 0x80000000
160#define MACCFG1_RESET_RX_MC 0x00080000
161#define MACCFG1_RESET_TX_MC 0x00040000
162#define MACCFG1_RESET_RX_FUN 0x00020000
163#define MACCFG1_RESET_TX_FUN 0x00010000
164#define MACCFG1_LOOPBACK 0x00000100
165#define MACCFG1_RX_FLOW 0x00000020
166#define MACCFG1_TX_FLOW 0x00000010
167#define MACCFG1_SYNCD_RX_EN 0x00000008
168#define MACCFG1_RX_EN 0x00000004
169#define MACCFG1_SYNCD_TX_EN 0x00000002
170#define MACCFG1_TX_EN 0x00000001
171
172#define MACCFG2_INIT_SETTINGS 0x00007205
173#define MACCFG2_FULL_DUPLEX 0x00000001
174#define MACCFG2_IF 0x00000300
175#define MACCFG2_MII 0x00000100
176#define MACCFG2_GMII 0x00000200
177#define MACCFG2_HUGEFRAME 0x00000020
178#define MACCFG2_LENGTHCHECK 0x00000010
Scott Woodd87eb122008-07-11 18:04:45 -0500179#define MACCFG2_MPEN 0x00000008
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180
Sebastian Poehn4aa3a712011-06-20 13:57:59 -0700181#define ECNTRL_FIFM 0x00008000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182#define ECNTRL_INIT_SETTINGS 0x00001000
183#define ECNTRL_TBI_MODE 0x00000020
Andy Fleminge8a2b6a2006-12-01 12:01:06 -0600184#define ECNTRL_REDUCED_MODE 0x00000010
Andy Fleming7f7f5312005-11-11 12:38:59 -0600185#define ECNTRL_R100 0x00000008
Andy Fleminge8a2b6a2006-12-01 12:01:06 -0600186#define ECNTRL_REDUCED_MII_MODE 0x00000004
187#define ECNTRL_SGMII_MODE 0x00000002
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188
189#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
190
191#define MINFLR_INIT_SETTINGS 0x00000040
192
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000193/* Tqueue control */
194#define TQUEUE_EN0 0x00008000
195#define TQUEUE_EN1 0x00004000
196#define TQUEUE_EN2 0x00002000
197#define TQUEUE_EN3 0x00001000
198#define TQUEUE_EN4 0x00000800
199#define TQUEUE_EN5 0x00000400
200#define TQUEUE_EN6 0x00000200
201#define TQUEUE_EN7 0x00000100
202#define TQUEUE_EN_ALL 0x0000FF00
203
204#define TR03WT_WT0_MASK 0xFF000000
205#define TR03WT_WT1_MASK 0x00FF0000
206#define TR03WT_WT2_MASK 0x0000FF00
207#define TR03WT_WT3_MASK 0x000000FF
208
209#define TR47WT_WT4_MASK 0xFF000000
210#define TR47WT_WT5_MASK 0x00FF0000
211#define TR47WT_WT6_MASK 0x0000FF00
212#define TR47WT_WT7_MASK 0x000000FF
213
214/* Rqueue control */
215#define RQUEUE_EX0 0x00800000
216#define RQUEUE_EX1 0x00400000
217#define RQUEUE_EX2 0x00200000
218#define RQUEUE_EX3 0x00100000
219#define RQUEUE_EX4 0x00080000
220#define RQUEUE_EX5 0x00040000
221#define RQUEUE_EX6 0x00020000
222#define RQUEUE_EX7 0x00010000
223#define RQUEUE_EX_ALL 0x00FF0000
224
225#define RQUEUE_EN0 0x00000080
226#define RQUEUE_EN1 0x00000040
227#define RQUEUE_EN2 0x00000020
228#define RQUEUE_EN3 0x00000010
229#define RQUEUE_EN4 0x00000008
230#define RQUEUE_EN5 0x00000004
231#define RQUEUE_EN6 0x00000002
232#define RQUEUE_EN7 0x00000001
233#define RQUEUE_EN_ALL 0x000000FF
234
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235/* Init to do tx snooping for buffers and descriptors */
236#define DMACTRL_INIT_SETTINGS 0x000000c3
237#define DMACTRL_GRS 0x00000010
238#define DMACTRL_GTS 0x00000008
239
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000240#define TSTAT_CLEAR_THALT_ALL 0xFF000000
241#define TSTAT_CLEAR_THALT 0x80000000
242#define TSTAT_CLEAR_THALT0 0x80000000
243#define TSTAT_CLEAR_THALT1 0x40000000
244#define TSTAT_CLEAR_THALT2 0x20000000
245#define TSTAT_CLEAR_THALT3 0x10000000
246#define TSTAT_CLEAR_THALT4 0x08000000
247#define TSTAT_CLEAR_THALT5 0x04000000
248#define TSTAT_CLEAR_THALT6 0x02000000
249#define TSTAT_CLEAR_THALT7 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250
251/* Interrupt coalescing macros */
252#define IC_ICEN 0x80000000
253#define IC_ICFT_MASK 0x1fe00000
254#define IC_ICFT_SHIFT 21
255#define mk_ic_icft(x) \
256 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
257#define IC_ICTT_MASK 0x0000ffff
258#define mk_ic_ictt(x) (x&IC_ICTT_MASK)
259
260#define mk_ic_value(count, time) (IC_ICEN | \
261 mk_ic_icft(count) | \
262 mk_ic_ictt(time))
Dai Harukib46a8452008-12-16 15:29:52 -0800263#define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
264 IC_ICFT_SHIFT)
265#define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
266
267#define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
268#define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269
Andy Fleming31de1982008-12-16 15:33:40 -0800270#define skip_bd(bdp, stride, base, ring_size) ({ \
271 typeof(bdp) new_bd = (bdp) + (stride); \
272 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; })
273
274#define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size)
275
Manfred Rudigiercc772ab2010-04-08 23:10:03 +0000276#define RCTRL_TS_ENABLE 0x01000000
Kumar Gala0bbaf062005-06-20 10:54:21 -0500277#define RCTRL_PAL_MASK 0x001f0000
278#define RCTRL_VLEX 0x00002000
279#define RCTRL_FILREN 0x00001000
280#define RCTRL_GHTX 0x00000400
281#define RCTRL_IPCSEN 0x00000200
282#define RCTRL_TUCSEN 0x00000100
283#define RCTRL_PRSDEP_MASK 0x000000c0
284#define RCTRL_PRSDEP_INIT 0x000000c0
Sebastian Poehn4aa3a712011-06-20 13:57:59 -0700285#define RCTRL_PRSFM 0x00000020
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286#define RCTRL_PROM 0x00000008
Andy Fleming7f7f5312005-11-11 12:38:59 -0600287#define RCTRL_EMEN 0x00000002
Dai Haruki77ecaf22008-12-16 15:30:48 -0800288#define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
Sebastian Pöhnf3dc1582011-07-15 16:00:20 -0700289 RCTRL_TUCSEN | RCTRL_FILREN)
Dai Haruki77ecaf22008-12-16 15:30:48 -0800290#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
291 RCTRL_PRSDEP_INIT)
Kumar Gala0bbaf062005-06-20 10:54:21 -0500292#define RCTRL_EXTHASH (RCTRL_GHTX)
293#define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
Andy Fleming7f7f5312005-11-11 12:38:59 -0600294#define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
Kumar Gala0bbaf062005-06-20 10:54:21 -0500295
296
Claudiu Manoil6be5ed32013-03-19 07:40:03 +0000297#define RSTAT_CLEAR_RHALT 0x00800000
298#define RSTAT_CLEAR_RXF0 0x00000080
299#define RSTAT_RXF_MASK 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300
Kumar Gala0bbaf062005-06-20 10:54:21 -0500301#define TCTRL_IPCSEN 0x00004000
302#define TCTRL_TUCSEN 0x00002000
303#define TCTRL_VLINS 0x00001000
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000304#define TCTRL_THDF 0x00000800
305#define TCTRL_RFCPAUSE 0x00000010
306#define TCTRL_TFCPAUSE 0x00000008
307#define TCTRL_TXSCHED_MASK 0x00000006
308#define TCTRL_TXSCHED_INIT 0x00000000
Claudiu Manoilb98b8ba2012-09-23 22:39:08 +0000309/* priority scheduling */
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000310#define TCTRL_TXSCHED_PRIO 0x00000002
Claudiu Manoilb98b8ba2012-09-23 22:39:08 +0000311/* weighted round-robin scheduling (WRRS) */
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000312#define TCTRL_TXSCHED_WRRS 0x00000004
Claudiu Manoilb98b8ba2012-09-23 22:39:08 +0000313/* default WRRS weight and policy setting,
314 * tailored to the tr03wt and tr47wt registers:
315 * equal weight for all Tx Qs, measured in 64byte units
316 */
317#define DEFAULT_WRRS_WEIGHT 0x18181818
318
Kumar Gala0bbaf062005-06-20 10:54:21 -0500319#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
320
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321#define IEVENT_INIT_CLEAR 0xffffffff
322#define IEVENT_BABR 0x80000000
323#define IEVENT_RXC 0x40000000
324#define IEVENT_BSY 0x20000000
325#define IEVENT_EBERR 0x10000000
326#define IEVENT_MSRO 0x04000000
327#define IEVENT_GTSC 0x02000000
328#define IEVENT_BABT 0x01000000
329#define IEVENT_TXC 0x00800000
330#define IEVENT_TXE 0x00400000
331#define IEVENT_TXB 0x00200000
332#define IEVENT_TXF 0x00100000
333#define IEVENT_LC 0x00040000
334#define IEVENT_CRL 0x00020000
335#define IEVENT_XFUN 0x00010000
336#define IEVENT_RXB0 0x00008000
Scott Woodd87eb122008-07-11 18:04:45 -0500337#define IEVENT_MAG 0x00000800
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338#define IEVENT_GRSC 0x00000100
339#define IEVENT_RXF0 0x00000080
Kumar Gala0bbaf062005-06-20 10:54:21 -0500340#define IEVENT_FIR 0x00000008
341#define IEVENT_FIQ 0x00000004
342#define IEVENT_DPE 0x00000002
343#define IEVENT_PERR 0x00000001
Dai Haruki8c7396a2008-12-17 16:52:00 -0800344#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
Dai Harukid080cd62008-04-09 19:37:51 -0500346#define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347#define IEVENT_ERR_MASK \
348(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
349 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
Scott Woodd87eb122008-07-11 18:04:45 -0500350 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
Xiaotian Feng18a36c12009-05-26 20:48:04 -0700351 | IEVENT_MAG | IEVENT_BABR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352
353#define IMASK_INIT_CLEAR 0x00000000
354#define IMASK_BABR 0x80000000
355#define IMASK_RXC 0x40000000
356#define IMASK_BSY 0x20000000
357#define IMASK_EBERR 0x10000000
358#define IMASK_MSRO 0x04000000
Sandeep Gopalpet7c65ec72009-12-16 01:15:17 +0000359#define IMASK_GTSC 0x02000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360#define IMASK_BABT 0x01000000
361#define IMASK_TXC 0x00800000
362#define IMASK_TXEEN 0x00400000
363#define IMASK_TXBEN 0x00200000
364#define IMASK_TXFEN 0x00100000
365#define IMASK_LC 0x00040000
366#define IMASK_CRL 0x00020000
367#define IMASK_XFUN 0x00010000
368#define IMASK_RXB0 0x00008000
Scott Woodd87eb122008-07-11 18:04:45 -0500369#define IMASK_MAG 0x00000800
Sandeep Gopalpet7c65ec72009-12-16 01:15:17 +0000370#define IMASK_GRSC 0x00000100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371#define IMASK_RXFEN0 0x00000080
Kumar Gala0bbaf062005-06-20 10:54:21 -0500372#define IMASK_FIR 0x00000008
373#define IMASK_FIQ 0x00000004
374#define IMASK_DPE 0x00000002
375#define IMASK_PERR 0x00000001
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
377 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
Kumar Gala0bbaf062005-06-20 10:54:21 -0500378 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
379 | IMASK_PERR)
Dai Harukid080cd62008-04-09 19:37:51 -0500380#define IMASK_RTX_DISABLED ((~(IMASK_RXFEN0 | IMASK_TXFEN | IMASK_BSY)) \
381 & IMASK_DEFAULT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382
Andy Fleming7f7f5312005-11-11 12:38:59 -0600383/* Fifo management */
384#define FIFO_TX_THR_MASK 0x01ff
385#define FIFO_TX_STARVE_MASK 0x01ff
386#define FIFO_TX_STARVE_OFF_MASK 0x01ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387
388/* Attribute fields */
389
390/* This enables rx snooping for buffers and descriptors */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391#define ATTR_BDSTASH 0x00000800
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393#define ATTR_BUFSTASH 0x00004000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394
395#define ATTR_SNOOPING 0x000000c0
Andy Fleming7f7f5312005-11-11 12:38:59 -0600396#define ATTR_INIT_SETTINGS ATTR_SNOOPING
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397
398#define ATTRELI_INIT_SETTINGS 0x0
Andy Fleming7f7f5312005-11-11 12:38:59 -0600399#define ATTRELI_EL_MASK 0x3fff0000
400#define ATTRELI_EL(x) (x << 16)
401#define ATTRELI_EI_MASK 0x00003fff
402#define ATTRELI_EI(x) (x)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403
Dai Haruki5a5efed2008-12-16 15:34:50 -0800404#define BD_LFLAG(flags) ((flags) << 16)
Andy Fleming1fbe4932009-02-04 16:37:40 -0800405#define BD_LENGTH_MASK 0x0000ffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406
Sandeep Gopalpet7a8b3372009-11-02 07:03:40 +0000407#define FPR_FILER_MASK 0xFFFFFFFF
408#define MAX_FILER_IDX 0xFF
409
Sandeep Gopalpet1ccb8382009-12-16 01:14:58 +0000410/* This default RIR value directly corresponds
411 * to the 3-bit hash value generated */
412#define DEFAULT_RIR0 0x05397700
413
Sandeep Gopalpet7a8b3372009-11-02 07:03:40 +0000414/* RQFCR register bits */
415#define RQFCR_GPI 0x80000000
416#define RQFCR_HASHTBL_Q 0x00000000
417#define RQFCR_HASHTBL_0 0x00020000
418#define RQFCR_HASHTBL_1 0x00040000
419#define RQFCR_HASHTBL_2 0x00060000
420#define RQFCR_HASHTBL_3 0x00080000
421#define RQFCR_HASH 0x00010000
Sebastian Poehn380b1532011-07-07 04:30:29 -0700422#define RQFCR_QUEUE 0x0000FC00
Sandeep Gopalpet7a8b3372009-11-02 07:03:40 +0000423#define RQFCR_CLE 0x00000200
424#define RQFCR_RJE 0x00000100
425#define RQFCR_AND 0x00000080
426#define RQFCR_CMP_EXACT 0x00000000
427#define RQFCR_CMP_MATCH 0x00000020
428#define RQFCR_CMP_NOEXACT 0x00000040
429#define RQFCR_CMP_NOMATCH 0x00000060
430
431/* RQFCR PID values */
432#define RQFCR_PID_MASK 0x00000000
433#define RQFCR_PID_PARSE 0x00000001
434#define RQFCR_PID_ARB 0x00000002
435#define RQFCR_PID_DAH 0x00000003
436#define RQFCR_PID_DAL 0x00000004
437#define RQFCR_PID_SAH 0x00000005
438#define RQFCR_PID_SAL 0x00000006
439#define RQFCR_PID_ETY 0x00000007
440#define RQFCR_PID_VID 0x00000008
441#define RQFCR_PID_PRI 0x00000009
442#define RQFCR_PID_TOS 0x0000000A
443#define RQFCR_PID_L4P 0x0000000B
444#define RQFCR_PID_DIA 0x0000000C
445#define RQFCR_PID_SIA 0x0000000D
446#define RQFCR_PID_DPT 0x0000000E
447#define RQFCR_PID_SPT 0x0000000F
448
449/* RQFPR when PID is 0x0001 */
450#define RQFPR_HDR_GE_512 0x00200000
451#define RQFPR_LERR 0x00100000
452#define RQFPR_RAR 0x00080000
453#define RQFPR_RARQ 0x00040000
454#define RQFPR_AR 0x00020000
455#define RQFPR_ARQ 0x00010000
456#define RQFPR_EBC 0x00008000
457#define RQFPR_VLN 0x00004000
458#define RQFPR_CFI 0x00002000
459#define RQFPR_JUM 0x00001000
460#define RQFPR_IPF 0x00000800
461#define RQFPR_FIF 0x00000400
462#define RQFPR_IPV4 0x00000200
463#define RQFPR_IPV6 0x00000100
464#define RQFPR_ICC 0x00000080
465#define RQFPR_ICV 0x00000040
466#define RQFPR_TCP 0x00000020
467#define RQFPR_UDP 0x00000010
468#define RQFPR_TUC 0x00000008
469#define RQFPR_TUV 0x00000004
470#define RQFPR_PER 0x00000002
471#define RQFPR_EER 0x00000001
472
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473/* TxBD status field bits */
474#define TXBD_READY 0x8000
475#define TXBD_PADCRC 0x4000
476#define TXBD_WRAP 0x2000
477#define TXBD_INTERRUPT 0x1000
478#define TXBD_LAST 0x0800
479#define TXBD_CRC 0x0400
480#define TXBD_DEF 0x0200
481#define TXBD_HUGEFRAME 0x0080
482#define TXBD_LATECOLLISION 0x0080
483#define TXBD_RETRYLIMIT 0x0040
484#define TXBD_RETRYCOUNTMASK 0x003c
485#define TXBD_UNDERRUN 0x0002
Kumar Gala0bbaf062005-06-20 10:54:21 -0500486#define TXBD_TOE 0x0002
487
488/* Tx FCB param bits */
489#define TXFCB_VLN 0x80
490#define TXFCB_IP 0x40
491#define TXFCB_IP6 0x20
492#define TXFCB_TUP 0x10
493#define TXFCB_UDP 0x08
494#define TXFCB_CIP 0x04
495#define TXFCB_CTU 0x02
496#define TXFCB_NPH 0x01
497#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498
499/* RxBD status field bits */
500#define RXBD_EMPTY 0x8000
501#define RXBD_RO1 0x4000
502#define RXBD_WRAP 0x2000
503#define RXBD_INTERRUPT 0x1000
504#define RXBD_LAST 0x0800
505#define RXBD_FIRST 0x0400
506#define RXBD_MISS 0x0100
507#define RXBD_BROADCAST 0x0080
508#define RXBD_MULTICAST 0x0040
509#define RXBD_LARGE 0x0020
510#define RXBD_NONOCTET 0x0010
511#define RXBD_SHORT 0x0008
512#define RXBD_CRCERR 0x0004
513#define RXBD_OVERRUN 0x0002
514#define RXBD_TRUNCATED 0x0001
515#define RXBD_STATS 0x01ff
Andy Fleming99da5002008-03-24 10:53:27 -0500516#define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
517 | RXBD_CRCERR | RXBD_OVERRUN \
518 | RXBD_TRUNCATED)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519
Kumar Gala0bbaf062005-06-20 10:54:21 -0500520/* Rx FCB status field bits */
521#define RXFCB_VLN 0x8000
522#define RXFCB_IP 0x4000
523#define RXFCB_IP6 0x2000
524#define RXFCB_TUP 0x1000
525#define RXFCB_CIP 0x0800
526#define RXFCB_CTU 0x0400
527#define RXFCB_EIP 0x0200
528#define RXFCB_ETU 0x0100
Andy Fleming7f7f5312005-11-11 12:38:59 -0600529#define RXFCB_CSUM_MASK 0x0f00
Kumar Gala0bbaf062005-06-20 10:54:21 -0500530#define RXFCB_PERR_MASK 0x000c
531#define RXFCB_PERR_BADL3 0x0008
532
Joe Perches0015e552012-03-25 07:10:07 +0000533#define GFAR_INT_NAME_MAX (IFNAMSIZ + 6) /* '_g#_xx' */
Dai Harukic50a5d92008-12-17 16:51:32 -0800534
Linus Torvalds1da177e2005-04-16 15:20:36 -0700535struct txbd8
536{
Dai Haruki5a5efed2008-12-16 15:34:50 -0800537 union {
538 struct {
539 u16 status; /* Status Fields */
540 u16 length; /* Buffer length */
541 };
542 u32 lstatus;
543 };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544 u32 bufPtr; /* Buffer Pointer */
545};
546
Kumar Gala0bbaf062005-06-20 10:54:21 -0500547struct txfcb {
Andy Fleming7f7f5312005-11-11 12:38:59 -0600548 u8 flags;
Manfred Rudigierf0ee7ac2010-04-08 23:10:35 +0000549 u8 ptp; /* Flag to enable tx timestamping */
Kumar Gala0bbaf062005-06-20 10:54:21 -0500550 u8 l4os; /* Level 4 Header Offset */
551 u8 l3os; /* Level 3 Header Offset */
552 u16 phcs; /* Pseudo-header Checksum */
553 u16 vlctl; /* VLAN control word */
554};
555
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556struct rxbd8
557{
Dai Haruki5a5efed2008-12-16 15:34:50 -0800558 union {
559 struct {
560 u16 status; /* Status Fields */
561 u16 length; /* Buffer Length */
562 };
563 u32 lstatus;
564 };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 u32 bufPtr; /* Buffer Pointer */
566};
567
Kumar Gala0bbaf062005-06-20 10:54:21 -0500568struct rxfcb {
Andy Fleming7f7f5312005-11-11 12:38:59 -0600569 u16 flags;
Kumar Gala0bbaf062005-06-20 10:54:21 -0500570 u8 rq; /* Receive Queue index */
571 u8 pro; /* Layer 4 Protocol */
572 u16 reserved;
573 u16 vlctl; /* VLAN control word */
574};
575
Ben Menchacaa6d36d52010-03-24 05:05:02 +0000576struct gianfar_skb_cb {
Claudiu Manoil50ad0762013-08-30 15:01:15 +0300577 unsigned int bytes_sent; /* bytes-on-wire (i.e. no FCB) */
Ben Menchacaa6d36d52010-03-24 05:05:02 +0000578};
579
580#define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
581
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582struct rmon_mib
583{
584 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
585 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
586 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
587 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
588 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
589 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
590 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
591 u32 rbyt; /* 0x.69c - Receive Byte Counter */
592 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
593 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
594 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
595 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
596 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
597 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
598 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
599 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
600 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
601 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
602 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
603 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
604 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
605 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
606 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
607 u32 rdrp; /* 0x.6dc - Receive Drop Counter */
608 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
609 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
610 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
611 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
612 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
613 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
614 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
615 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
616 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
617 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
618 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
619 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
620 u8 res1[4];
621 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
622 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
623 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
624 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
625 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
626 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
627 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
628 u32 car1; /* 0x.730 - Carry Register One */
629 u32 car2; /* 0x.734 - Carry Register Two */
630 u32 cam1; /* 0x.738 - Carry Mask Register One */
631 u32 cam2; /* 0x.73c - Carry Mask Register Two */
632};
633
634struct gfar_extra_stats {
Paul Gortmaker212079d2013-02-12 15:38:19 -0500635 atomic64_t rx_large;
636 atomic64_t rx_short;
637 atomic64_t rx_nonoctet;
638 atomic64_t rx_crcerr;
639 atomic64_t rx_overrun;
640 atomic64_t rx_bsy;
641 atomic64_t rx_babr;
642 atomic64_t rx_trunc;
643 atomic64_t eberr;
644 atomic64_t tx_babt;
645 atomic64_t tx_underrun;
646 atomic64_t rx_skbmissing;
647 atomic64_t tx_timeout;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648};
649
650#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
Paul Gortmaker212079d2013-02-12 15:38:19 -0500651#define GFAR_EXTRA_STATS_LEN \
652 (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653
Paul Gortmaker68719782013-02-12 15:28:35 -0500654/* Number of stats exported via ethtool */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
656
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657struct gfar {
Kumar Gala0bbaf062005-06-20 10:54:21 -0500658 u32 tsec_id; /* 0x.000 - Controller ID register */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000659 u32 tsec_id2; /* 0x.004 - Controller ID2 register */
660 u8 res1[8];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500661 u32 ievent; /* 0x.010 - Interrupt Event Register */
662 u32 imask; /* 0x.014 - Interrupt Mask Register */
663 u32 edis; /* 0x.018 - Error Disabled Register */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000664 u32 emapg; /* 0x.01c - Group Error mapping register */
Kumar Gala0bbaf062005-06-20 10:54:21 -0500665 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
666 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
667 u32 ptv; /* 0x.028 - Pause Time Value Register */
668 u32 dmactrl; /* 0x.02c - DMA Control Register */
669 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000670 u8 res2[28];
671 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold
672 register */
673 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff
674 register */
675 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold
676 register */
677 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve
678 shutoff register */
679 u8 res3[44];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500680 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681 u8 res4[8];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500682 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000684 u8 res5[96];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500685 u32 tctrl; /* 0x.100 - Transmit Control Register */
686 u32 tstat; /* 0x.104 - Transmit Status Register */
687 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
688 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
689 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
690 u32 tqueue; /* 0x.114 - Transmit queue control register */
691 u8 res7[40];
692 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
693 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
694 u8 res8[52];
695 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
696 u8 res9a[4];
697 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
698 u8 res9b[4];
699 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
700 u8 res9c[4];
701 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
702 u8 res9d[4];
703 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
704 u8 res9e[4];
705 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
706 u8 res9f[4];
707 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
708 u8 res9g[4];
709 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
710 u8 res9h[4];
711 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
712 u8 res9[64];
713 u32 tbaseh; /* 0x.200 - TxBD base address high */
714 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
715 u8 res10a[4];
716 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
717 u8 res10b[4];
718 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
719 u8 res10c[4];
720 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
721 u8 res10d[4];
722 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
723 u8 res10e[4];
724 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
725 u8 res10f[4];
726 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
727 u8 res10g[4];
728 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
729 u8 res10[192];
730 u32 rctrl; /* 0x.300 - Receive Control Register */
731 u32 rstat; /* 0x.304 - Receive Status Register */
732 u8 res12[8];
733 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
734 u32 rqueue; /* 0x.314 - Receive queue control register */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000735 u32 rir0; /* 0x.318 - Ring mapping register 0 */
736 u32 rir1; /* 0x.31c - Ring mapping register 1 */
737 u32 rir2; /* 0x.320 - Ring mapping register 2 */
738 u32 rir3; /* 0x.324 - Ring mapping register 3 */
739 u8 res13[8];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500740 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
741 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
742 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
743 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
744 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
745 u8 res14[56];
746 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
747 u8 res15a[4];
748 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
749 u8 res15b[4];
750 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
751 u8 res15c[4];
752 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
753 u8 res15d[4];
754 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
755 u8 res15e[4];
756 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
757 u8 res15f[4];
758 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
759 u8 res15g[4];
760 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
761 u8 res15h[4];
762 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
763 u8 res16[64];
764 u32 rbaseh; /* 0x.400 - RxBD base address high */
765 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
766 u8 res17a[4];
767 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
768 u8 res17b[4];
769 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
770 u8 res17c[4];
771 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
772 u8 res17d[4];
773 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
774 u8 res17e[4];
775 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
776 u8 res17f[4];
777 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
778 u8 res17g[4];
779 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
780 u8 res17[192];
781 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
782 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
783 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
784 u32 hafdup; /* 0x.50c - Half Duplex Register */
785 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786 u8 res18[12];
Andy Flemingbb40dcb2005-09-23 22:54:21 -0400787 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000788 u32 ifctrl; /* 0x.538 - Interface control register */
Kumar Gala0bbaf062005-06-20 10:54:21 -0500789 u32 ifstat; /* 0x.53c - Interface Status Register */
790 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
791 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
792 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
793 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
794 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
795 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
796 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
797 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
798 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
799 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
800 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
801 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
802 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
803 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
804 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
805 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
806 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
807 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
808 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
809 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
810 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
811 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
812 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
813 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
814 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
815 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
816 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
817 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
818 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
819 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
820 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
821 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
822 u8 res20[192];
823 struct rmon_mib rmon; /* 0x.680-0x.73c */
824 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
825 u8 res21[188];
826 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
827 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
828 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
829 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
830 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
831 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
832 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
833 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834 u8 res22[96];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500835 u32 gaddr0; /* 0x.880 - Group address register 0 */
836 u32 gaddr1; /* 0x.884 - Group address register 1 */
837 u32 gaddr2; /* 0x.888 - Group address register 2 */
838 u32 gaddr3; /* 0x.88c - Group address register 3 */
839 u32 gaddr4; /* 0x.890 - Group address register 4 */
840 u32 gaddr5; /* 0x.894 - Group address register 5 */
841 u32 gaddr6; /* 0x.898 - Group address register 6 */
842 u32 gaddr7; /* 0x.89c - Group address register 7 */
843 u8 res23a[352];
844 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
845 u8 res23b[252];
846 u8 res23c[248];
847 u32 attr; /* 0x.bf8 - Attributes Register */
848 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000849 u8 res24[688];
850 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */
851 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */
852 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */
853 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */
854 u8 res25[16];
855 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
856 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
857 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
858 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */
859 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
860 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
861 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
862 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */
863 u8 res26[32];
864 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */
865 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */
866 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */
867 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */
868 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */
869 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */
870 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */
871 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */
872 u8 res27[208];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700873};
874
Andy Flemingb31a1d82008-12-16 15:29:15 -0800875/* Flags related to gianfar device features */
876#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
877#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
878#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
879#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
880#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
881#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
882#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
883#define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
884#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
885#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
886#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
Manfred Rudigiercc772ab2010-04-08 23:10:03 +0000887#define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800
Andy Flemingb31a1d82008-12-16 15:29:15 -0800888
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +0000889#if (MAXGROUPS == 2)
890#define DEFAULT_MAPPING 0xAA
891#else
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000892#define DEFAULT_MAPPING 0xFF
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +0000893#endif
894
Claudiu Manoil20862782014-02-17 12:53:14 +0200895#define ISRG_RR0 0x80000000
896#define ISRG_TR0 0x00800000
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +0000897
898/* The same driver can operate in two modes */
899/* SQ_SG_MODE: Single Queue Single Group Mode
900 * (Backward compatible mode)
901 * MQ_MG_MODE: Multi Queue Multi Group mode
902 */
903enum {
904 SQ_SG_MODE = 0,
905 MQ_MG_MODE
906};
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000907
Eric Dumazet1ac9ad12011-01-12 12:13:14 +0000908/*
909 * Per TX queue stats
910 */
911struct tx_q_stats {
912 unsigned long tx_packets;
913 unsigned long tx_bytes;
914};
915
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000916/**
917 * struct gfar_priv_tx_q - per tx queue structure
918 * @txlock: per queue tx spin lock
919 * @tx_skbuff:skb pointers
920 * @skb_curtx: to be used skb pointer
921 * @skb_dirtytx:the last used skb pointer
Eric Dumazet1ac9ad12011-01-12 12:13:14 +0000922 * @stats: bytes/packets stats
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000923 * @qindex: index of this queue
924 * @dev: back pointer to the dev structure
925 * @grp: back pointer to the group to which this queue belongs
926 * @tx_bd_base: First tx buffer descriptor
927 * @cur_tx: Next free ring entry
928 * @dirty_tx: First buffer in line to be transmitted
929 * @tx_ring_size: Tx ring size
930 * @num_txbdfree: number of free TxBds
931 * @txcoalescing: enable/disable tx coalescing
932 * @txic: transmit interrupt coalescing value
933 * @txcount: coalescing value if based on tx frame count
934 * @txtime: coalescing value if based on time
935 */
936struct gfar_priv_tx_q {
Claudiu Manoil0cd3fde2013-01-29 03:55:10 +0000937 /* cacheline 1 */
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000938 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000939 struct txbd8 *tx_bd_base;
940 struct txbd8 *cur_tx;
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000941 unsigned int num_txbdfree;
Claudiu Manoil0cd3fde2013-01-29 03:55:10 +0000942 unsigned short skb_curtx;
943 unsigned short tx_ring_size;
944 struct tx_q_stats stats;
945 struct gfar_priv_grp *grp;
946 /* cacheline 2 */
947 struct net_device *dev;
948 struct sk_buff **tx_skbuff;
949 struct txbd8 *dirty_tx;
950 unsigned short skb_dirtytx;
951 unsigned short qindex;
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000952 /* Configuration info for the coalescing features */
Claudiu Manoil0cd3fde2013-01-29 03:55:10 +0000953 unsigned int txcoalescing;
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000954 unsigned long txic;
Claudiu Manoil0cd3fde2013-01-29 03:55:10 +0000955 dma_addr_t tx_bd_dma_base;
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000956};
957
Sandeep Gopalpeta7f38042009-12-16 01:15:07 +0000958/*
959 * Per RX queue stats
960 */
961struct rx_q_stats {
962 unsigned long rx_packets;
963 unsigned long rx_bytes;
964 unsigned long rx_dropped;
965};
966
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000967/**
968 * struct gfar_priv_rx_q - per rx queue structure
969 * @rxlock: per queue rx spin lock
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000970 * @rx_skbuff: skb pointers
971 * @skb_currx: currently use skb pointer
972 * @rx_bd_base: First rx buffer descriptor
973 * @cur_rx: Next free rx ring entry
974 * @qindex: index of this queue
975 * @dev: back pointer to the dev structure
976 * @rx_ring_size: Rx ring size
977 * @rxcoalescing: enable/disable rx-coalescing
978 * @rxic: receive interrupt coalescing vlaue
979 */
980
981struct gfar_priv_rx_q {
982 spinlock_t rxlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000983 struct sk_buff ** rx_skbuff;
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000984 dma_addr_t rx_bd_dma_base;
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000985 struct rxbd8 *rx_bd_base;
986 struct rxbd8 *cur_rx;
987 struct net_device *dev;
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +0000988 struct gfar_priv_grp *grp;
Sandeep Gopalpeta7f38042009-12-16 01:15:07 +0000989 struct rx_q_stats stats;
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000990 u16 skb_currx;
991 u16 qindex;
992 unsigned int rx_ring_size;
993 /* RX Coalescing values */
994 unsigned char rxcoalescing;
995 unsigned long rxic;
996};
997
Claudiu Manoilee873fd2013-01-29 03:55:12 +0000998enum gfar_irqinfo_id {
999 GFAR_TX = 0,
1000 GFAR_RX = 1,
1001 GFAR_ER = 2,
1002 GFAR_NUM_IRQS = 3
1003};
1004
1005struct gfar_irqinfo {
1006 unsigned int irq;
1007 char name[GFAR_INT_NAME_MAX];
1008};
1009
Sandeep Gopalpetf4983702009-11-02 07:03:09 +00001010/**
1011 * struct gfar_priv_grp - per group structure
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +00001012 * @napi: the napi poll function
Sandeep Gopalpetf4983702009-11-02 07:03:09 +00001013 * @priv: back pointer to the priv structure
1014 * @regs: the ioremapped register space for this group
Claudiu Manoilee873fd2013-01-29 03:55:12 +00001015 * @irqinfo: TX/RX/ER irq data for this group
Sandeep Gopalpetf4983702009-11-02 07:03:09 +00001016 */
1017
1018struct gfar_priv_grp {
1019 spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES)));
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +00001020 struct napi_struct napi;
Sandeep Gopalpetf4983702009-11-02 07:03:09 +00001021 struct gfar_private *priv;
1022 struct gfar __iomem *regs;
Claudiu Manoil84915c62013-08-01 10:07:05 +03001023 unsigned int rstat;
Anton Vorontsov18294ad2009-11-04 12:53:00 +00001024 unsigned long num_rx_queues;
Claudiu Manoilee873fd2013-01-29 03:55:12 +00001025 unsigned long rx_bit_map;
1026 /* cacheline 3 */
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +00001027 unsigned int tstat;
Claudiu Manoilee873fd2013-01-29 03:55:12 +00001028 unsigned long num_tx_queues;
1029 unsigned long tx_bit_map;
Sandeep Gopalpetf4983702009-11-02 07:03:09 +00001030
Claudiu Manoilee873fd2013-01-29 03:55:12 +00001031 struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
Sandeep Gopalpetf4983702009-11-02 07:03:09 +00001032};
1033
Claudiu Manoilee873fd2013-01-29 03:55:12 +00001034#define gfar_irq(grp, ID) \
1035 ((grp)->irqinfo[GFAR_##ID])
1036
Anton Vorontsov7d350972010-06-30 06:39:12 +00001037enum gfar_errata {
1038 GFAR_ERRATA_74 = 0x01,
Anton Vorontsovdeb90ea2010-06-30 06:39:13 +00001039 GFAR_ERRATA_76 = 0x02,
Anton Vorontsov511d9342010-06-30 06:39:15 +00001040 GFAR_ERRATA_A002 = 0x04,
Alex Dubov4363c2fdd2011-03-16 17:57:13 +00001041 GFAR_ERRATA_12 = 0x08, /* a.k.a errata eTSEC49 */
Anton Vorontsov7d350972010-06-30 06:39:12 +00001042};
1043
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044/* Struct stolen almost completely (and shamelessly) from the FCC enet source
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001045 * (Ok, that's not so true anymore, but there is a family resemblance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
1047 * and tx_bd_base always point to the currently available buffer.
1048 * The dirty_tx tracks the current buffer that is being sent by the
1049 * controller. The cur_tx and dirty_tx are equal under both completely
1050 * empty and completely full conditions. The empty/ready indicator in
1051 * the buffer descriptor determines the actual condition.
1052 */
1053struct gfar_private {
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +00001054 unsigned int num_rx_queues;
Claudiu Manoilb597d202013-02-14 05:00:03 +00001055
1056 struct device *dev;
1057 struct net_device *ndev;
1058 enum gfar_errata errata;
1059 unsigned int rx_buffer_size;
1060
Claudiu Manoilba779712013-02-14 05:00:07 +00001061 u16 uses_rxfcb;
Claudiu Manoilb597d202013-02-14 05:00:03 +00001062 u16 padding;
1063
1064 /* HW time stamping enabled flag */
1065 int hwts_rx_en;
1066 int hwts_tx_en;
1067
1068 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1069 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
1070 struct gfar_priv_grp gfargrp[MAXGROUPS];
1071
1072 u32 device_flags;
1073
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +00001074 unsigned int mode;
Claudiu Manoilb597d202013-02-14 05:00:03 +00001075 unsigned int num_tx_queues;
1076 unsigned int num_grps;
1077
1078 /* Network Statistics */
1079 struct gfar_extra_stats extra_stats;
1080
1081 /* PHY stuff */
1082 phy_interface_t interface;
1083 struct device_node *phy_node;
1084 struct device_node *tbi_node;
1085 struct phy_device *phydev;
1086 struct mii_bus *mii_bus;
1087 int oldspeed;
1088 int oldduplex;
1089 int oldlink;
1090
1091 /* Bitfield update lock */
1092 spinlock_t bflock;
1093
1094 uint32_t msg_enable;
1095
1096 struct work_struct reset_task;
1097
1098 struct platform_device *ofdev;
1099 unsigned char
1100 extended_hash:1,
1101 bd_stash_en:1,
1102 rx_filer_enable:1,
1103 /* Wake-on-LAN enabled */
1104 wol_en:1,
1105 /* Enable priorty based Tx scheduling in Hw */
Claudiu Manoil23402bd2013-08-12 13:53:26 +03001106 prio_sched_en:1,
1107 /* Flow control flags */
1108 pause_aneg_en:1,
1109 tx_pause_en:1,
1110 rx_pause_en:1;
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +00001111
1112 /* The total tx and rx ring size for the enabled queues */
1113 unsigned int total_tx_ring_size;
1114 unsigned int total_rx_ring_size;
1115
Claudiu Manoil20862782014-02-17 12:53:14 +02001116 u32 rqueue;
1117 u32 tqueue;
1118
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +00001119 /* RX per device parameters */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120 unsigned int rx_stash_size;
Andy Fleming7f7f5312005-11-11 12:38:59 -06001121 unsigned int rx_stash_index;
Andy Flemingfef61082006-04-20 16:44:29 -05001122
Sandeep Gopalpet7a8b3372009-11-02 07:03:40 +00001123 u32 cur_filer_idx;
1124
Sebastian Poehn4aa3a712011-06-20 13:57:59 -07001125 /* RX queue filer rule set*/
1126 struct ethtool_rx_list rx_list;
1127 struct mutex rx_queue_access;
Andy Flemingfef61082006-04-20 16:44:29 -05001128
1129 /* Hash registers and their width */
1130 u32 __iomem *hash_regs[16];
1131 int hash_width;
1132
1133 /* global parameters */
Andy Fleming7f7f5312005-11-11 12:38:59 -06001134 unsigned int fifo_threshold;
1135 unsigned int fifo_starve;
1136 unsigned int fifo_starve_off;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001137
Wu Jiajun-B063786c43e042011-06-07 21:46:51 +00001138 /*Filer table*/
1139 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
1140 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141};
1142
Sandeep Gopalpet7a8b3372009-11-02 07:03:40 +00001143
Anton Vorontsov7d350972010-06-30 06:39:12 +00001144static inline int gfar_has_errata(struct gfar_private *priv,
1145 enum gfar_errata err)
1146{
1147 return priv->errata & err;
1148}
1149
Kim Phillipsfb017472013-01-11 12:18:21 +00001150static inline u32 gfar_read(unsigned __iomem *addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151{
1152 u32 val;
Kim Phillipsfb017472013-01-11 12:18:21 +00001153 val = ioread32be(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154 return val;
1155}
1156
Kim Phillipsfb017472013-01-11 12:18:21 +00001157static inline void gfar_write(unsigned __iomem *addr, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001158{
Kim Phillipsfb017472013-01-11 12:18:21 +00001159 iowrite32be(val, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001160}
1161
Sandeep Gopalpet7a8b3372009-11-02 07:03:40 +00001162static inline void gfar_write_filer(struct gfar_private *priv,
1163 unsigned int far, unsigned int fcr, unsigned int fpr)
1164{
1165 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1166
1167 gfar_write(&regs->rqfar, far);
1168 gfar_write(&regs->rqfcr, fcr);
1169 gfar_write(&regs->rqfpr, fpr);
1170}
1171
Sebastian Poehn4aa3a712011-06-20 13:57:59 -07001172static inline void gfar_read_filer(struct gfar_private *priv,
1173 unsigned int far, unsigned int *fcr, unsigned int *fpr)
1174{
1175 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1176
1177 gfar_write(&regs->rqfar, far);
1178 *fcr = gfar_read(&regs->rqfcr);
1179 *fpr = gfar_read(&regs->rqfpr);
1180}
1181
Claudiu Manoil20862782014-02-17 12:53:14 +02001182static inline void gfar_write_isrg(struct gfar_private *priv)
1183{
1184 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1185 u32 __iomem *baddr = &regs->isrg0;
1186 u32 isrg = 0;
1187 int grp_idx, i;
1188
1189 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1190 struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx];
1191
1192 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
1193 isrg |= (ISRG_RR0 >> i);
1194 }
1195
1196 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
1197 isrg |= (ISRG_TR0 >> i);
1198 }
1199
1200 gfar_write(baddr, isrg);
1201
1202 baddr++;
1203 isrg = 0;
1204 }
1205}
1206
Joe Perchesbddb2d92013-09-23 15:11:37 -07001207void lock_rx_qs(struct gfar_private *priv);
1208void lock_tx_qs(struct gfar_private *priv);
1209void unlock_rx_qs(struct gfar_private *priv);
1210void unlock_tx_qs(struct gfar_private *priv);
1211irqreturn_t gfar_receive(int irq, void *dev_id);
1212int startup_gfar(struct net_device *dev);
1213void stop_gfar(struct net_device *dev);
1214void gfar_halt(struct net_device *dev);
1215void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, int enable,
1216 u32 regnum, u32 read);
1217void gfar_configure_coalescing_all(struct gfar_private *priv);
Andy Fleming7f7f5312005-11-11 12:38:59 -06001218void gfar_init_sysfs(struct net_device *dev);
Michał Mirosławc8f44af2011-11-15 15:29:55 +00001219int gfar_set_features(struct net_device *dev, netdev_features_t features);
Joe Perchesbddb2d92013-09-23 15:11:37 -07001220void gfar_check_rx_parser_mode(struct gfar_private *priv);
1221void gfar_vlan_mode(struct net_device *dev, netdev_features_t features);
Andy Flemingbb40dcb2005-09-23 22:54:21 -04001222
Anton Vorontsovb2f66d12009-02-01 00:54:16 -08001223extern const struct ethtool_ops gfar_ethtool_ops;
1224
Sebastian Poehn4aa3a712011-06-20 13:57:59 -07001225#define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX))
1226
1227#define RQFCR_PID_PRI_MASK 0xFFFFFFF8
1228#define RQFCR_PID_L4P_MASK 0xFFFFFF00
1229#define RQFCR_PID_VID_MASK 0xFFFFF000
1230#define RQFCR_PID_PORT_MASK 0xFFFF0000
1231#define RQFCR_PID_MAC_MASK 0xFF000000
1232
1233struct gfar_mask_entry {
1234 unsigned int mask; /* The mask value which is valid form start to end */
1235 unsigned int start;
1236 unsigned int end;
1237 unsigned int block; /* Same block values indicate depended entries */
1238};
1239
1240/* Represents a receive filer table entry */
1241struct gfar_filer_entry {
1242 u32 ctrl;
1243 u32 prop;
1244};
1245
1246
1247/* The 20 additional entries are a shadow for one extra element */
1248struct filer_table {
1249 u32 index;
1250 struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20];
1251};
1252
Richard Cochran66636282012-04-03 22:59:19 +00001253/* The gianfar_ptp module will set this variable */
1254extern int gfar_phc_index;
1255
Linus Torvalds1da177e2005-04-16 15:20:36 -07001256#endif /* __GIANFAR_H */