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gerrit-public.fairphone.software / kernel / msm-5.4 / 22b1d707ffc99faebd86257ad19d5bb9fc624734 / . / include / asm-mips / txx9 / rbtx4938.h
blob: 8450f735d056433fe5cdd178c3d7466147a27053 [file] [log] [blame]
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]1/*
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]2 * Definitions for TX4937/TX4938
3 *
4 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
5 * terms of the GNU General Public License version 2. This program is
6 * licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 *
9 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
10 */
Atsushi Nemoto22b1d702008-07-11 00:31:36 +0900[diff] [blame^]11#ifndef __ASM_TXX9_RBTX4938_H
12#define __ASM_TXX9_RBTX4938_H
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]13
14#include <asm/addrspace.h>
Atsushi Nemotoc87abd72007-08-02 23:36:02 +0900[diff] [blame]15#include <asm/txx9irq.h>
Atsushi Nemoto22b1d702008-07-11 00:31:36 +0900[diff] [blame^]16#include <asm/txx9/tx4938.h>
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]17
18/* CS */
19#define RBTX4938_CE0 0x1c000000 /* 64M */
20#define RBTX4938_CE2 0x17f00000 /* 1M */
21
22/* Address map */
23#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000)
24#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002)
25#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004)
26#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006)
27#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008)
28#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000)
29#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002)
30#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004)
31#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000)
32#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002)
33#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004)
34#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006)
35#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008)
36#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a)
37#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c)
38#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000)
39#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000)
40#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002)
41#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008)
42#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a)
43#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000)
44#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002)
45#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004)
46#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000)
47
48/* Ethernet port address (Jumperless Mode (W12:Open)) */
49#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
50
51/* bits for ISTAT/IMASK/IMSTAT */
52#define RBTX4938_INTB_PCID 0
53#define RBTX4938_INTB_PCIC 1
54#define RBTX4938_INTB_PCIB 2
55#define RBTX4938_INTB_PCIA 3
56#define RBTX4938_INTB_RTC 4
57#define RBTX4938_INTB_ATA 5
58#define RBTX4938_INTB_MODEM 6
59#define RBTX4938_INTB_SWINT 7
60#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID)
61#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC)
62#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB)
63#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA)
64#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC)
65#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA)
66#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
67#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
68
Atsushi Nemoto66140c82008-04-14 21:49:07 +0900[diff] [blame]69#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
70#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR)
71#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
72#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
73#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
74#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
75#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
76#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
77#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
78#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
79#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
80#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
81#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
82#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
83#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
84#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
85#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
86#define rbtx4938_softresetlock_addr \
87 ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
88#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]89
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]90/*
91 * IRQ mappings
92 */
93
94#define RBTX4938_SOFT_INT0 0 /* not used */
95#define RBTX4938_SOFT_INT1 1 /* not used */
96#define RBTX4938_IRC_INT 2
97#define RBTX4938_TIMER_INT 7
98
99/* These are the virtual IRQ numbers, we divide all IRQ's into
100 * 'spaces', the 'space' determines where and how to enable/disable
101 * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
102 * IRQ hardware is supported.
103 */
104#define RBTX4938_NR_IRQ_LOCAL 8
105#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */
106#define RBTX4938_NR_IRQ_IOC 8
107
Atsushi Nemotoc87abd72007-08-02 23:36:02 +0900[diff] [blame]108#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
109#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]110
Atsushi Nemotoc87abd72007-08-02 23:36:02 +0900[diff] [blame]111#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE
112#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]113#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2)
114#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2)
115#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0)
116#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1)
117#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7)
118
119#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0
120#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7
121
122#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */
123#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */
124#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG
125#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL)
126#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC)
127#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
128
129#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0)
130#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1)
131#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT)
132#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT)
133#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
134#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
135#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
136#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
Ralf Baechle21a151d2007-10-11 23:46:15 +0100[diff] [blame]137#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]138#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
139#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
140#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
141#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
142#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
143#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
144#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
145#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
146#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
147#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
148#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
149#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
150#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
151#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
152#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
153#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
154#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
155#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
156#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
157
158
159/* IOC (PCI, etc) */
160#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC)
161/* Onboard 10M Ether */
162#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1)
163
164#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
165#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
166
Atsushi Nemoto22b1d702008-07-11 00:31:36 +0900[diff] [blame^]167#endif /* __ASM_TXX9_RBTX4938_H */