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gerrit-public.fairphone.software / kernel / msm-5.4 / 234323ba4f226d9d3d90d5c30f7883362a810a20 / . / arch / arm / mach-u300 / core.c
blob: bc2339192fd96a310d514323a4a84acfb2495b55 [file] [log] [blame]
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1/*
2 *
3 * arch/arm/mach-u300/core.c
4 *
5 *
Linus Walleijfcb28d22012-08-13 10:11:15 +0200[diff] [blame]6 * Copyright (C) 2007-2012 ST-Ericsson SA
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]7 * License terms: GNU General Public License (GPL) version 2
8 * Core platform support, IRQ handling and device definitions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/interrupt.h>
15#include <linux/bitops.h>
16#include <linux/device.h>
17#include <linux/mm.h>
18#include <linux/termios.h>
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]19#include <linux/dmaengine.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]20#include <linux/amba/bus.h>
Linus Walleija64ae392012-02-20 21:26:30 +0100[diff] [blame]21#include <linux/amba/mmci.h>
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]22#include <linux/amba/serial.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]23#include <linux/platform_device.h>
24#include <linux/gpio.h>
Linus Walleijb7276b22010-08-05 07:58:58 +0100[diff] [blame]25#include <linux/clk.h>
26#include <linux/err.h>
Linus Walleij93ac5a52010-09-13 00:35:37 +0200[diff] [blame]27#include <linux/mtd/nand.h>
28#include <linux/mtd/fsmc.h>
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]29#include <linux/pinctrl/machine.h>
Linus Walleij28a8d142012-02-09 01:52:22 +0100[diff] [blame]30#include <linux/pinctrl/consumer.h>
Linus Walleij51dddfe2012-01-20 17:53:15 +0100[diff] [blame]31#include <linux/pinctrl/pinconf-generic.h>
Jon Medhurstd70a5962011-08-04 15:41:42 +0100[diff] [blame]32#include <linux/dma-mapping.h>
Linus Walleij50667d62012-06-19 23:44:25 +0200[diff] [blame]33#include <linux/platform_data/clk-u300.h>
Linus Walleij65172852012-08-13 10:56:43 +0200[diff] [blame]34#include <linux/platform_data/pinctrl-coh901.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]35
36#include <asm/types.h>
37#include <asm/setup.h>
38#include <asm/memory.h>
39#include <asm/hardware/vic.h>
40#include <asm/mach/map.h>
41#include <asm/mach/irq.h>
Linus Walleij234323b2012-08-13 11:35:55 +0200[diff] [blame^]42#include <asm/mach-types.h>
43#include <asm/mach/arch.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]44
Linus Walleij93ac5a52010-09-13 00:35:37 +0200[diff] [blame]45#include <mach/coh901318.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]46#include <mach/hardware.h>
47#include <mach/syscon.h>
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]48#include <mach/dma_channels.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]49
Linus Walleij234323b2012-08-13 11:35:55 +0200[diff] [blame^]50#include "timer.h"
Linus Walleijc7c8c782009-08-14 10:59:05 +0100[diff] [blame]51#include "spi.h"
Linus Walleij6be2a0c2009-08-13 21:42:01 +0100[diff] [blame]52#include "i2c.h"
Linus Walleija64ae392012-02-20 21:26:30 +0100[diff] [blame]53#include "u300-gpio.h"
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]54
55/*
56 * Static I/O mappings that are needed for booting the U300 platforms. The
57 * only things we need are the areas where we find the timer, syscon and
58 * intcon, since the remaining device drivers will map their own memory
59 * physical to virtual as the need arise.
60 */
61static struct map_desc u300_io_desc[] __initdata = {
62 {
63 .virtual = U300_SLOW_PER_VIRT_BASE,
64 .pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
65 .length = SZ_64K,
66 .type = MT_DEVICE,
67 },
68 {
69 .virtual = U300_AHB_PER_VIRT_BASE,
70 .pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
71 .length = SZ_32K,
72 .type = MT_DEVICE,
73 },
74 {
75 .virtual = U300_FAST_PER_VIRT_BASE,
76 .pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
77 .length = SZ_32K,
78 .type = MT_DEVICE,
79 },
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]80};
81
Linus Walleij234323b2012-08-13 11:35:55 +0200[diff] [blame^]82static void __init u300_map_io(void)
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]83{
84 iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
Jon Medhurstd70a5962011-08-04 15:41:42 +0100[diff] [blame]85 /* We enable a real big DMA buffer if need be. */
86 init_consistent_dma_size(SZ_4M);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]87}
88
89/*
90 * Declaration of devices found on the U300 board and
91 * their respective memory locations.
92 */
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]93
94static struct amba_pl011_data uart0_plat_data = {
95#ifdef CONFIG_COH901318
96 .dma_filter = coh901318_filter_id,
97 .dma_rx_param = (void *) U300_DMA_UART0_RX,
98 .dma_tx_param = (void *) U300_DMA_UART0_TX,
99#endif
100};
101
Russell King6db2a452011-12-18 15:26:38 +0000[diff] [blame]102/* Slow device at 0x3000 offset */
103static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
104 { IRQ_U300_UART0 }, &uart0_plat_data);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]105
106/* The U335 have an additional UART1 on the APP CPU */
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]107static struct amba_pl011_data uart1_plat_data = {
108#ifdef CONFIG_COH901318
109 .dma_filter = coh901318_filter_id,
110 .dma_rx_param = (void *) U300_DMA_UART1_RX,
111 .dma_tx_param = (void *) U300_DMA_UART1_TX,
112#endif
113};
114
Russell King6db2a452011-12-18 15:26:38 +0000[diff] [blame]115/* Fast device at 0x7000 offset */
116static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
117 { IRQ_U300_UART1 }, &uart1_plat_data);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]118
Russell King6db2a452011-12-18 15:26:38 +0000[diff] [blame]119/* AHB device at 0x4000 offset */
120static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]121
Russell King6db2a452011-12-18 15:26:38 +0000[diff] [blame]122/* Fast device at 0x6000 offset */
123static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
124 { IRQ_U300_SPI }, NULL);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]125
Russell King6db2a452011-12-18 15:26:38 +0000[diff] [blame]126/* Fast device at 0x1000 offset */
127#define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
128
Linus Walleija64ae392012-02-20 21:26:30 +0100[diff] [blame]129static struct mmci_platform_data mmcsd_platform_data = {
130 /*
131 * Do not set ocr_mask or voltage translation function,
132 * we have a regulator we can control instead.
133 */
134 .f_max = 24000000,
135 .gpio_wp = -1,
136 .gpio_cd = U300_GPIO_PIN_MMC_CD,
137 .cd_invert = true,
138 .capabilities = MMC_CAP_MMC_HIGHSPEED |
139 MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
140#ifdef CONFIG_COH901318
141 .dma_filter = coh901318_filter_id,
142 .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
143 /* Don't specify a TX channel, this RX channel is bidirectional */
144#endif
145};
146
Russell King6db2a452011-12-18 15:26:38 +0000[diff] [blame]147static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
Linus Walleija64ae392012-02-20 21:26:30 +0100[diff] [blame]148 U300_MMCSD_IRQS, &mmcsd_platform_data);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]149
150/*
151 * The order of device declaration may be important, since some devices
152 * have dependencies on other devices being initialized first.
153 */
154static struct amba_device *amba_devs[] __initdata = {
155 &uart0_device,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]156 &uart1_device,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]157 &pl022_device,
158 &pl172_device,
159 &mmcsd_device,
160};
161
162/* Here follows a list of all hw resources that the platform devices
163 * allocate. Note, clock dependencies are not included
164 */
165
166static struct resource gpio_resources[] = {
167 {
168 .start = U300_GPIO_BASE,
169 .end = (U300_GPIO_BASE + SZ_4K - 1),
170 .flags = IORESOURCE_MEM,
171 },
172 {
173 .name = "gpio0",
174 .start = IRQ_U300_GPIO_PORT0,
175 .end = IRQ_U300_GPIO_PORT0,
176 .flags = IORESOURCE_IRQ,
177 },
178 {
179 .name = "gpio1",
180 .start = IRQ_U300_GPIO_PORT1,
181 .end = IRQ_U300_GPIO_PORT1,
182 .flags = IORESOURCE_IRQ,
183 },
184 {
185 .name = "gpio2",
186 .start = IRQ_U300_GPIO_PORT2,
187 .end = IRQ_U300_GPIO_PORT2,
188 .flags = IORESOURCE_IRQ,
189 },
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]190 {
191 .name = "gpio3",
192 .start = IRQ_U300_GPIO_PORT3,
193 .end = IRQ_U300_GPIO_PORT3,
194 .flags = IORESOURCE_IRQ,
195 },
196 {
197 .name = "gpio4",
198 .start = IRQ_U300_GPIO_PORT4,
199 .end = IRQ_U300_GPIO_PORT4,
200 .flags = IORESOURCE_IRQ,
201 },
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]202 {
203 .name = "gpio5",
204 .start = IRQ_U300_GPIO_PORT5,
205 .end = IRQ_U300_GPIO_PORT5,
206 .flags = IORESOURCE_IRQ,
207 },
208 {
209 .name = "gpio6",
210 .start = IRQ_U300_GPIO_PORT6,
211 .end = IRQ_U300_GPIO_PORT6,
212 .flags = IORESOURCE_IRQ,
213 },
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]214};
215
216static struct resource keypad_resources[] = {
217 {
218 .start = U300_KEYPAD_BASE,
219 .end = U300_KEYPAD_BASE + SZ_4K - 1,
220 .flags = IORESOURCE_MEM,
221 },
222 {
223 .name = "coh901461-press",
224 .start = IRQ_U300_KEYPAD_KEYBF,
225 .end = IRQ_U300_KEYPAD_KEYBF,
226 .flags = IORESOURCE_IRQ,
227 },
228 {
229 .name = "coh901461-release",
230 .start = IRQ_U300_KEYPAD_KEYBR,
231 .end = IRQ_U300_KEYPAD_KEYBR,
232 .flags = IORESOURCE_IRQ,
233 },
234};
235
236static struct resource rtc_resources[] = {
237 {
238 .start = U300_RTC_BASE,
239 .end = U300_RTC_BASE + SZ_4K - 1,
240 .flags = IORESOURCE_MEM,
241 },
242 {
243 .start = IRQ_U300_RTC,
244 .end = IRQ_U300_RTC,
245 .flags = IORESOURCE_IRQ,
246 },
247};
248
249/*
250 * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
251 * but these are not yet used by the driver.
252 */
253static struct resource fsmc_resources[] = {
254 {
Linus Walleij93ac5a52010-09-13 00:35:37 +0200[diff] [blame]255 .name = "nand_data",
256 .start = U300_NAND_CS0_PHYS_BASE,
257 .end = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
258 .flags = IORESOURCE_MEM,
259 },
260 {
261 .name = "fsmc_regs",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]262 .start = U300_NAND_IF_PHYS_BASE,
263 .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
264 .flags = IORESOURCE_MEM,
265 },
266};
267
268static struct resource i2c0_resources[] = {
269 {
270 .start = U300_I2C0_BASE,
271 .end = U300_I2C0_BASE + SZ_4K - 1,
272 .flags = IORESOURCE_MEM,
273 },
274 {
275 .start = IRQ_U300_I2C0,
276 .end = IRQ_U300_I2C0,
277 .flags = IORESOURCE_IRQ,
278 },
279};
280
281static struct resource i2c1_resources[] = {
282 {
283 .start = U300_I2C1_BASE,
284 .end = U300_I2C1_BASE + SZ_4K - 1,
285 .flags = IORESOURCE_MEM,
286 },
287 {
288 .start = IRQ_U300_I2C1,
289 .end = IRQ_U300_I2C1,
290 .flags = IORESOURCE_IRQ,
291 },
292
293};
294
295static struct resource wdog_resources[] = {
296 {
297 .start = U300_WDOG_BASE,
298 .end = U300_WDOG_BASE + SZ_4K - 1,
299 .flags = IORESOURCE_MEM,
300 },
301 {
302 .start = IRQ_U300_WDOG,
303 .end = IRQ_U300_WDOG,
304 .flags = IORESOURCE_IRQ,
305 }
306};
307
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]308static struct resource dma_resource[] = {
309 {
310 .start = U300_DMAC_BASE,
311 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
312 .flags = IORESOURCE_MEM,
313 },
314 {
315 .start = IRQ_U300_DMA,
316 .end = IRQ_U300_DMA,
317 .flags = IORESOURCE_IRQ,
318 }
319};
320
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]321/* points out all dma slave channels.
322 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
323 * Select all channels from A to B, end of list is marked with -1,-1
324 */
325static int dma_slave_channels[] = {
326 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
327 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
328
329/* points out all dma memcpy channels. */
330static int dma_memcpy_channels[] = {
331 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
332
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]333/** register dma for memory access
334 *
335 * active 1 means dma intends to access memory
336 * 0 means dma wont access memory
337 */
338static void coh901318_access_memory_state(struct device *dev, bool active)
339{
340}
341
342#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
343 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
344 COH901318_CX_CFG_LCR_DISABLE | \
345 COH901318_CX_CFG_TC_IRQ_ENABLE | \
346 COH901318_CX_CFG_BE_IRQ_ENABLE)
347#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
348 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
349 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
350 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
351 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
352 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
353 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
354 COH901318_CX_CTRL_TCP_DISABLE | \
355 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
356 COH901318_CX_CTRL_HSP_DISABLE | \
357 COH901318_CX_CTRL_HSS_DISABLE | \
358 COH901318_CX_CTRL_DDMA_LEGACY | \
359 COH901318_CX_CTRL_PRDD_SOURCE)
360#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
361 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
362 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
363 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
364 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
365 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
366 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
367 COH901318_CX_CTRL_TCP_DISABLE | \
368 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
369 COH901318_CX_CTRL_HSP_DISABLE | \
370 COH901318_CX_CTRL_HSS_DISABLE | \
371 COH901318_CX_CTRL_DDMA_LEGACY | \
372 COH901318_CX_CTRL_PRDD_SOURCE)
373#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
374 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
375 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
376 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
377 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
378 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
379 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
380 COH901318_CX_CTRL_TCP_DISABLE | \
381 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
382 COH901318_CX_CTRL_HSP_DISABLE | \
383 COH901318_CX_CTRL_HSS_DISABLE | \
384 COH901318_CX_CTRL_DDMA_LEGACY | \
385 COH901318_CX_CTRL_PRDD_SOURCE)
386
387const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
388 {
389 .number = U300_DMA_MSL_TX_0,
390 .name = "MSL TX 0",
391 .priority_high = 0,
392 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
393 },
394 {
395 .number = U300_DMA_MSL_TX_1,
396 .name = "MSL TX 1",
397 .priority_high = 0,
398 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
399 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]400 COH901318_CX_CFG_LCR_DISABLE |
401 COH901318_CX_CFG_TC_IRQ_ENABLE |
402 COH901318_CX_CFG_BE_IRQ_ENABLE,
403 .param.ctrl_lli_chained = 0 |
404 COH901318_CX_CTRL_TC_ENABLE |
405 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
406 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
407 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
408 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
409 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
410 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
411 COH901318_CX_CTRL_TCP_DISABLE |
412 COH901318_CX_CTRL_TC_IRQ_DISABLE |
413 COH901318_CX_CTRL_HSP_ENABLE |
414 COH901318_CX_CTRL_HSS_DISABLE |
415 COH901318_CX_CTRL_DDMA_LEGACY |
416 COH901318_CX_CTRL_PRDD_SOURCE,
417 .param.ctrl_lli = 0 |
418 COH901318_CX_CTRL_TC_ENABLE |
419 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
420 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
421 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
422 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
423 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
424 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
425 COH901318_CX_CTRL_TCP_ENABLE |
426 COH901318_CX_CTRL_TC_IRQ_DISABLE |
427 COH901318_CX_CTRL_HSP_ENABLE |
428 COH901318_CX_CTRL_HSS_DISABLE |
429 COH901318_CX_CTRL_DDMA_LEGACY |
430 COH901318_CX_CTRL_PRDD_SOURCE,
431 .param.ctrl_lli_last = 0 |
432 COH901318_CX_CTRL_TC_ENABLE |
433 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
434 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
435 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
436 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
437 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
438 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
439 COH901318_CX_CTRL_TCP_ENABLE |
440 COH901318_CX_CTRL_TC_IRQ_ENABLE |
441 COH901318_CX_CTRL_HSP_ENABLE |
442 COH901318_CX_CTRL_HSS_DISABLE |
443 COH901318_CX_CTRL_DDMA_LEGACY |
444 COH901318_CX_CTRL_PRDD_SOURCE,
445 },
446 {
447 .number = U300_DMA_MSL_TX_2,
448 .name = "MSL TX 2",
449 .priority_high = 0,
450 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
451 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]452 COH901318_CX_CFG_LCR_DISABLE |
453 COH901318_CX_CFG_TC_IRQ_ENABLE |
454 COH901318_CX_CFG_BE_IRQ_ENABLE,
455 .param.ctrl_lli_chained = 0 |
456 COH901318_CX_CTRL_TC_ENABLE |
457 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
458 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
459 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
460 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
461 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
462 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
463 COH901318_CX_CTRL_TCP_DISABLE |
464 COH901318_CX_CTRL_TC_IRQ_DISABLE |
465 COH901318_CX_CTRL_HSP_ENABLE |
466 COH901318_CX_CTRL_HSS_DISABLE |
467 COH901318_CX_CTRL_DDMA_LEGACY |
468 COH901318_CX_CTRL_PRDD_SOURCE,
469 .param.ctrl_lli = 0 |
470 COH901318_CX_CTRL_TC_ENABLE |
471 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
472 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
473 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
474 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
475 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
476 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
477 COH901318_CX_CTRL_TCP_ENABLE |
478 COH901318_CX_CTRL_TC_IRQ_DISABLE |
479 COH901318_CX_CTRL_HSP_ENABLE |
480 COH901318_CX_CTRL_HSS_DISABLE |
481 COH901318_CX_CTRL_DDMA_LEGACY |
482 COH901318_CX_CTRL_PRDD_SOURCE,
483 .param.ctrl_lli_last = 0 |
484 COH901318_CX_CTRL_TC_ENABLE |
485 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
486 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
487 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
488 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
489 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
490 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
491 COH901318_CX_CTRL_TCP_ENABLE |
492 COH901318_CX_CTRL_TC_IRQ_ENABLE |
493 COH901318_CX_CTRL_HSP_ENABLE |
494 COH901318_CX_CTRL_HSS_DISABLE |
495 COH901318_CX_CTRL_DDMA_LEGACY |
496 COH901318_CX_CTRL_PRDD_SOURCE,
497 .desc_nbr_max = 10,
498 },
499 {
500 .number = U300_DMA_MSL_TX_3,
501 .name = "MSL TX 3",
502 .priority_high = 0,
503 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
504 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]505 COH901318_CX_CFG_LCR_DISABLE |
506 COH901318_CX_CFG_TC_IRQ_ENABLE |
507 COH901318_CX_CFG_BE_IRQ_ENABLE,
508 .param.ctrl_lli_chained = 0 |
509 COH901318_CX_CTRL_TC_ENABLE |
510 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
511 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
512 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
513 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
514 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
515 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
516 COH901318_CX_CTRL_TCP_DISABLE |
517 COH901318_CX_CTRL_TC_IRQ_DISABLE |
518 COH901318_CX_CTRL_HSP_ENABLE |
519 COH901318_CX_CTRL_HSS_DISABLE |
520 COH901318_CX_CTRL_DDMA_LEGACY |
521 COH901318_CX_CTRL_PRDD_SOURCE,
522 .param.ctrl_lli = 0 |
523 COH901318_CX_CTRL_TC_ENABLE |
524 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
525 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
526 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
527 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
528 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
529 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
530 COH901318_CX_CTRL_TCP_ENABLE |
531 COH901318_CX_CTRL_TC_IRQ_DISABLE |
532 COH901318_CX_CTRL_HSP_ENABLE |
533 COH901318_CX_CTRL_HSS_DISABLE |
534 COH901318_CX_CTRL_DDMA_LEGACY |
535 COH901318_CX_CTRL_PRDD_SOURCE,
536 .param.ctrl_lli_last = 0 |
537 COH901318_CX_CTRL_TC_ENABLE |
538 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
539 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
540 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
541 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
542 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
543 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
544 COH901318_CX_CTRL_TCP_ENABLE |
545 COH901318_CX_CTRL_TC_IRQ_ENABLE |
546 COH901318_CX_CTRL_HSP_ENABLE |
547 COH901318_CX_CTRL_HSS_DISABLE |
548 COH901318_CX_CTRL_DDMA_LEGACY |
549 COH901318_CX_CTRL_PRDD_SOURCE,
550 },
551 {
552 .number = U300_DMA_MSL_TX_4,
553 .name = "MSL TX 4",
554 .priority_high = 0,
555 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
556 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]557 COH901318_CX_CFG_LCR_DISABLE |
558 COH901318_CX_CFG_TC_IRQ_ENABLE |
559 COH901318_CX_CFG_BE_IRQ_ENABLE,
560 .param.ctrl_lli_chained = 0 |
561 COH901318_CX_CTRL_TC_ENABLE |
562 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
563 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
564 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
565 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
566 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
567 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
568 COH901318_CX_CTRL_TCP_DISABLE |
569 COH901318_CX_CTRL_TC_IRQ_DISABLE |
570 COH901318_CX_CTRL_HSP_ENABLE |
571 COH901318_CX_CTRL_HSS_DISABLE |
572 COH901318_CX_CTRL_DDMA_LEGACY |
573 COH901318_CX_CTRL_PRDD_SOURCE,
574 .param.ctrl_lli = 0 |
575 COH901318_CX_CTRL_TC_ENABLE |
576 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
577 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
578 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
579 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
580 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
581 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
582 COH901318_CX_CTRL_TCP_ENABLE |
583 COH901318_CX_CTRL_TC_IRQ_DISABLE |
584 COH901318_CX_CTRL_HSP_ENABLE |
585 COH901318_CX_CTRL_HSS_DISABLE |
586 COH901318_CX_CTRL_DDMA_LEGACY |
587 COH901318_CX_CTRL_PRDD_SOURCE,
588 .param.ctrl_lli_last = 0 |
589 COH901318_CX_CTRL_TC_ENABLE |
590 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
591 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
592 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
593 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
594 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
595 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
596 COH901318_CX_CTRL_TCP_ENABLE |
597 COH901318_CX_CTRL_TC_IRQ_ENABLE |
598 COH901318_CX_CTRL_HSP_ENABLE |
599 COH901318_CX_CTRL_HSS_DISABLE |
600 COH901318_CX_CTRL_DDMA_LEGACY |
601 COH901318_CX_CTRL_PRDD_SOURCE,
602 },
603 {
604 .number = U300_DMA_MSL_TX_5,
605 .name = "MSL TX 5",
606 .priority_high = 0,
607 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
608 },
609 {
610 .number = U300_DMA_MSL_TX_6,
611 .name = "MSL TX 6",
612 .priority_high = 0,
613 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
614 },
615 {
616 .number = U300_DMA_MSL_RX_0,
617 .name = "MSL RX 0",
618 .priority_high = 0,
619 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
620 },
621 {
622 .number = U300_DMA_MSL_RX_1,
623 .name = "MSL RX 1",
624 .priority_high = 0,
625 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
626 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]627 COH901318_CX_CFG_LCR_DISABLE |
628 COH901318_CX_CFG_TC_IRQ_ENABLE |
629 COH901318_CX_CFG_BE_IRQ_ENABLE,
630 .param.ctrl_lli_chained = 0 |
631 COH901318_CX_CTRL_TC_ENABLE |
632 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
633 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
634 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
635 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
636 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
637 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
638 COH901318_CX_CTRL_TCP_DISABLE |
639 COH901318_CX_CTRL_TC_IRQ_DISABLE |
640 COH901318_CX_CTRL_HSP_ENABLE |
641 COH901318_CX_CTRL_HSS_DISABLE |
642 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
643 COH901318_CX_CTRL_PRDD_DEST,
644 .param.ctrl_lli = 0,
645 .param.ctrl_lli_last = 0 |
646 COH901318_CX_CTRL_TC_ENABLE |
647 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
648 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
649 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
650 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
651 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
652 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
653 COH901318_CX_CTRL_TCP_DISABLE |
654 COH901318_CX_CTRL_TC_IRQ_ENABLE |
655 COH901318_CX_CTRL_HSP_ENABLE |
656 COH901318_CX_CTRL_HSS_DISABLE |
657 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
658 COH901318_CX_CTRL_PRDD_DEST,
659 },
660 {
661 .number = U300_DMA_MSL_RX_2,
662 .name = "MSL RX 2",
663 .priority_high = 0,
664 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
665 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]666 COH901318_CX_CFG_LCR_DISABLE |
667 COH901318_CX_CFG_TC_IRQ_ENABLE |
668 COH901318_CX_CFG_BE_IRQ_ENABLE,
669 .param.ctrl_lli_chained = 0 |
670 COH901318_CX_CTRL_TC_ENABLE |
671 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
672 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
673 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
674 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
675 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
676 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
677 COH901318_CX_CTRL_TCP_DISABLE |
678 COH901318_CX_CTRL_TC_IRQ_DISABLE |
679 COH901318_CX_CTRL_HSP_ENABLE |
680 COH901318_CX_CTRL_HSS_DISABLE |
681 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
682 COH901318_CX_CTRL_PRDD_DEST,
683 .param.ctrl_lli = 0 |
684 COH901318_CX_CTRL_TC_ENABLE |
685 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
686 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
687 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
688 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
689 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
690 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
691 COH901318_CX_CTRL_TCP_DISABLE |
692 COH901318_CX_CTRL_TC_IRQ_ENABLE |
693 COH901318_CX_CTRL_HSP_ENABLE |
694 COH901318_CX_CTRL_HSS_DISABLE |
695 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
696 COH901318_CX_CTRL_PRDD_DEST,
697 .param.ctrl_lli_last = 0 |
698 COH901318_CX_CTRL_TC_ENABLE |
699 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
700 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
701 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
702 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
703 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
704 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
705 COH901318_CX_CTRL_TCP_DISABLE |
706 COH901318_CX_CTRL_TC_IRQ_ENABLE |
707 COH901318_CX_CTRL_HSP_ENABLE |
708 COH901318_CX_CTRL_HSS_DISABLE |
709 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
710 COH901318_CX_CTRL_PRDD_DEST,
711 },
712 {
713 .number = U300_DMA_MSL_RX_3,
714 .name = "MSL RX 3",
715 .priority_high = 0,
716 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
717 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]718 COH901318_CX_CFG_LCR_DISABLE |
719 COH901318_CX_CFG_TC_IRQ_ENABLE |
720 COH901318_CX_CFG_BE_IRQ_ENABLE,
721 .param.ctrl_lli_chained = 0 |
722 COH901318_CX_CTRL_TC_ENABLE |
723 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
724 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
725 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
726 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
727 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
728 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
729 COH901318_CX_CTRL_TCP_DISABLE |
730 COH901318_CX_CTRL_TC_IRQ_DISABLE |
731 COH901318_CX_CTRL_HSP_ENABLE |
732 COH901318_CX_CTRL_HSS_DISABLE |
733 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
734 COH901318_CX_CTRL_PRDD_DEST,
735 .param.ctrl_lli = 0 |
736 COH901318_CX_CTRL_TC_ENABLE |
737 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
738 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
739 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
740 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
741 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
742 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
743 COH901318_CX_CTRL_TCP_DISABLE |
744 COH901318_CX_CTRL_TC_IRQ_ENABLE |
745 COH901318_CX_CTRL_HSP_ENABLE |
746 COH901318_CX_CTRL_HSS_DISABLE |
747 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
748 COH901318_CX_CTRL_PRDD_DEST,
749 .param.ctrl_lli_last = 0 |
750 COH901318_CX_CTRL_TC_ENABLE |
751 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
752 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
753 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
754 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
755 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
756 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
757 COH901318_CX_CTRL_TCP_DISABLE |
758 COH901318_CX_CTRL_TC_IRQ_ENABLE |
759 COH901318_CX_CTRL_HSP_ENABLE |
760 COH901318_CX_CTRL_HSS_DISABLE |
761 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
762 COH901318_CX_CTRL_PRDD_DEST,
763 },
764 {
765 .number = U300_DMA_MSL_RX_4,
766 .name = "MSL RX 4",
767 .priority_high = 0,
768 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
769 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]770 COH901318_CX_CFG_LCR_DISABLE |
771 COH901318_CX_CFG_TC_IRQ_ENABLE |
772 COH901318_CX_CFG_BE_IRQ_ENABLE,
773 .param.ctrl_lli_chained = 0 |
774 COH901318_CX_CTRL_TC_ENABLE |
775 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
776 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
777 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
778 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
779 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
780 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
781 COH901318_CX_CTRL_TCP_DISABLE |
782 COH901318_CX_CTRL_TC_IRQ_DISABLE |
783 COH901318_CX_CTRL_HSP_ENABLE |
784 COH901318_CX_CTRL_HSS_DISABLE |
785 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
786 COH901318_CX_CTRL_PRDD_DEST,
787 .param.ctrl_lli = 0 |
788 COH901318_CX_CTRL_TC_ENABLE |
789 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
790 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
791 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
792 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
793 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
794 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
795 COH901318_CX_CTRL_TCP_DISABLE |
796 COH901318_CX_CTRL_TC_IRQ_ENABLE |
797 COH901318_CX_CTRL_HSP_ENABLE |
798 COH901318_CX_CTRL_HSS_DISABLE |
799 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
800 COH901318_CX_CTRL_PRDD_DEST,
801 .param.ctrl_lli_last = 0 |
802 COH901318_CX_CTRL_TC_ENABLE |
803 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
804 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
805 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
806 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
807 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
808 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
809 COH901318_CX_CTRL_TCP_DISABLE |
810 COH901318_CX_CTRL_TC_IRQ_ENABLE |
811 COH901318_CX_CTRL_HSP_ENABLE |
812 COH901318_CX_CTRL_HSS_DISABLE |
813 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
814 COH901318_CX_CTRL_PRDD_DEST,
815 },
816 {
817 .number = U300_DMA_MSL_RX_5,
818 .name = "MSL RX 5",
819 .priority_high = 0,
820 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
821 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]822 COH901318_CX_CFG_LCR_DISABLE |
823 COH901318_CX_CFG_TC_IRQ_ENABLE |
824 COH901318_CX_CFG_BE_IRQ_ENABLE,
825 .param.ctrl_lli_chained = 0 |
826 COH901318_CX_CTRL_TC_ENABLE |
827 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
828 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
829 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
830 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
831 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
832 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
833 COH901318_CX_CTRL_TCP_DISABLE |
834 COH901318_CX_CTRL_TC_IRQ_DISABLE |
835 COH901318_CX_CTRL_HSP_ENABLE |
836 COH901318_CX_CTRL_HSS_DISABLE |
837 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
838 COH901318_CX_CTRL_PRDD_DEST,
839 .param.ctrl_lli = 0 |
840 COH901318_CX_CTRL_TC_ENABLE |
841 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
842 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
843 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
844 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
845 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
846 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
847 COH901318_CX_CTRL_TCP_DISABLE |
848 COH901318_CX_CTRL_TC_IRQ_ENABLE |
849 COH901318_CX_CTRL_HSP_ENABLE |
850 COH901318_CX_CTRL_HSS_DISABLE |
851 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
852 COH901318_CX_CTRL_PRDD_DEST,
853 .param.ctrl_lli_last = 0 |
854 COH901318_CX_CTRL_TC_ENABLE |
855 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
856 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
857 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
858 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
859 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
860 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
861 COH901318_CX_CTRL_TCP_DISABLE |
862 COH901318_CX_CTRL_TC_IRQ_ENABLE |
863 COH901318_CX_CTRL_HSP_ENABLE |
864 COH901318_CX_CTRL_HSS_DISABLE |
865 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
866 COH901318_CX_CTRL_PRDD_DEST,
867 },
868 {
869 .number = U300_DMA_MSL_RX_6,
870 .name = "MSL RX 6",
871 .priority_high = 0,
872 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
873 },
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]874 /*
875 * Don't set up device address, burst count or size of src
876 * or dst bus for this peripheral - handled by PrimeCell
877 * DMA extension.
878 */
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]879 {
880 .number = U300_DMA_MMCSD_RX_TX,
881 .name = "MMCSD RX TX",
882 .priority_high = 0,
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]883 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]884 COH901318_CX_CFG_LCR_DISABLE |
885 COH901318_CX_CFG_TC_IRQ_ENABLE |
886 COH901318_CX_CFG_BE_IRQ_ENABLE,
887 .param.ctrl_lli_chained = 0 |
888 COH901318_CX_CTRL_TC_ENABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]889 COH901318_CX_CTRL_MASTER_MODE_M1RW |
Linus Walleijd4095662010-02-14 19:41:35 +0100[diff] [blame]890 COH901318_CX_CTRL_TCP_ENABLE |
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]891 COH901318_CX_CTRL_TC_IRQ_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]892 COH901318_CX_CTRL_HSP_ENABLE |
893 COH901318_CX_CTRL_HSS_DISABLE |
894 COH901318_CX_CTRL_DDMA_LEGACY,
895 .param.ctrl_lli = 0 |
896 COH901318_CX_CTRL_TC_ENABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]897 COH901318_CX_CTRL_MASTER_MODE_M1RW |
898 COH901318_CX_CTRL_TCP_ENABLE |
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]899 COH901318_CX_CTRL_TC_IRQ_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]900 COH901318_CX_CTRL_HSP_ENABLE |
901 COH901318_CX_CTRL_HSS_DISABLE |
902 COH901318_CX_CTRL_DDMA_LEGACY,
903 .param.ctrl_lli_last = 0 |
904 COH901318_CX_CTRL_TC_ENABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]905 COH901318_CX_CTRL_MASTER_MODE_M1RW |
Linus Walleijd4095662010-02-14 19:41:35 +0100[diff] [blame]906 COH901318_CX_CTRL_TCP_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]907 COH901318_CX_CTRL_TC_IRQ_ENABLE |
908 COH901318_CX_CTRL_HSP_ENABLE |
909 COH901318_CX_CTRL_HSS_DISABLE |
910 COH901318_CX_CTRL_DDMA_LEGACY,
911
912 },
913 {
914 .number = U300_DMA_MSPRO_TX,
915 .name = "MSPRO TX",
916 .priority_high = 0,
917 },
918 {
919 .number = U300_DMA_MSPRO_RX,
920 .name = "MSPRO RX",
921 .priority_high = 0,
922 },
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]923 /*
924 * Don't set up device address, burst count or size of src
925 * or dst bus for this peripheral - handled by PrimeCell
926 * DMA extension.
927 */
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]928 {
929 .number = U300_DMA_UART0_TX,
930 .name = "UART0 TX",
931 .priority_high = 0,
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]932 .param.config = COH901318_CX_CFG_CH_DISABLE |
933 COH901318_CX_CFG_LCR_DISABLE |
934 COH901318_CX_CFG_TC_IRQ_ENABLE |
935 COH901318_CX_CFG_BE_IRQ_ENABLE,
936 .param.ctrl_lli_chained = 0 |
937 COH901318_CX_CTRL_TC_ENABLE |
938 COH901318_CX_CTRL_MASTER_MODE_M1RW |
939 COH901318_CX_CTRL_TCP_ENABLE |
940 COH901318_CX_CTRL_TC_IRQ_DISABLE |
941 COH901318_CX_CTRL_HSP_ENABLE |
942 COH901318_CX_CTRL_HSS_DISABLE |
943 COH901318_CX_CTRL_DDMA_LEGACY,
944 .param.ctrl_lli = 0 |
945 COH901318_CX_CTRL_TC_ENABLE |
946 COH901318_CX_CTRL_MASTER_MODE_M1RW |
947 COH901318_CX_CTRL_TCP_ENABLE |
948 COH901318_CX_CTRL_TC_IRQ_ENABLE |
949 COH901318_CX_CTRL_HSP_ENABLE |
950 COH901318_CX_CTRL_HSS_DISABLE |
951 COH901318_CX_CTRL_DDMA_LEGACY,
952 .param.ctrl_lli_last = 0 |
953 COH901318_CX_CTRL_TC_ENABLE |
954 COH901318_CX_CTRL_MASTER_MODE_M1RW |
955 COH901318_CX_CTRL_TCP_ENABLE |
956 COH901318_CX_CTRL_TC_IRQ_ENABLE |
957 COH901318_CX_CTRL_HSP_ENABLE |
958 COH901318_CX_CTRL_HSS_DISABLE |
959 COH901318_CX_CTRL_DDMA_LEGACY,
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]960 },
961 {
962 .number = U300_DMA_UART0_RX,
963 .name = "UART0 RX",
964 .priority_high = 0,
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]965 .param.config = COH901318_CX_CFG_CH_DISABLE |
966 COH901318_CX_CFG_LCR_DISABLE |
967 COH901318_CX_CFG_TC_IRQ_ENABLE |
968 COH901318_CX_CFG_BE_IRQ_ENABLE,
969 .param.ctrl_lli_chained = 0 |
970 COH901318_CX_CTRL_TC_ENABLE |
971 COH901318_CX_CTRL_MASTER_MODE_M1RW |
972 COH901318_CX_CTRL_TCP_ENABLE |
973 COH901318_CX_CTRL_TC_IRQ_DISABLE |
974 COH901318_CX_CTRL_HSP_ENABLE |
975 COH901318_CX_CTRL_HSS_DISABLE |
976 COH901318_CX_CTRL_DDMA_LEGACY,
977 .param.ctrl_lli = 0 |
978 COH901318_CX_CTRL_TC_ENABLE |
979 COH901318_CX_CTRL_MASTER_MODE_M1RW |
980 COH901318_CX_CTRL_TCP_ENABLE |
981 COH901318_CX_CTRL_TC_IRQ_ENABLE |
982 COH901318_CX_CTRL_HSP_ENABLE |
983 COH901318_CX_CTRL_HSS_DISABLE |
984 COH901318_CX_CTRL_DDMA_LEGACY,
985 .param.ctrl_lli_last = 0 |
986 COH901318_CX_CTRL_TC_ENABLE |
987 COH901318_CX_CTRL_MASTER_MODE_M1RW |
988 COH901318_CX_CTRL_TCP_ENABLE |
989 COH901318_CX_CTRL_TC_IRQ_ENABLE |
990 COH901318_CX_CTRL_HSP_ENABLE |
991 COH901318_CX_CTRL_HSS_DISABLE |
992 COH901318_CX_CTRL_DDMA_LEGACY,
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]993 },
994 {
995 .number = U300_DMA_APEX_TX,
996 .name = "APEX TX",
997 .priority_high = 0,
998 },
999 {
1000 .number = U300_DMA_APEX_RX,
1001 .name = "APEX RX",
1002 .priority_high = 0,
1003 },
1004 {
1005 .number = U300_DMA_PCM_I2S0_TX,
1006 .name = "PCM I2S0 TX",
1007 .priority_high = 1,
1008 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1009 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1010 COH901318_CX_CFG_LCR_DISABLE |
1011 COH901318_CX_CFG_TC_IRQ_ENABLE |
1012 COH901318_CX_CFG_BE_IRQ_ENABLE,
1013 .param.ctrl_lli_chained = 0 |
1014 COH901318_CX_CTRL_TC_ENABLE |
1015 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1016 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1017 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1018 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1019 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1020 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1021 COH901318_CX_CTRL_TCP_DISABLE |
1022 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1023 COH901318_CX_CTRL_HSP_ENABLE |
1024 COH901318_CX_CTRL_HSS_DISABLE |
1025 COH901318_CX_CTRL_DDMA_LEGACY |
1026 COH901318_CX_CTRL_PRDD_SOURCE,
1027 .param.ctrl_lli = 0 |
1028 COH901318_CX_CTRL_TC_ENABLE |
1029 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1030 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1031 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1032 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1033 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1034 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1035 COH901318_CX_CTRL_TCP_ENABLE |
1036 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1037 COH901318_CX_CTRL_HSP_ENABLE |
1038 COH901318_CX_CTRL_HSS_DISABLE |
1039 COH901318_CX_CTRL_DDMA_LEGACY |
1040 COH901318_CX_CTRL_PRDD_SOURCE,
1041 .param.ctrl_lli_last = 0 |
1042 COH901318_CX_CTRL_TC_ENABLE |
1043 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1044 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1045 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1046 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1047 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1048 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1049 COH901318_CX_CTRL_TCP_ENABLE |
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]1050 COH901318_CX_CTRL_TC_IRQ_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1051 COH901318_CX_CTRL_HSP_ENABLE |
1052 COH901318_CX_CTRL_HSS_DISABLE |
1053 COH901318_CX_CTRL_DDMA_LEGACY |
1054 COH901318_CX_CTRL_PRDD_SOURCE,
1055 },
1056 {
1057 .number = U300_DMA_PCM_I2S0_RX,
1058 .name = "PCM I2S0 RX",
1059 .priority_high = 1,
1060 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1061 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1062 COH901318_CX_CFG_LCR_DISABLE |
1063 COH901318_CX_CFG_TC_IRQ_ENABLE |
1064 COH901318_CX_CFG_BE_IRQ_ENABLE,
1065 .param.ctrl_lli_chained = 0 |
1066 COH901318_CX_CTRL_TC_ENABLE |
1067 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1068 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1069 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1070 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1071 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1072 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1073 COH901318_CX_CTRL_TCP_DISABLE |
1074 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1075 COH901318_CX_CTRL_HSP_ENABLE |
1076 COH901318_CX_CTRL_HSS_DISABLE |
1077 COH901318_CX_CTRL_DDMA_LEGACY |
1078 COH901318_CX_CTRL_PRDD_DEST,
1079 .param.ctrl_lli = 0 |
1080 COH901318_CX_CTRL_TC_ENABLE |
1081 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1082 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1083 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1084 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1085 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1086 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1087 COH901318_CX_CTRL_TCP_ENABLE |
1088 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1089 COH901318_CX_CTRL_HSP_ENABLE |
1090 COH901318_CX_CTRL_HSS_DISABLE |
1091 COH901318_CX_CTRL_DDMA_LEGACY |
1092 COH901318_CX_CTRL_PRDD_DEST,
1093 .param.ctrl_lli_last = 0 |
1094 COH901318_CX_CTRL_TC_ENABLE |
1095 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1096 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1097 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1098 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1099 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1100 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1101 COH901318_CX_CTRL_TCP_ENABLE |
1102 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1103 COH901318_CX_CTRL_HSP_ENABLE |
1104 COH901318_CX_CTRL_HSS_DISABLE |
1105 COH901318_CX_CTRL_DDMA_LEGACY |
1106 COH901318_CX_CTRL_PRDD_DEST,
1107 },
1108 {
1109 .number = U300_DMA_PCM_I2S1_TX,
1110 .name = "PCM I2S1 TX",
1111 .priority_high = 1,
1112 .dev_addr = U300_PCM_I2S1_BASE + 0x14,
1113 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1114 COH901318_CX_CFG_LCR_DISABLE |
1115 COH901318_CX_CFG_TC_IRQ_ENABLE |
1116 COH901318_CX_CFG_BE_IRQ_ENABLE,
1117 .param.ctrl_lli_chained = 0 |
1118 COH901318_CX_CTRL_TC_ENABLE |
1119 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1120 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1121 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1122 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1123 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1124 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1125 COH901318_CX_CTRL_TCP_DISABLE |
1126 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1127 COH901318_CX_CTRL_HSP_ENABLE |
1128 COH901318_CX_CTRL_HSS_DISABLE |
1129 COH901318_CX_CTRL_DDMA_LEGACY |
1130 COH901318_CX_CTRL_PRDD_SOURCE,
1131 .param.ctrl_lli = 0 |
1132 COH901318_CX_CTRL_TC_ENABLE |
1133 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1134 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1135 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1136 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1137 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1138 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1139 COH901318_CX_CTRL_TCP_ENABLE |
1140 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1141 COH901318_CX_CTRL_HSP_ENABLE |
1142 COH901318_CX_CTRL_HSS_DISABLE |
1143 COH901318_CX_CTRL_DDMA_LEGACY |
1144 COH901318_CX_CTRL_PRDD_SOURCE,
1145 .param.ctrl_lli_last = 0 |
1146 COH901318_CX_CTRL_TC_ENABLE |
1147 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1148 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1149 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1150 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1151 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1152 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1153 COH901318_CX_CTRL_TCP_ENABLE |
1154 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1155 COH901318_CX_CTRL_HSP_ENABLE |
1156 COH901318_CX_CTRL_HSS_DISABLE |
1157 COH901318_CX_CTRL_DDMA_LEGACY |
1158 COH901318_CX_CTRL_PRDD_SOURCE,
1159 },
1160 {
1161 .number = U300_DMA_PCM_I2S1_RX,
1162 .name = "PCM I2S1 RX",
1163 .priority_high = 1,
1164 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1165 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1166 COH901318_CX_CFG_LCR_DISABLE |
1167 COH901318_CX_CFG_TC_IRQ_ENABLE |
1168 COH901318_CX_CFG_BE_IRQ_ENABLE,
1169 .param.ctrl_lli_chained = 0 |
1170 COH901318_CX_CTRL_TC_ENABLE |
1171 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1172 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1173 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1174 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1175 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1176 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1177 COH901318_CX_CTRL_TCP_DISABLE |
1178 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1179 COH901318_CX_CTRL_HSP_ENABLE |
1180 COH901318_CX_CTRL_HSS_DISABLE |
1181 COH901318_CX_CTRL_DDMA_LEGACY |
1182 COH901318_CX_CTRL_PRDD_DEST,
1183 .param.ctrl_lli = 0 |
1184 COH901318_CX_CTRL_TC_ENABLE |
1185 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1186 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1187 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1188 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1189 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1190 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1191 COH901318_CX_CTRL_TCP_ENABLE |
1192 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1193 COH901318_CX_CTRL_HSP_ENABLE |
1194 COH901318_CX_CTRL_HSS_DISABLE |
1195 COH901318_CX_CTRL_DDMA_LEGACY |
1196 COH901318_CX_CTRL_PRDD_DEST,
1197 .param.ctrl_lli_last = 0 |
1198 COH901318_CX_CTRL_TC_ENABLE |
1199 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1200 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1201 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1202 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1203 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1204 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1205 COH901318_CX_CTRL_TCP_ENABLE |
1206 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1207 COH901318_CX_CTRL_HSP_ENABLE |
1208 COH901318_CX_CTRL_HSS_DISABLE |
1209 COH901318_CX_CTRL_DDMA_LEGACY |
1210 COH901318_CX_CTRL_PRDD_DEST,
1211 },
1212 {
1213 .number = U300_DMA_XGAM_CDI,
1214 .name = "XGAM CDI",
1215 .priority_high = 0,
1216 },
1217 {
1218 .number = U300_DMA_XGAM_PDI,
1219 .name = "XGAM PDI",
1220 .priority_high = 0,
1221 },
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]1222 /*
1223 * Don't set up device address, burst count or size of src
1224 * or dst bus for this peripheral - handled by PrimeCell
1225 * DMA extension.
1226 */
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1227 {
1228 .number = U300_DMA_SPI_TX,
1229 .name = "SPI TX",
1230 .priority_high = 0,
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]1231 .param.config = COH901318_CX_CFG_CH_DISABLE |
1232 COH901318_CX_CFG_LCR_DISABLE |
1233 COH901318_CX_CFG_TC_IRQ_ENABLE |
1234 COH901318_CX_CFG_BE_IRQ_ENABLE,
1235 .param.ctrl_lli_chained = 0 |
1236 COH901318_CX_CTRL_TC_ENABLE |
1237 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1238 COH901318_CX_CTRL_TCP_DISABLE |
1239 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1240 COH901318_CX_CTRL_HSP_ENABLE |
1241 COH901318_CX_CTRL_HSS_DISABLE |
1242 COH901318_CX_CTRL_DDMA_LEGACY,
1243 .param.ctrl_lli = 0 |
1244 COH901318_CX_CTRL_TC_ENABLE |
1245 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1246 COH901318_CX_CTRL_TCP_DISABLE |
1247 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1248 COH901318_CX_CTRL_HSP_ENABLE |
1249 COH901318_CX_CTRL_HSS_DISABLE |
1250 COH901318_CX_CTRL_DDMA_LEGACY,
1251 .param.ctrl_lli_last = 0 |
1252 COH901318_CX_CTRL_TC_ENABLE |
1253 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1254 COH901318_CX_CTRL_TCP_DISABLE |
1255 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1256 COH901318_CX_CTRL_HSP_ENABLE |
1257 COH901318_CX_CTRL_HSS_DISABLE |
1258 COH901318_CX_CTRL_DDMA_LEGACY,
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1259 },
1260 {
1261 .number = U300_DMA_SPI_RX,
1262 .name = "SPI RX",
1263 .priority_high = 0,
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]1264 .param.config = COH901318_CX_CFG_CH_DISABLE |
1265 COH901318_CX_CFG_LCR_DISABLE |
1266 COH901318_CX_CFG_TC_IRQ_ENABLE |
1267 COH901318_CX_CFG_BE_IRQ_ENABLE,
1268 .param.ctrl_lli_chained = 0 |
1269 COH901318_CX_CTRL_TC_ENABLE |
1270 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1271 COH901318_CX_CTRL_TCP_DISABLE |
1272 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1273 COH901318_CX_CTRL_HSP_ENABLE |
1274 COH901318_CX_CTRL_HSS_DISABLE |
1275 COH901318_CX_CTRL_DDMA_LEGACY,
1276 .param.ctrl_lli = 0 |
1277 COH901318_CX_CTRL_TC_ENABLE |
1278 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1279 COH901318_CX_CTRL_TCP_DISABLE |
1280 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1281 COH901318_CX_CTRL_HSP_ENABLE |
1282 COH901318_CX_CTRL_HSS_DISABLE |
1283 COH901318_CX_CTRL_DDMA_LEGACY,
1284 .param.ctrl_lli_last = 0 |
1285 COH901318_CX_CTRL_TC_ENABLE |
1286 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1287 COH901318_CX_CTRL_TCP_DISABLE |
1288 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1289 COH901318_CX_CTRL_HSP_ENABLE |
1290 COH901318_CX_CTRL_HSS_DISABLE |
1291 COH901318_CX_CTRL_DDMA_LEGACY,
1292
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1293 },
1294 {
1295 .number = U300_DMA_GENERAL_PURPOSE_0,
1296 .name = "GENERAL 00",
1297 .priority_high = 0,
1298
1299 .param.config = flags_memcpy_config,
1300 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1301 .param.ctrl_lli = flags_memcpy_lli,
1302 .param.ctrl_lli_last = flags_memcpy_lli_last,
1303 },
1304 {
1305 .number = U300_DMA_GENERAL_PURPOSE_1,
1306 .name = "GENERAL 01",
1307 .priority_high = 0,
1308
1309 .param.config = flags_memcpy_config,
1310 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1311 .param.ctrl_lli = flags_memcpy_lli,
1312 .param.ctrl_lli_last = flags_memcpy_lli_last,
1313 },
1314 {
1315 .number = U300_DMA_GENERAL_PURPOSE_2,
1316 .name = "GENERAL 02",
1317 .priority_high = 0,
1318
1319 .param.config = flags_memcpy_config,
1320 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1321 .param.ctrl_lli = flags_memcpy_lli,
1322 .param.ctrl_lli_last = flags_memcpy_lli_last,
1323 },
1324 {
1325 .number = U300_DMA_GENERAL_PURPOSE_3,
1326 .name = "GENERAL 03",
1327 .priority_high = 0,
1328
1329 .param.config = flags_memcpy_config,
1330 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1331 .param.ctrl_lli = flags_memcpy_lli,
1332 .param.ctrl_lli_last = flags_memcpy_lli_last,
1333 },
1334 {
1335 .number = U300_DMA_GENERAL_PURPOSE_4,
1336 .name = "GENERAL 04",
1337 .priority_high = 0,
1338
1339 .param.config = flags_memcpy_config,
1340 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1341 .param.ctrl_lli = flags_memcpy_lli,
1342 .param.ctrl_lli_last = flags_memcpy_lli_last,
1343 },
1344 {
1345 .number = U300_DMA_GENERAL_PURPOSE_5,
1346 .name = "GENERAL 05",
1347 .priority_high = 0,
1348
1349 .param.config = flags_memcpy_config,
1350 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1351 .param.ctrl_lli = flags_memcpy_lli,
1352 .param.ctrl_lli_last = flags_memcpy_lli_last,
1353 },
1354 {
1355 .number = U300_DMA_GENERAL_PURPOSE_6,
1356 .name = "GENERAL 06",
1357 .priority_high = 0,
1358
1359 .param.config = flags_memcpy_config,
1360 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1361 .param.ctrl_lli = flags_memcpy_lli,
1362 .param.ctrl_lli_last = flags_memcpy_lli_last,
1363 },
1364 {
1365 .number = U300_DMA_GENERAL_PURPOSE_7,
1366 .name = "GENERAL 07",
1367 .priority_high = 0,
1368
1369 .param.config = flags_memcpy_config,
1370 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1371 .param.ctrl_lli = flags_memcpy_lli,
1372 .param.ctrl_lli_last = flags_memcpy_lli_last,
1373 },
1374 {
1375 .number = U300_DMA_GENERAL_PURPOSE_8,
1376 .name = "GENERAL 08",
1377 .priority_high = 0,
1378
1379 .param.config = flags_memcpy_config,
1380 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1381 .param.ctrl_lli = flags_memcpy_lli,
1382 .param.ctrl_lli_last = flags_memcpy_lli_last,
1383 },
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1384 {
1385 .number = U300_DMA_UART1_TX,
1386 .name = "UART1 TX",
1387 .priority_high = 0,
1388 },
1389 {
1390 .number = U300_DMA_UART1_RX,
1391 .name = "UART1 RX",
1392 .priority_high = 0,
1393 }
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1394};
1395
1396
1397static struct coh901318_platform coh901318_platform = {
1398 .chans_slave = dma_slave_channels,
1399 .chans_memcpy = dma_memcpy_channels,
1400 .access_memory_state = coh901318_access_memory_state,
1401 .chan_conf = chan_config,
1402 .max_channels = U300_DMA_CHANNELS,
1403};
1404
Linus Walleij128a06d2012-02-21 14:31:45 +0100[diff] [blame]1405static struct resource pinctrl_resources[] = {
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1406 {
1407 .start = U300_SYSCON_BASE,
1408 .end = U300_SYSCON_BASE + SZ_4K - 1,
1409 .flags = IORESOURCE_MEM,
1410 },
1411};
1412
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1413static struct platform_device wdog_device = {
Linus Walleij633e81a2010-01-25 07:18:16 +0100[diff] [blame]1414 .name = "coh901327_wdog",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1415 .id = -1,
1416 .num_resources = ARRAY_SIZE(wdog_resources),
1417 .resource = wdog_resources,
1418};
1419
1420static struct platform_device i2c0_device = {
Linus Walleij6be2a0c2009-08-13 21:42:01 +0100[diff] [blame]1421 .name = "stu300",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1422 .id = 0,
1423 .num_resources = ARRAY_SIZE(i2c0_resources),
1424 .resource = i2c0_resources,
1425};
1426
1427static struct platform_device i2c1_device = {
Linus Walleij6be2a0c2009-08-13 21:42:01 +0100[diff] [blame]1428 .name = "stu300",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1429 .id = 1,
1430 .num_resources = ARRAY_SIZE(i2c1_resources),
1431 .resource = i2c1_resources,
1432};
1433
Linus Walleij128a06d2012-02-21 14:31:45 +0100[diff] [blame]1434static struct platform_device pinctrl_device = {
1435 .name = "pinctrl-u300",
1436 .id = -1,
1437 .num_resources = ARRAY_SIZE(pinctrl_resources),
1438 .resource = pinctrl_resources,
1439};
1440
Linus Walleijcc890cd2011-09-08 09:04:51 +0100[diff] [blame]1441/*
1442 * The different variants have a few different versions of the
1443 * GPIO block, with different number of ports.
1444 */
1445static struct u300_gpio_platform u300_gpio_plat = {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100[diff] [blame]1446 .ports = 7,
Linus Walleijcc890cd2011-09-08 09:04:51 +0100[diff] [blame]1447 .gpio_base = 0,
1448 .gpio_irq_base = IRQ_U300_GPIO_BASE,
Linus Walleij128a06d2012-02-21 14:31:45 +0100[diff] [blame]1449 .pinctrl_device = &pinctrl_device,
Linus Walleijcc890cd2011-09-08 09:04:51 +0100[diff] [blame]1450};
1451
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1452static struct platform_device gpio_device = {
1453 .name = "u300-gpio",
1454 .id = -1,
1455 .num_resources = ARRAY_SIZE(gpio_resources),
1456 .resource = gpio_resources,
Linus Walleijcc890cd2011-09-08 09:04:51 +0100[diff] [blame]1457 .dev = {
1458 .platform_data = &u300_gpio_plat,
1459 },
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1460};
1461
1462static struct platform_device keypad_device = {
1463 .name = "keypad",
1464 .id = -1,
1465 .num_resources = ARRAY_SIZE(keypad_resources),
1466 .resource = keypad_resources,
1467};
1468
1469static struct platform_device rtc_device = {
Linus Walleij378ce742009-11-14 01:03:24 +0100[diff] [blame]1470 .name = "rtc-coh901331",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1471 .id = -1,
1472 .num_resources = ARRAY_SIZE(rtc_resources),
1473 .resource = rtc_resources,
1474};
1475
Linus Walleij93ac5a52010-09-13 00:35:37 +0200[diff] [blame]1476static struct mtd_partition u300_partitions[] = {
1477 {
1478 .name = "bootrecords",
1479 .offset = 0,
1480 .size = SZ_128K,
1481 },
1482 {
1483 .name = "free",
1484 .offset = SZ_128K,
1485 .size = 8064 * SZ_1K,
1486 },
1487 {
1488 .name = "platform",
1489 .offset = 8192 * SZ_1K,
1490 .size = 253952 * SZ_1K,
1491 },
1492};
1493
1494static struct fsmc_nand_platform_data nand_platform_data = {
1495 .partitions = u300_partitions,
1496 .nr_partitions = ARRAY_SIZE(u300_partitions),
1497 .options = NAND_SKIP_BBTSCAN,
1498 .width = FSMC_NAND_BW8,
Shiraz Hashim02bfc4e2012-03-07 17:00:52 +0530[diff] [blame]1499 .ale_off = PLAT_NAND_ALE,
1500 .cle_off = PLAT_NAND_CLE,
Linus Walleij93ac5a52010-09-13 00:35:37 +0200[diff] [blame]1501};
1502
1503static struct platform_device nand_device = {
1504 .name = "fsmc-nand",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1505 .id = -1,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1506 .resource = fsmc_resources,
Linus Walleij93ac5a52010-09-13 00:35:37 +0200[diff] [blame]1507 .num_resources = ARRAY_SIZE(fsmc_resources),
1508 .dev = {
1509 .platform_data = &nand_platform_data,
1510 },
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1511};
1512
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1513static struct platform_device dma_device = {
1514 .name = "coh901318",
1515 .id = -1,
1516 .resource = dma_resource,
1517 .num_resources = ARRAY_SIZE(dma_resource),
1518 .dev = {
1519 .platform_data = &coh901318_platform,
1520 .coherent_dma_mask = ~0,
1521 },
1522};
1523
Linus Walleij51dddfe2012-01-20 17:53:15 +0100[diff] [blame]1524static unsigned long pin_pullup_conf[] = {
1525 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
1526};
1527
1528static unsigned long pin_highz_conf[] = {
1529 PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
1530};
1531
1532/* Pin control settings */
Linus Walleije93bcee2012-02-09 07:23:28 +0100[diff] [blame]1533static struct pinctrl_map __initdata u300_pinmux_map[] = {
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1534 /* anonymous maps for chip power and EMIFs */
Stephen Warren1e2082b2012-03-02 13:05:48 -0700[diff] [blame]1535 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
1536 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
1537 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1538 /* per-device maps for MMC/SD, SPI and UART */
Stephen Warren1e2082b2012-03-02 13:05:48 -0700[diff] [blame]1539 PIN_MAP_MUX_GROUP_DEFAULT("mmci", "pinctrl-u300", NULL, "mmc0"),
1540 PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
1541 PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
Linus Walleij51dddfe2012-01-20 17:53:15 +0100[diff] [blame]1542 /* This pin is used for clock return rather than GPIO */
1543 PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
1544 pin_pullup_conf),
1545 /* This pin is used for card detect */
1546 PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
1547 pin_highz_conf),
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1548};
1549
1550struct u300_mux_hog {
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1551 struct device *dev;
Linus Walleije93bcee2012-02-09 07:23:28 +0100[diff] [blame]1552 struct pinctrl *p;
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1553};
1554
1555static struct u300_mux_hog u300_mux_hogs[] = {
1556 {
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1557 .dev = &uart0_device.dev,
1558 },
1559 {
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1560 .dev = &pl022_device.dev,
1561 },
1562 {
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1563 .dev = &mmcsd_device.dev,
1564 },
1565};
1566
Linus Walleije93bcee2012-02-09 07:23:28 +0100[diff] [blame]1567static int __init u300_pinctrl_fetch(void)
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1568{
1569 int i;
1570
1571 for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
Linus Walleije93bcee2012-02-09 07:23:28 +0100[diff] [blame]1572 struct pinctrl *p;
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1573
Stephen Warren6e5e9592012-03-02 13:05:47 -0700[diff] [blame]1574 p = pinctrl_get_select_default(u300_mux_hogs[i].dev);
Linus Walleije93bcee2012-02-09 07:23:28 +0100[diff] [blame]1575 if (IS_ERR(p)) {
Stephen Warren6e5e9592012-03-02 13:05:47 -0700[diff] [blame]1576 pr_err("u300: could not get pinmux hog for dev %s\n",
1577 dev_name(u300_mux_hogs[i].dev));
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1578 continue;
1579 }
Linus Walleije93bcee2012-02-09 07:23:28 +0100[diff] [blame]1580 u300_mux_hogs[i].p = p;
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1581 }
1582 return 0;
1583}
Linus Walleije93bcee2012-02-09 07:23:28 +0100[diff] [blame]1584subsys_initcall(u300_pinctrl_fetch);
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1585
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1586/*
1587 * Notice that AMBA devices are initialized before platform devices.
1588 *
1589 */
1590static struct platform_device *platform_devs[] __initdata = {
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1591 &dma_device,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1592 &i2c0_device,
1593 &i2c1_device,
1594 &keypad_device,
1595 &rtc_device,
1596 &gpio_device,
Linus Walleij93ac5a52010-09-13 00:35:37 +0200[diff] [blame]1597 &nand_device,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1598 &wdog_device,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1599};
1600
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1601/*
1602 * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1603 * together so some interrupts are connected to the first one and some
1604 * to the second one.
1605 */
Linus Walleij234323b2012-08-13 11:35:55 +0200[diff] [blame^]1606static void __init u300_init_irq(void)
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1607{
1608 u32 mask[2] = {0, 0};
Linus Walleijb7276b22010-08-05 07:58:58 +0100[diff] [blame]1609 struct clk *clk;
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1610 int i;
1611
Linus Walleij379aae52010-08-05 07:58:13 +0100[diff] [blame]1612 /* initialize clocking early, we want to clock the INTCON */
Linus Walleij50667d62012-06-19 23:44:25 +0200[diff] [blame]1613 u300_clk_init(U300_SYSCON_VBASE);
1614
1615 /* Bootstrap EMIF and SEMI clocks */
1616 clk = clk_get_sys("pl172", NULL);
1617 BUG_ON(IS_ERR(clk));
1618 clk_prepare_enable(clk);
1619 clk = clk_get_sys("semi", NULL);
1620 BUG_ON(IS_ERR(clk));
1621 clk_prepare_enable(clk);
Linus Walleij379aae52010-08-05 07:58:13 +0100[diff] [blame]1622
Linus Walleijb7276b22010-08-05 07:58:58 +0100[diff] [blame]1623 /* Clock the interrupt controller */
1624 clk = clk_get_sys("intcon", NULL);
1625 BUG_ON(IS_ERR(clk));
Linus Walleij50667d62012-06-19 23:44:25 +0200[diff] [blame]1626 clk_prepare_enable(clk);
Linus Walleijb7276b22010-08-05 07:58:58 +0100[diff] [blame]1627
Linus Walleijcc890cd2011-09-08 09:04:51 +0100[diff] [blame]1628 for (i = 0; i < U300_VIC_IRQS_END; i++)
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1629 set_bit(i, (unsigned long *) &mask[0]);
Linus Walleij13445002012-04-18 15:29:58 +0200[diff] [blame]1630 vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
1631 mask[0], mask[0]);
1632 vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
1633 mask[1], mask[1]);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1634}
1635
1636
1637/*
1638 * U300 platforms peripheral handling
1639 */
1640struct db_chip {
1641 u16 chipid;
1642 const char *name;
1643};
1644
1645/*
1646 * This is a list of the Digital Baseband chips used in the U300 platform.
1647 */
1648static struct db_chip db_chips[] __initdata = {
1649 {
1650 .chipid = 0xb800,
1651 .name = "DB3000",
1652 },
1653 {
1654 .chipid = 0xc000,
1655 .name = "DB3100",
1656 },
1657 {
1658 .chipid = 0xc800,
1659 .name = "DB3150",
1660 },
1661 {
1662 .chipid = 0xd800,
1663 .name = "DB3200",
1664 },
1665 {
1666 .chipid = 0xe000,
1667 .name = "DB3250",
1668 },
1669 {
1670 .chipid = 0xe800,
1671 .name = "DB3210",
1672 },
1673 {
1674 .chipid = 0xf000,
1675 .name = "DB3350 P1x",
1676 },
1677 {
1678 .chipid = 0xf100,
1679 .name = "DB3350 P2x",
1680 },
1681 {
1682 .chipid = 0x0000, /* List terminator */
1683 .name = NULL,
1684 }
1685};
1686
Linus Walleija2bb9f42009-08-13 21:57:22 +0100[diff] [blame]1687static void __init u300_init_check_chip(void)
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1688{
1689
1690 u16 val;
1691 struct db_chip *chip;
1692 const char *chipname;
1693 const char unknown[] = "UNKNOWN";
1694
1695 /* Read out and print chip ID */
1696 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1697 /* This is in funky bigendian order... */
1698 val = (val & 0xFFU) << 8 | (val >> 8);
1699 chip = db_chips;
1700 chipname = unknown;
1701
1702 for ( ; chip->chipid; chip++) {
1703 if (chip->chipid == (val & 0xFF00U)) {
1704 chipname = chip->name;
1705 break;
1706 }
1707 }
1708 printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1709 "(chip ID 0x%04x)\n", chipname, val);
1710
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1711 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]1712 printk(KERN_ERR "Platform configured for BS335 " \
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1713 " with DB3350 but %s detected, expect problems!",
1714 chipname);
1715 }
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1716}
1717
1718/*
1719 * Some devices and their resources require reserved physical memory from
1720 * the end of the available RAM. This function traverses the list of devices
Daniel Mack3ad2f3f2010-02-03 08:01:28 +0800[diff] [blame]1721 * and assigns actual addresses to these.
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1722 */
1723static void __init u300_assign_physmem(void)
1724{
1725 unsigned long curr_start = __pa(high_memory);
1726 int i, j;
1727
1728 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1729 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1730 struct resource *const res =
1731 &platform_devs[i]->resource[j];
1732
1733 if (IORESOURCE_MEM == res->flags &&
1734 0 == res->start) {
1735 res->start = curr_start;
1736 res->end += curr_start;
Joe Perches28f65c112011-06-09 09:13:32 -0700[diff] [blame]1737 curr_start += resource_size(res);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1738
1739 printk(KERN_INFO "core.c: Mapping RAM " \
1740 "%#x-%#x to device %s:%s\n",
1741 res->start, res->end,
1742 platform_devs[i]->name, res->name);
1743 }
1744 }
1745 }
1746}
1747
Linus Walleij234323b2012-08-13 11:35:55 +0200[diff] [blame^]1748static void __init u300_init_machine(void)
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1749{
1750 int i;
1751 u16 val;
1752
1753 /* Check what platform we run and print some status information */
1754 u300_init_check_chip();
1755
Linus Walleijc7c8c782009-08-14 10:59:05 +0100[diff] [blame]1756 /* Initialize SPI device with some board specifics */
1757 u300_spi_init(&pl022_device);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1758
1759 /* Register the AMBA devices in the AMBA bus abstraction layer */
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1760 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1761 struct amba_device *d = amba_devs[i];
1762 amba_device_register(d, &iomem_resource);
1763 }
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1764
1765 u300_assign_physmem();
1766
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1767 /* Initialize pinmuxing */
Linus Walleije93bcee2012-02-09 07:23:28 +0100[diff] [blame]1768 pinctrl_register_mappings(u300_pinmux_map,
1769 ARRAY_SIZE(u300_pinmux_map));
Linus Walleij98da3522011-05-02 20:54:38 +0200[diff] [blame]1770
Linus Walleij6be2a0c2009-08-13 21:42:01 +0100[diff] [blame]1771 /* Register subdevices on the I2C buses */
1772 u300_i2c_register_board_devices();
1773
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1774 /* Register the platform devices */
1775 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1776
Linus Walleijec8f1252010-08-13 11:31:59 +0200[diff] [blame]1777 /* Register subdevices on the SPI bus */
1778 u300_spi_register_board_devices();
1779
Linus Walleijc43ed562011-08-09 21:30:01 +0200[diff] [blame]1780 /* Enable SEMI self refresh */
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1781 val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1782 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1783 writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1784}
1785
Russell King7e3974b2011-11-05 15:51:25 +0000[diff] [blame]1786/* Forward declare this function from the watchdog */
1787void coh901327_watchdog_reset(void);
1788
Linus Walleij234323b2012-08-13 11:35:55 +0200[diff] [blame^]1789static void u300_restart(char mode, const char *cmd)
Russell King7e3974b2011-11-05 15:51:25 +0000[diff] [blame]1790{
1791 switch (mode) {
1792 case 's':
1793 case 'h':
Russell King7e3974b2011-11-05 15:51:25 +0000[diff] [blame]1794#ifdef CONFIG_COH901327_WATCHDOG
1795 coh901327_watchdog_reset();
1796#endif
1797 break;
1798 default:
1799 /* Do nothing */
1800 break;
1801 }
1802 /* Wait for system do die/reset. */
1803 while (1);
1804}
Linus Walleij234323b2012-08-13 11:35:55 +0200[diff] [blame^]1805
1806MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
1807 /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
1808 .atag_offset = 0x100,
1809 .map_io = u300_map_io,
1810 .init_irq = u300_init_irq,
1811 .handle_irq = vic_handle_irq,
1812 .timer = &u300_timer,
1813 .init_machine = u300_init_machine,
1814 .restart = u300_restart,
1815MACHINE_END