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gerrit-public.fairphone.software / kernel / msm-5.4 / 24196d5c597272b1e5c57903f2e3c7996e607117 / . / arch / arm / boot / dts / imx28-cfa10049.dts
blob: b222614ac9e0d3ac2dac19b330f23bed7db02380 [file] [log] [blame]
Maxime Riparddb84c032012-08-31 16:00:41 +0200[diff] [blame]1/*
2 * Copyright 2012 Free Electrons
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/*
13 * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
14 * need to include the CFA-10036 DTS.
15 */
16/include/ "imx28-cfa10036.dts"
17
18/ {
19 model = "Crystalfontz CFA-10049 Board";
20 compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
21
22 apb@80000000 {
Maxime Ripard223d1f92012-09-04 10:44:03 +0200[diff] [blame]23 apbh@80000000 {
24 pinctrl@80018000 {
Maxime Ripard24196d52012-11-03 16:59:08 +0100[diff] [blame^]25 pinctrl-names = "default", "default";
26 pinctrl-1 = <&hog_pins_cfa10049>;
27
28 hog_pins_cfa10049: hog-10049@0 {
29 reg = <0>;
30 fsl,pinmux-ids = <
31 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
32 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
33 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
34 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
35 >;
36 fsl,drive-strength = <0>;
37 fsl,voltage = <1>;
38 fsl,pull-up = <0>;
39 };
40
Maxime Ripard223d1f92012-09-04 10:44:03 +0200[diff] [blame]41 spi3_pins_cfa10049: spi3-cfa10049@0 {
42 reg = <0>;
43 fsl,pinmux-ids = <
44 0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */
45 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
Maxime Ripard13b45692012-09-10 22:35:41 +0200[diff] [blame]46 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
47 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
Maxime Riparddb7a8942012-10-31 11:30:10 +0100[diff] [blame]48 0x01b2 /* MX28_PAD_GPMI_CLE__SSP3_D5 */
Maxime Ripard223d1f92012-09-04 10:44:03 +0200[diff] [blame]49 >;
50 fsl,drive-strength = <1>;
51 fsl,voltage = <1>;
52 fsl,pull-up = <1>;
53 };
54 };
55
56 ssp3: ssp@80016000 {
57 compatible = "fsl,imx28-spi";
58 pinctrl-names = "default";
59 pinctrl-0 = <&spi3_pins_cfa10049>;
60 status = "okay";
Maxime Ripard13b45692012-09-10 22:35:41 +0200[diff] [blame]61
62 gpio5: gpio5@0 {
63 compatible = "fairchild,74hc595";
64 gpio-controller;
65 #gpio-cells = <2>;
66 reg = <0>;
67 registers-number = <2>;
68 spi-max-frequency = <100000>;
69 };
70
71 gpio6: gpio6@1 {
72 compatible = "fairchild,74hc595";
73 gpio-controller;
74 #gpio-cells = <2>;
75 reg = <1>;
76 registers-number = <4>;
77 spi-max-frequency = <100000>;
78 };
79
Maxime Riparddb7a8942012-10-31 11:30:10 +0100[diff] [blame]80 dac0: dh2228@2 {
81 compatible = "rohm,dh2228fv";
82 reg = <2>;
83 spi-max-frequency = <100000>;
84 };
Maxime Ripard223d1f92012-09-04 10:44:03 +0200[diff] [blame]85 };
86 };
87
Maxime Riparddb84c032012-08-31 16:00:41 +0200[diff] [blame]88 apbx@80040000 {
89 i2c1: i2c@8005a000 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&i2c1_pins_a>;
92 status = "okay";
93 };
Maxime Ripard186e3d92012-09-03 16:15:25 +0200[diff] [blame]94
95 usbphy1: usbphy@8007e000 {
96 status = "okay";
97 };
98 };
99 };
100
101 ahb@80080000 {
102 usb1: usb@80090000 {
103 vbus-supply = <&reg_usb1_vbus>;
104 pinctrl-0 = <&usbphy1_pins_a>;
105 pinctrl-names = "default";
106 status = "okay";
107 };
108 };
109
110 regulators {
111 compatible = "simple-bus";
112
113 reg_usb1_vbus: usb1_vbus {
114 compatible = "regulator-fixed";
115 regulator-name = "usb1_vbus";
116 regulator-min-microvolt = <5000000>;
117 regulator-max-microvolt = <5000000>;
118 gpio = <&gpio0 7 1>;
Maxime Riparddb84c032012-08-31 16:00:41 +0200[diff] [blame]119 };
120 };
Maxime Ripard8eec4b32012-10-07 10:36:28 +0800[diff] [blame]121
122 ahb@80080000 {
123 mac0: ethernet@800f0000 {
124 phy-mode = "rmii";
125 pinctrl-names = "default";
126 pinctrl-0 = <&mac0_pins_a>;
127 phy-reset-gpios = <&gpio2 21 0>;
128 phy-reset-duration = <100>;
129 status = "okay";
130 };
131 };
Maxime Riparddb84c032012-08-31 16:00:41 +0200[diff] [blame]132};