blob: cb0a3fe3271879f750dd9bd24fc3f21ea39789bd [file] [log] [blame]
Shawn Guo2954ff32012-05-04 21:33:42 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Lothar Waßmannbc3875f2013-09-19 08:59:48 +020012#include "imx23-pinfunc.h"
Shawn Guo2954ff32012-05-04 21:33:42 +080013
14/ {
Fabio Estevam7f107882016-11-12 13:30:35 -020015 #address-cells = <1>;
16 #size-cells = <1>;
17
Shawn Guo2954ff32012-05-04 21:33:42 +080018 interrupt-parent = <&icoll>;
Fabio Estevama971c552017-01-23 14:54:10 -020019 /*
20 * The decompressor and also some bootloaders rely on a
21 * pre-existing /chosen node to be available to insert the
22 * command line and merge other ATAGS info.
23 * Also for U-Boot there must be a pre-existing /memory node.
24 */
25 chosen {};
Marco Franchi7f08e6a2018-01-24 11:22:13 -020026 memory { device_type = "memory"; };
Shawn Guo2954ff32012-05-04 21:33:42 +080027
Shawn Guoce4c6f92012-05-04 14:32:35 +080028 aliases {
29 gpio0 = &gpio0;
30 gpio1 = &gpio1;
31 gpio2 = &gpio2;
Shawn Guoa4508392012-06-28 11:45:00 +080032 serial0 = &auart0;
33 serial1 = &auart1;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -030034 spi0 = &ssp0;
35 spi1 = &ssp1;
Peter Chen1f35cc62013-12-20 15:52:05 +080036 usbphy0 = &usbphy0;
Shawn Guoce4c6f92012-05-04 14:32:35 +080037 };
38
Shawn Guo2954ff32012-05-04 21:33:42 +080039 cpus {
Fabio Estevamd447dd82016-11-16 13:15:38 -020040 #address-cells = <1>;
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +010041 #size-cells = <0>;
42
Fabio Estevamd447dd82016-11-16 13:15:38 -020043 cpu@0 {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +010044 compatible = "arm,arm926ej-s";
45 device_type = "cpu";
Fabio Estevamd447dd82016-11-16 13:15:38 -020046 reg = <0>;
Shawn Guo2954ff32012-05-04 21:33:42 +080047 };
48 };
49
50 apb@80000000 {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 reg = <0x80000000 0x80000>;
55 ranges;
56
57 apbh@80000000 {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 reg = <0x80000000 0x40000>;
62 ranges;
63
64 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +080065 compatible = "fsl,imx23-icoll", "fsl,icoll";
Shawn Guo2954ff32012-05-04 21:33:42 +080066 interrupt-controller;
67 #interrupt-cells = <1>;
68 reg = <0x80000000 0x2000>;
69 };
70
Shawn Guof30fb032013-02-25 21:56:56 +080071 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +080072 compatible = "fsl,imx23-dma-apbh";
Fabio Estevam640bf062012-07-30 21:29:18 -030073 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +080074 interrupts = <0 14 20 0
75 13 13 13 13>;
76 interrupt-names = "empty", "ssp0", "ssp1", "empty",
77 "gpmi0", "gpmi1", "gpmi2", "gpmi3";
78 #dma-cells = <1>;
79 dma-channels = <8>;
Shawn Guo53f94432012-08-22 21:36:30 +080080 clocks = <&clks 15>;
Shawn Guo2954ff32012-05-04 21:33:42 +080081 };
82
83 ecc@80008000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030084 reg = <0x80008000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +080085 status = "disabled";
86 };
87
Marek Vasuta217c462012-06-09 01:21:55 +020088 gpmi-nand@8000c000 {
Huang Shijieb9f25f82012-07-03 12:58:13 +080089 compatible = "fsl,imx23-gpmi-nand";
90 #address-cells = <1>;
91 #size-cells = <1>;
Fabio Estevam640bf062012-07-30 21:29:18 -030092 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijieb9f25f82012-07-03 12:58:13 +080093 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +080094 interrupts = <56>;
95 interrupt-names = "bch";
Shawn Guo53f94432012-08-22 21:36:30 +080096 clocks = <&clks 34>;
Huang Shijieb6442552012-10-10 18:27:09 +080097 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +080098 dmas = <&dma_apbh 4>;
99 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800100 status = "disabled";
101 };
102
103 ssp0: ssp@80010000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300104 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800105 interrupts = <15>;
Shawn Guo53f94432012-08-22 21:36:30 +0800106 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +0800107 dmas = <&dma_apbh 1>;
108 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800109 status = "disabled";
110 };
111
112 etm@80014000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300113 reg = <0x80014000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800114 status = "disabled";
115 };
116
117 pinctrl@80018000 {
118 #address-cells = <1>;
119 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800120 compatible = "fsl,imx23-pinctrl", "simple-bus";
Fabio Estevam640bf062012-07-30 21:29:18 -0300121 reg = <0x80018000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800122
Shawn Guoce4c6f92012-05-04 14:32:35 +0800123 gpio0: gpio@0 {
124 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000125 reg = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800126 interrupts = <16>;
127 gpio-controller;
128 #gpio-cells = <2>;
129 interrupt-controller;
130 #interrupt-cells = <2>;
131 };
132
133 gpio1: gpio@1 {
134 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000135 reg = <1>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800136 interrupts = <17>;
137 gpio-controller;
138 #gpio-cells = <2>;
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 };
142
143 gpio2: gpio@2 {
144 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000145 reg = <2>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800146 interrupts = <18>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
151 };
152
Shawn Guo2954ff32012-05-04 21:33:42 +0800153 duart_pins_a: duart@0 {
154 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800155 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200156 MX23_PAD_PWM0__DUART_RX
157 MX23_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800158 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800159 fsl,drive-strength = <MXS_DRIVE_4mA>;
160 fsl,voltage = <MXS_VOLTAGE_HIGH>;
161 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800162 };
Shawn Guobe1ce302012-05-06 16:29:36 +0800163
Shawn Guoa4508392012-06-28 11:45:00 +0800164 auart0_pins_a: auart0@0 {
165 reg = <0>;
166 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200167 MX23_PAD_AUART1_RX__AUART1_RX
168 MX23_PAD_AUART1_TX__AUART1_TX
169 MX23_PAD_AUART1_CTS__AUART1_CTS
170 MX23_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoa4508392012-06-28 11:45:00 +0800171 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800172 fsl,drive-strength = <MXS_DRIVE_4mA>;
173 fsl,voltage = <MXS_VOLTAGE_HIGH>;
174 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa4508392012-06-28 11:45:00 +0800175 };
176
Fabio Estevam98916a22012-07-30 16:33:44 -0300177 auart0_2pins_a: auart0-2pins@0 {
178 reg = <0>;
179 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200180 MX23_PAD_I2C_SCL__AUART1_TX
181 MX23_PAD_I2C_SDA__AUART1_RX
Fabio Estevam98916a22012-07-30 16:33:44 -0300182 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800183 fsl,drive-strength = <MXS_DRIVE_4mA>;
184 fsl,voltage = <MXS_VOLTAGE_HIGH>;
185 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam98916a22012-07-30 16:33:44 -0300186 };
187
Marek Vasutd33c7312016-06-09 21:43:11 +0200188 auart1_2pins_a: auart1-2pins@0 {
189 reg = <0>;
190 fsl,pinmux-ids = <
191 MX23_PAD_GPMI_D14__AUART2_RX
192 MX23_PAD_GPMI_D15__AUART2_TX
193 >;
194 fsl,drive-strength = <MXS_DRIVE_4mA>;
195 fsl,voltage = <MXS_VOLTAGE_HIGH>;
196 fsl,pull-up = <MXS_PULL_DISABLE>;
197 };
198
Huang Shijieb9f25f82012-07-03 12:58:13 +0800199 gpmi_pins_a: gpmi-nand@0 {
200 reg = <0>;
201 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200202 MX23_PAD_GPMI_D00__GPMI_D00
203 MX23_PAD_GPMI_D01__GPMI_D01
204 MX23_PAD_GPMI_D02__GPMI_D02
205 MX23_PAD_GPMI_D03__GPMI_D03
206 MX23_PAD_GPMI_D04__GPMI_D04
207 MX23_PAD_GPMI_D05__GPMI_D05
208 MX23_PAD_GPMI_D06__GPMI_D06
209 MX23_PAD_GPMI_D07__GPMI_D07
210 MX23_PAD_GPMI_CLE__GPMI_CLE
211 MX23_PAD_GPMI_ALE__GPMI_ALE
212 MX23_PAD_GPMI_RDY0__GPMI_RDY0
213 MX23_PAD_GPMI_RDY1__GPMI_RDY1
214 MX23_PAD_GPMI_WPN__GPMI_WPN
215 MX23_PAD_GPMI_WRN__GPMI_WRN
216 MX23_PAD_GPMI_RDN__GPMI_RDN
217 MX23_PAD_GPMI_CE1N__GPMI_CE1N
218 MX23_PAD_GPMI_CE0N__GPMI_CE0N
Huang Shijieb9f25f82012-07-03 12:58:13 +0800219 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800220 fsl,drive-strength = <MXS_DRIVE_4mA>;
221 fsl,voltage = <MXS_VOLTAGE_HIGH>;
222 fsl,pull-up = <MXS_PULL_DISABLE>;
Huang Shijieb9f25f82012-07-03 12:58:13 +0800223 };
224
Fabio Estevam74aeda32017-12-27 12:04:34 -0200225 gpmi_pins_fixup: gpmi-pins-fixup@0 {
226 reg = <0>;
Huang Shijieb9f25f82012-07-03 12:58:13 +0800227 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200228 MX23_PAD_GPMI_WPN__GPMI_WPN
229 MX23_PAD_GPMI_WRN__GPMI_WRN
230 MX23_PAD_GPMI_RDN__GPMI_RDN
Huang Shijieb9f25f82012-07-03 12:58:13 +0800231 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800232 fsl,drive-strength = <MXS_DRIVE_12mA>;
Huang Shijieb9f25f82012-07-03 12:58:13 +0800233 };
234
Shawn Guo72beaba2012-06-28 11:44:59 +0800235 mmc0_4bit_pins_a: mmc0-4bit@0 {
236 reg = <0>;
237 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200238 MX23_PAD_SSP1_DATA0__SSP1_DATA0
239 MX23_PAD_SSP1_DATA1__SSP1_DATA1
240 MX23_PAD_SSP1_DATA2__SSP1_DATA2
241 MX23_PAD_SSP1_DATA3__SSP1_DATA3
242 MX23_PAD_SSP1_CMD__SSP1_CMD
243 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guo72beaba2012-06-28 11:44:59 +0800244 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800245 fsl,drive-strength = <MXS_DRIVE_8mA>;
246 fsl,voltage = <MXS_VOLTAGE_HIGH>;
247 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo72beaba2012-06-28 11:44:59 +0800248 };
249
Shawn Guobe1ce302012-05-06 16:29:36 +0800250 mmc0_8bit_pins_a: mmc0-8bit@0 {
251 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800252 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200253 MX23_PAD_SSP1_DATA0__SSP1_DATA0
254 MX23_PAD_SSP1_DATA1__SSP1_DATA1
255 MX23_PAD_SSP1_DATA2__SSP1_DATA2
256 MX23_PAD_SSP1_DATA3__SSP1_DATA3
257 MX23_PAD_GPMI_D08__SSP1_DATA4
258 MX23_PAD_GPMI_D09__SSP1_DATA5
259 MX23_PAD_GPMI_D10__SSP1_DATA6
260 MX23_PAD_GPMI_D11__SSP1_DATA7
261 MX23_PAD_SSP1_CMD__SSP1_CMD
262 MX23_PAD_SSP1_DETECT__SSP1_DETECT
263 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800264 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800265 fsl,drive-strength = <MXS_DRIVE_8mA>;
266 fsl,voltage = <MXS_VOLTAGE_HIGH>;
267 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800268 };
269
Fabio Estevam74aeda32017-12-27 12:04:34 -0200270 mmc0_pins_fixup: mmc0-pins-fixup@0 {
271 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800272 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200273 MX23_PAD_SSP1_DETECT__SSP1_DETECT
274 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800275 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800276 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800277 };
Shawn Guo52f71762012-06-28 11:45:06 +0800278
Marek Vasut1ebcb162016-06-09 21:43:10 +0200279 mmc1_4bit_pins_a: mmc1-4bit@0 {
280 reg = <0>;
281 fsl,pinmux-ids = <
282 MX23_PAD_GPMI_D00__SSP2_DATA0
283 MX23_PAD_GPMI_D01__SSP2_DATA1
284 MX23_PAD_GPMI_D02__SSP2_DATA2
285 MX23_PAD_GPMI_D03__SSP2_DATA3
286 MX23_PAD_GPMI_RDY1__SSP2_CMD
287 MX23_PAD_GPMI_WRN__SSP2_SCK
288 >;
289 fsl,drive-strength = <MXS_DRIVE_8mA>;
290 fsl,voltage = <MXS_VOLTAGE_HIGH>;
291 fsl,pull-up = <MXS_PULL_ENABLE>;
292 };
293
294 mmc1_8bit_pins_a: mmc1-8bit@0 {
295 reg = <0>;
296 fsl,pinmux-ids = <
297 MX23_PAD_GPMI_D00__SSP2_DATA0
298 MX23_PAD_GPMI_D01__SSP2_DATA1
299 MX23_PAD_GPMI_D02__SSP2_DATA2
300 MX23_PAD_GPMI_D03__SSP2_DATA3
301 MX23_PAD_GPMI_D04__SSP2_DATA4
302 MX23_PAD_GPMI_D05__SSP2_DATA5
303 MX23_PAD_GPMI_D06__SSP2_DATA6
304 MX23_PAD_GPMI_D07__SSP2_DATA7
305 MX23_PAD_GPMI_RDY1__SSP2_CMD
306 MX23_PAD_GPMI_WRN__SSP2_SCK
307 >;
308 fsl,drive-strength = <MXS_DRIVE_8mA>;
309 fsl,voltage = <MXS_VOLTAGE_HIGH>;
310 fsl,pull-up = <MXS_PULL_ENABLE>;
311 };
312
Shawn Guo52f71762012-06-28 11:45:06 +0800313 pwm2_pins_a: pwm2@0 {
314 reg = <0>;
315 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200316 MX23_PAD_PWM2__PWM2
Shawn Guo52f71762012-06-28 11:45:06 +0800317 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800318 fsl,drive-strength = <MXS_DRIVE_4mA>;
319 fsl,voltage = <MXS_VOLTAGE_HIGH>;
320 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo52f71762012-06-28 11:45:06 +0800321 };
Shawn Guoa915ee422012-06-28 11:45:07 +0800322
323 lcdif_24bit_pins_a: lcdif-24bit@0 {
324 reg = <0>;
325 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200326 MX23_PAD_LCD_D00__LCD_D00
327 MX23_PAD_LCD_D01__LCD_D01
328 MX23_PAD_LCD_D02__LCD_D02
329 MX23_PAD_LCD_D03__LCD_D03
330 MX23_PAD_LCD_D04__LCD_D04
331 MX23_PAD_LCD_D05__LCD_D05
332 MX23_PAD_LCD_D06__LCD_D06
333 MX23_PAD_LCD_D07__LCD_D07
334 MX23_PAD_LCD_D08__LCD_D08
335 MX23_PAD_LCD_D09__LCD_D09
336 MX23_PAD_LCD_D10__LCD_D10
337 MX23_PAD_LCD_D11__LCD_D11
338 MX23_PAD_LCD_D12__LCD_D12
339 MX23_PAD_LCD_D13__LCD_D13
340 MX23_PAD_LCD_D14__LCD_D14
341 MX23_PAD_LCD_D15__LCD_D15
342 MX23_PAD_LCD_D16__LCD_D16
343 MX23_PAD_LCD_D17__LCD_D17
344 MX23_PAD_GPMI_D08__LCD_D18
345 MX23_PAD_GPMI_D09__LCD_D19
346 MX23_PAD_GPMI_D10__LCD_D20
347 MX23_PAD_GPMI_D11__LCD_D21
348 MX23_PAD_GPMI_D12__LCD_D22
349 MX23_PAD_GPMI_D13__LCD_D23
350 MX23_PAD_LCD_DOTCK__LCD_DOTCK
351 MX23_PAD_LCD_ENABLE__LCD_ENABLE
352 MX23_PAD_LCD_HSYNC__LCD_HSYNC
353 MX23_PAD_LCD_VSYNC__LCD_VSYNC
Shawn Guoa915ee422012-06-28 11:45:07 +0800354 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800355 fsl,drive-strength = <MXS_DRIVE_4mA>;
356 fsl,voltage = <MXS_VOLTAGE_HIGH>;
357 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa915ee422012-06-28 11:45:07 +0800358 };
Fadil Berishaa0487862012-11-17 16:52:32 -0500359
360 spi2_pins_a: spi2@0 {
361 reg = <0>;
362 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200363 MX23_PAD_GPMI_WRN__SSP2_SCK
364 MX23_PAD_GPMI_RDY1__SSP2_CMD
365 MX23_PAD_GPMI_D00__SSP2_DATA0
366 MX23_PAD_GPMI_D03__SSP2_DATA3
Fadil Berishaa0487862012-11-17 16:52:32 -0500367 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800368 fsl,drive-strength = <MXS_DRIVE_8mA>;
369 fsl,voltage = <MXS_VOLTAGE_HIGH>;
370 fsl,pull-up = <MXS_PULL_ENABLE>;
Fadil Berishaa0487862012-11-17 16:52:32 -0500371 };
Harald Geyer71a34d82015-04-17 14:43:24 +0000372
373 i2c_pins_a: i2c@0 {
374 reg = <0>;
375 fsl,pinmux-ids = <
376 MX23_PAD_I2C_SCL__I2C_SCL
377 MX23_PAD_I2C_SDA__I2C_SDA
378 >;
379 fsl,drive-strength = <MXS_DRIVE_8mA>;
380 fsl,voltage = <MXS_VOLTAGE_HIGH>;
381 fsl,pull-up = <MXS_PULL_ENABLE>;
382 };
383
384 i2c_pins_b: i2c@1 {
385 reg = <1>;
386 fsl,pinmux-ids = <
387 MX23_PAD_LCD_ENABLE__I2C_SCL
388 MX23_PAD_LCD_HSYNC__I2C_SDA
389 >;
390 fsl,drive-strength = <MXS_DRIVE_8mA>;
391 fsl,voltage = <MXS_VOLTAGE_HIGH>;
392 fsl,pull-up = <MXS_PULL_ENABLE>;
393 };
394
395 i2c_pins_c: i2c@2 {
396 reg = <2>;
397 fsl,pinmux-ids = <
398 MX23_PAD_SSP1_DATA1__I2C_SCL
399 MX23_PAD_SSP1_DATA2__I2C_SDA
400 >;
401 fsl,drive-strength = <MXS_DRIVE_8mA>;
402 fsl,voltage = <MXS_VOLTAGE_HIGH>;
403 fsl,pull-up = <MXS_PULL_ENABLE>;
404 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800405 };
406
407 digctl@8001c000 {
Shawn Guo38d65902013-03-26 21:11:02 +0800408 compatible = "fsl,imx23-digctl";
Shawn Guo2954ff32012-05-04 21:33:42 +0800409 reg = <0x8001c000 2000>;
410 status = "disabled";
411 };
412
413 emi@80020000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300414 reg = <0x80020000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800415 status = "disabled";
416 };
417
Shawn Guof30fb032013-02-25 21:56:56 +0800418 dma_apbx: dma-apbx@80024000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800419 compatible = "fsl,imx23-dma-apbx";
Fabio Estevam640bf062012-07-30 21:29:18 -0300420 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800421 interrupts = <7 5 9 26
422 19 0 25 23
423 60 58 9 0
424 0 0 0 0>;
425 interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
426 "saif0", "empty", "auart0-rx", "auart0-tx",
427 "auart1-rx", "auart1-tx", "saif1", "empty",
428 "empty", "empty", "empty", "empty";
429 #dma-cells = <1>;
430 dma-channels = <16>;
Shawn Guo53f94432012-08-22 21:36:30 +0800431 clocks = <&clks 16>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800432 };
433
434 dcp@80028000 {
Marek Vasut7d56a282013-12-10 20:26:22 +0100435 compatible = "fsl,imx23-dcp";
Fabio Estevam640bf062012-07-30 21:29:18 -0300436 reg = <0x80028000 0x2000>;
Marek Vasut7d56a282013-12-10 20:26:22 +0100437 interrupts = <53 54>;
438 status = "okay";
Shawn Guo2954ff32012-05-04 21:33:42 +0800439 };
440
441 pxp@8002a000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300442 reg = <0x8002a000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800443 status = "disabled";
444 };
445
446 ocotp@8002c000 {
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000447 compatible = "fsl,imx23-ocotp", "fsl,ocotp";
448 #address-cells = <1>;
449 #size-cells = <1>;
Fabio Estevam640bf062012-07-30 21:29:18 -0300450 reg = <0x8002c000 0x2000>;
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000451 clocks = <&clks 15>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800452 };
453
454 axi-ahb@8002e000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300455 reg = <0x8002e000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800456 status = "disabled";
457 };
458
459 lcdif@80030000 {
Shawn Guoa915ee422012-06-28 11:45:07 +0800460 compatible = "fsl,imx23-lcdif";
Shawn Guo2954ff32012-05-04 21:33:42 +0800461 reg = <0x80030000 2000>;
Shawn Guoa915ee422012-06-28 11:45:07 +0800462 interrupts = <46 45>;
Shawn Guo53f94432012-08-22 21:36:30 +0800463 clocks = <&clks 38>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800464 status = "disabled";
465 };
466
467 ssp1: ssp@80034000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300468 reg = <0x80034000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800469 interrupts = <2>;
Shawn Guo53f94432012-08-22 21:36:30 +0800470 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +0800471 dmas = <&dma_apbh 2>;
472 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800473 status = "disabled";
474 };
475
476 tvenc@80038000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300477 reg = <0x80038000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800478 status = "disabled";
479 };
Jagan Teki46311702016-10-26 15:31:01 +0530480 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800481
482 apbx@80040000 {
483 compatible = "simple-bus";
484 #address-cells = <1>;
485 #size-cells = <1>;
486 reg = <0x80040000 0x40000>;
487 ranges;
488
Shawn Guo53f94432012-08-22 21:36:30 +0800489 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800490 compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
Fabio Estevam640bf062012-07-30 21:29:18 -0300491 reg = <0x80040000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800492 #clock-cells = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800493 };
494
495 saif0: saif@80042000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300496 reg = <0x80042000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800497 dmas = <&dma_apbx 4>;
498 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800499 status = "disabled";
500 };
501
502 power@80044000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300503 reg = <0x80044000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800504 status = "disabled";
505 };
506
507 saif1: saif@80046000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300508 reg = <0x80046000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800509 dmas = <&dma_apbx 10>;
510 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800511 status = "disabled";
512 };
513
514 audio-out@80048000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300515 reg = <0x80048000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800516 dmas = <&dma_apbx 1>;
517 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800518 status = "disabled";
519 };
520
521 audio-in@8004c000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300522 reg = <0x8004c000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800523 dmas = <&dma_apbx 0>;
524 dma-names = "rx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800525 status = "disabled";
526 };
527
Alexandre Bellonibd798f92013-12-18 19:50:56 +0100528 lradc: lradc@80050000 {
Marek Vasut1f451882013-01-21 20:05:00 +0000529 compatible = "fsl,imx23-lradc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300530 reg = <0x80050000 0x2000>;
Marek Vasut1f451882013-01-21 20:05:00 +0000531 interrupts = <36 37 38 39 40 41 42 43 44>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800532 status = "disabled";
Juergen Beisert18da7552013-09-23 15:36:00 +0100533 clocks = <&clks 26>;
Stefan Wahrene8e94ed2015-06-02 22:03:28 +0000534 #io-channel-cells = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800535 };
536
537 spdif@80054000 {
538 reg = <0x80054000 2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800539 dmas = <&dma_apbx 2>;
540 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800541 status = "disabled";
542 };
543
Harald Geyer71a34d82015-04-17 14:43:24 +0000544 i2c: i2c@80058000 {
545 #address-cells = <1>;
546 #size-cells = <0>;
547 compatible = "fsl,imx23-i2c";
Fabio Estevam640bf062012-07-30 21:29:18 -0300548 reg = <0x80058000 0x2000>;
Harald Geyer71a34d82015-04-17 14:43:24 +0000549 interrupts = <27>;
550 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800551 dmas = <&dma_apbx 3>;
552 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800553 status = "disabled";
554 };
555
556 rtc@8005c000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800557 compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300558 reg = <0x8005c000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800559 interrupts = <22>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800560 };
561
Shawn Guo52f71762012-06-28 11:45:06 +0800562 pwm: pwm@80064000 {
563 compatible = "fsl,imx23-pwm";
Fabio Estevam640bf062012-07-30 21:29:18 -0300564 reg = <0x80064000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800565 clocks = <&clks 30>;
Shawn Guo52f71762012-06-28 11:45:06 +0800566 #pwm-cells = <2>;
567 fsl,pwm-number = <5>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800568 status = "disabled";
569 };
570
571 timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800572 compatible = "fsl,imx23-timrot", "fsl,timrot";
Fabio Estevam640bf062012-07-30 21:29:18 -0300573 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800574 interrupts = <28 29 30 31>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800575 clocks = <&clks 28>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800576 };
577
578 auart0: serial@8006c000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800579 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800580 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800581 interrupts = <24>;
Shawn Guo53f94432012-08-22 21:36:30 +0800582 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800583 dmas = <&dma_apbx 6>, <&dma_apbx 7>;
584 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800585 status = "disabled";
586 };
587
588 auart1: serial@8006e000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800589 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800590 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800591 interrupts = <59>;
Shawn Guo53f94432012-08-22 21:36:30 +0800592 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800593 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
594 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800595 status = "disabled";
596 };
597
598 duart: serial@80070000 {
599 compatible = "arm,pl011", "arm,primecell";
600 reg = <0x80070000 0x2000>;
601 interrupts = <0>;
Shawn Guo53f94432012-08-22 21:36:30 +0800602 clocks = <&clks 32>, <&clks 16>;
603 clock-names = "uart", "apb_pclk";
Shawn Guo2954ff32012-05-04 21:33:42 +0800604 status = "disabled";
605 };
606
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300607 usbphy0: usbphy@8007c000 {
608 compatible = "fsl,imx23-usbphy";
Shawn Guo2954ff32012-05-04 21:33:42 +0800609 reg = <0x8007c000 0x2000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300610 clocks = <&clks 41>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800611 status = "disabled";
612 };
613 };
614 };
615
616 ahb@80080000 {
617 compatible = "simple-bus";
618 #address-cells = <1>;
619 #size-cells = <1>;
620 reg = <0x80080000 0x80000>;
621 ranges;
622
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300623 usb0: usb@80080000 {
624 compatible = "fsl,imx23-usb", "fsl,imx27-usb";
Fabio Estevam640bf062012-07-30 21:29:18 -0300625 reg = <0x80080000 0x40000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300626 interrupts = <11>;
627 fsl,usbphy = <&usbphy0>;
628 clocks = <&clks 40>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800629 status = "disabled";
630 };
631 };
Alexandre Bellonibd798f92013-12-18 19:50:56 +0100632
Sanchayan Maity0b452cc2016-02-16 10:30:54 +0530633 iio-hwmon {
Alexandre Bellonibd798f92013-12-18 19:50:56 +0100634 compatible = "iio-hwmon";
635 io-channels = <&lradc 8>;
636 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800637};