blob: ff96e592ec3cea5eae8fa2068a4485a9a21f7b0e [file] [log] [blame]
Shawn Guo2954ff32012-05-04 21:33:42 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Lothar Waßmannbc3875f2013-09-19 08:59:48 +020012#include "skeleton.dtsi"
13#include "imx23-pinfunc.h"
Shawn Guo2954ff32012-05-04 21:33:42 +080014
15/ {
16 interrupt-parent = <&icoll>;
17
Shawn Guoce4c6f92012-05-04 14:32:35 +080018 aliases {
19 gpio0 = &gpio0;
20 gpio1 = &gpio1;
21 gpio2 = &gpio2;
Shawn Guoa4508392012-06-28 11:45:00 +080022 serial0 = &auart0;
23 serial1 = &auart1;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -030024 spi0 = &ssp0;
25 spi1 = &ssp1;
Shawn Guoce4c6f92012-05-04 14:32:35 +080026 };
27
Shawn Guo2954ff32012-05-04 21:33:42 +080028 cpus {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +010029 #address-cells = <0>;
30 #size-cells = <0>;
31
32 cpu {
33 compatible = "arm,arm926ej-s";
34 device_type = "cpu";
Shawn Guo2954ff32012-05-04 21:33:42 +080035 };
36 };
37
38 apb@80000000 {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 reg = <0x80000000 0x80000>;
43 ranges;
44
45 apbh@80000000 {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 reg = <0x80000000 0x40000>;
50 ranges;
51
52 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +080053 compatible = "fsl,imx23-icoll", "fsl,icoll";
Shawn Guo2954ff32012-05-04 21:33:42 +080054 interrupt-controller;
55 #interrupt-cells = <1>;
56 reg = <0x80000000 0x2000>;
57 };
58
Shawn Guof30fb032013-02-25 21:56:56 +080059 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +080060 compatible = "fsl,imx23-dma-apbh";
Fabio Estevam640bf062012-07-30 21:29:18 -030061 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +080062 interrupts = <0 14 20 0
63 13 13 13 13>;
64 interrupt-names = "empty", "ssp0", "ssp1", "empty",
65 "gpmi0", "gpmi1", "gpmi2", "gpmi3";
66 #dma-cells = <1>;
67 dma-channels = <8>;
Shawn Guo53f94432012-08-22 21:36:30 +080068 clocks = <&clks 15>;
Shawn Guo2954ff32012-05-04 21:33:42 +080069 };
70
71 ecc@80008000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030072 reg = <0x80008000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +080073 status = "disabled";
74 };
75
Marek Vasuta217c462012-06-09 01:21:55 +020076 gpmi-nand@8000c000 {
Huang Shijieb9f25f82012-07-03 12:58:13 +080077 compatible = "fsl,imx23-gpmi-nand";
78 #address-cells = <1>;
79 #size-cells = <1>;
Fabio Estevam640bf062012-07-30 21:29:18 -030080 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijieb9f25f82012-07-03 12:58:13 +080081 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +080082 interrupts = <56>;
83 interrupt-names = "bch";
Shawn Guo53f94432012-08-22 21:36:30 +080084 clocks = <&clks 34>;
Huang Shijieb6442552012-10-10 18:27:09 +080085 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +080086 dmas = <&dma_apbh 4>;
87 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +080088 status = "disabled";
89 };
90
91 ssp0: ssp@80010000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030092 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +080093 interrupts = <15>;
Shawn Guo53f94432012-08-22 21:36:30 +080094 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +080095 dmas = <&dma_apbh 1>;
96 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +080097 status = "disabled";
98 };
99
100 etm@80014000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300101 reg = <0x80014000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800102 status = "disabled";
103 };
104
105 pinctrl@80018000 {
106 #address-cells = <1>;
107 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800108 compatible = "fsl,imx23-pinctrl", "simple-bus";
Fabio Estevam640bf062012-07-30 21:29:18 -0300109 reg = <0x80018000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800110
Shawn Guoce4c6f92012-05-04 14:32:35 +0800111 gpio0: gpio@0 {
112 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
113 interrupts = <16>;
114 gpio-controller;
115 #gpio-cells = <2>;
116 interrupt-controller;
117 #interrupt-cells = <2>;
118 };
119
120 gpio1: gpio@1 {
121 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
122 interrupts = <17>;
123 gpio-controller;
124 #gpio-cells = <2>;
125 interrupt-controller;
126 #interrupt-cells = <2>;
127 };
128
129 gpio2: gpio@2 {
130 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
131 interrupts = <18>;
132 gpio-controller;
133 #gpio-cells = <2>;
134 interrupt-controller;
135 #interrupt-cells = <2>;
136 };
137
Shawn Guo2954ff32012-05-04 21:33:42 +0800138 duart_pins_a: duart@0 {
139 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800140 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200141 MX23_PAD_PWM0__DUART_RX
142 MX23_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800143 >;
Shawn Guo2954ff32012-05-04 21:33:42 +0800144 fsl,drive-strength = <0>;
145 fsl,voltage = <1>;
146 fsl,pull-up = <0>;
147 };
Shawn Guobe1ce302012-05-06 16:29:36 +0800148
Shawn Guoa4508392012-06-28 11:45:00 +0800149 auart0_pins_a: auart0@0 {
150 reg = <0>;
151 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200152 MX23_PAD_AUART1_RX__AUART1_RX
153 MX23_PAD_AUART1_TX__AUART1_TX
154 MX23_PAD_AUART1_CTS__AUART1_CTS
155 MX23_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoa4508392012-06-28 11:45:00 +0800156 >;
157 fsl,drive-strength = <0>;
158 fsl,voltage = <1>;
159 fsl,pull-up = <0>;
160 };
161
Fabio Estevam98916a22012-07-30 16:33:44 -0300162 auart0_2pins_a: auart0-2pins@0 {
163 reg = <0>;
164 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200165 MX23_PAD_I2C_SCL__AUART1_TX
166 MX23_PAD_I2C_SDA__AUART1_RX
Fabio Estevam98916a22012-07-30 16:33:44 -0300167 >;
168 fsl,drive-strength = <0>;
169 fsl,voltage = <1>;
170 fsl,pull-up = <0>;
171 };
172
Huang Shijieb9f25f82012-07-03 12:58:13 +0800173 gpmi_pins_a: gpmi-nand@0 {
174 reg = <0>;
175 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200176 MX23_PAD_GPMI_D00__GPMI_D00
177 MX23_PAD_GPMI_D01__GPMI_D01
178 MX23_PAD_GPMI_D02__GPMI_D02
179 MX23_PAD_GPMI_D03__GPMI_D03
180 MX23_PAD_GPMI_D04__GPMI_D04
181 MX23_PAD_GPMI_D05__GPMI_D05
182 MX23_PAD_GPMI_D06__GPMI_D06
183 MX23_PAD_GPMI_D07__GPMI_D07
184 MX23_PAD_GPMI_CLE__GPMI_CLE
185 MX23_PAD_GPMI_ALE__GPMI_ALE
186 MX23_PAD_GPMI_RDY0__GPMI_RDY0
187 MX23_PAD_GPMI_RDY1__GPMI_RDY1
188 MX23_PAD_GPMI_WPN__GPMI_WPN
189 MX23_PAD_GPMI_WRN__GPMI_WRN
190 MX23_PAD_GPMI_RDN__GPMI_RDN
191 MX23_PAD_GPMI_CE1N__GPMI_CE1N
192 MX23_PAD_GPMI_CE0N__GPMI_CE0N
Huang Shijieb9f25f82012-07-03 12:58:13 +0800193 >;
194 fsl,drive-strength = <0>;
195 fsl,voltage = <1>;
196 fsl,pull-up = <0>;
197 };
198
199 gpmi_pins_fixup: gpmi-pins-fixup {
200 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200201 MX23_PAD_GPMI_WPN__GPMI_WPN
202 MX23_PAD_GPMI_WRN__GPMI_WRN
203 MX23_PAD_GPMI_RDN__GPMI_RDN
Huang Shijieb9f25f82012-07-03 12:58:13 +0800204 >;
205 fsl,drive-strength = <2>;
206 };
207
Shawn Guo72beaba2012-06-28 11:44:59 +0800208 mmc0_4bit_pins_a: mmc0-4bit@0 {
209 reg = <0>;
210 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200211 MX23_PAD_SSP1_DATA0__SSP1_DATA0
212 MX23_PAD_SSP1_DATA1__SSP1_DATA1
213 MX23_PAD_SSP1_DATA2__SSP1_DATA2
214 MX23_PAD_SSP1_DATA3__SSP1_DATA3
215 MX23_PAD_SSP1_CMD__SSP1_CMD
216 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guo72beaba2012-06-28 11:44:59 +0800217 >;
218 fsl,drive-strength = <1>;
219 fsl,voltage = <1>;
220 fsl,pull-up = <1>;
221 };
222
Shawn Guobe1ce302012-05-06 16:29:36 +0800223 mmc0_8bit_pins_a: mmc0-8bit@0 {
224 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800225 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200226 MX23_PAD_SSP1_DATA0__SSP1_DATA0
227 MX23_PAD_SSP1_DATA1__SSP1_DATA1
228 MX23_PAD_SSP1_DATA2__SSP1_DATA2
229 MX23_PAD_SSP1_DATA3__SSP1_DATA3
230 MX23_PAD_GPMI_D08__SSP1_DATA4
231 MX23_PAD_GPMI_D09__SSP1_DATA5
232 MX23_PAD_GPMI_D10__SSP1_DATA6
233 MX23_PAD_GPMI_D11__SSP1_DATA7
234 MX23_PAD_SSP1_CMD__SSP1_CMD
235 MX23_PAD_SSP1_DETECT__SSP1_DETECT
236 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800237 >;
Shawn Guobe1ce302012-05-06 16:29:36 +0800238 fsl,drive-strength = <1>;
239 fsl,voltage = <1>;
240 fsl,pull-up = <1>;
241 };
242
243 mmc0_pins_fixup: mmc0-pins-fixup {
Shawn Guof14da762012-06-28 11:44:57 +0800244 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200245 MX23_PAD_SSP1_DETECT__SSP1_DETECT
246 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800247 >;
Shawn Guobe1ce302012-05-06 16:29:36 +0800248 fsl,pull-up = <0>;
249 };
Shawn Guo52f71762012-06-28 11:45:06 +0800250
251 pwm2_pins_a: pwm2@0 {
252 reg = <0>;
253 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200254 MX23_PAD_PWM2__PWM2
Shawn Guo52f71762012-06-28 11:45:06 +0800255 >;
256 fsl,drive-strength = <0>;
257 fsl,voltage = <1>;
258 fsl,pull-up = <0>;
259 };
Shawn Guoa915ee422012-06-28 11:45:07 +0800260
261 lcdif_24bit_pins_a: lcdif-24bit@0 {
262 reg = <0>;
263 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200264 MX23_PAD_LCD_D00__LCD_D00
265 MX23_PAD_LCD_D01__LCD_D01
266 MX23_PAD_LCD_D02__LCD_D02
267 MX23_PAD_LCD_D03__LCD_D03
268 MX23_PAD_LCD_D04__LCD_D04
269 MX23_PAD_LCD_D05__LCD_D05
270 MX23_PAD_LCD_D06__LCD_D06
271 MX23_PAD_LCD_D07__LCD_D07
272 MX23_PAD_LCD_D08__LCD_D08
273 MX23_PAD_LCD_D09__LCD_D09
274 MX23_PAD_LCD_D10__LCD_D10
275 MX23_PAD_LCD_D11__LCD_D11
276 MX23_PAD_LCD_D12__LCD_D12
277 MX23_PAD_LCD_D13__LCD_D13
278 MX23_PAD_LCD_D14__LCD_D14
279 MX23_PAD_LCD_D15__LCD_D15
280 MX23_PAD_LCD_D16__LCD_D16
281 MX23_PAD_LCD_D17__LCD_D17
282 MX23_PAD_GPMI_D08__LCD_D18
283 MX23_PAD_GPMI_D09__LCD_D19
284 MX23_PAD_GPMI_D10__LCD_D20
285 MX23_PAD_GPMI_D11__LCD_D21
286 MX23_PAD_GPMI_D12__LCD_D22
287 MX23_PAD_GPMI_D13__LCD_D23
288 MX23_PAD_LCD_DOTCK__LCD_DOTCK
289 MX23_PAD_LCD_ENABLE__LCD_ENABLE
290 MX23_PAD_LCD_HSYNC__LCD_HSYNC
291 MX23_PAD_LCD_VSYNC__LCD_VSYNC
Shawn Guoa915ee422012-06-28 11:45:07 +0800292 >;
293 fsl,drive-strength = <0>;
294 fsl,voltage = <1>;
295 fsl,pull-up = <0>;
296 };
Fadil Berishaa0487862012-11-17 16:52:32 -0500297
298 spi2_pins_a: spi2@0 {
299 reg = <0>;
300 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200301 MX23_PAD_GPMI_WRN__SSP2_SCK
302 MX23_PAD_GPMI_RDY1__SSP2_CMD
303 MX23_PAD_GPMI_D00__SSP2_DATA0
304 MX23_PAD_GPMI_D03__SSP2_DATA3
Fadil Berishaa0487862012-11-17 16:52:32 -0500305 >;
306 fsl,drive-strength = <1>;
307 fsl,voltage = <1>;
308 fsl,pull-up = <1>;
309 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800310 };
311
312 digctl@8001c000 {
Shawn Guo38d65902013-03-26 21:11:02 +0800313 compatible = "fsl,imx23-digctl";
Shawn Guo2954ff32012-05-04 21:33:42 +0800314 reg = <0x8001c000 2000>;
315 status = "disabled";
316 };
317
318 emi@80020000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300319 reg = <0x80020000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800320 status = "disabled";
321 };
322
Shawn Guof30fb032013-02-25 21:56:56 +0800323 dma_apbx: dma-apbx@80024000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800324 compatible = "fsl,imx23-dma-apbx";
Fabio Estevam640bf062012-07-30 21:29:18 -0300325 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800326 interrupts = <7 5 9 26
327 19 0 25 23
328 60 58 9 0
329 0 0 0 0>;
330 interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
331 "saif0", "empty", "auart0-rx", "auart0-tx",
332 "auart1-rx", "auart1-tx", "saif1", "empty",
333 "empty", "empty", "empty", "empty";
334 #dma-cells = <1>;
335 dma-channels = <16>;
Shawn Guo53f94432012-08-22 21:36:30 +0800336 clocks = <&clks 16>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800337 };
338
339 dcp@80028000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300340 reg = <0x80028000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800341 status = "disabled";
342 };
343
344 pxp@8002a000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300345 reg = <0x8002a000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800346 status = "disabled";
347 };
348
349 ocotp@8002c000 {
Shawn Guo69d75a02013-03-29 09:59:28 +0800350 compatible = "fsl,ocotp";
Fabio Estevam640bf062012-07-30 21:29:18 -0300351 reg = <0x8002c000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800352 status = "disabled";
353 };
354
355 axi-ahb@8002e000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300356 reg = <0x8002e000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800357 status = "disabled";
358 };
359
360 lcdif@80030000 {
Shawn Guoa915ee422012-06-28 11:45:07 +0800361 compatible = "fsl,imx23-lcdif";
Shawn Guo2954ff32012-05-04 21:33:42 +0800362 reg = <0x80030000 2000>;
Shawn Guoa915ee422012-06-28 11:45:07 +0800363 interrupts = <46 45>;
Shawn Guo53f94432012-08-22 21:36:30 +0800364 clocks = <&clks 38>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800365 status = "disabled";
366 };
367
368 ssp1: ssp@80034000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300369 reg = <0x80034000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800370 interrupts = <2>;
Shawn Guo53f94432012-08-22 21:36:30 +0800371 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +0800372 dmas = <&dma_apbh 2>;
373 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800374 status = "disabled";
375 };
376
377 tvenc@80038000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300378 reg = <0x80038000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800379 status = "disabled";
380 };
381 };
382
383 apbx@80040000 {
384 compatible = "simple-bus";
385 #address-cells = <1>;
386 #size-cells = <1>;
387 reg = <0x80040000 0x40000>;
388 ranges;
389
Shawn Guo53f94432012-08-22 21:36:30 +0800390 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800391 compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
Fabio Estevam640bf062012-07-30 21:29:18 -0300392 reg = <0x80040000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800393 #clock-cells = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800394 };
395
396 saif0: saif@80042000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300397 reg = <0x80042000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800398 dmas = <&dma_apbx 4>;
399 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800400 status = "disabled";
401 };
402
403 power@80044000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300404 reg = <0x80044000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800405 status = "disabled";
406 };
407
408 saif1: saif@80046000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300409 reg = <0x80046000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800410 dmas = <&dma_apbx 10>;
411 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800412 status = "disabled";
413 };
414
415 audio-out@80048000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300416 reg = <0x80048000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800417 dmas = <&dma_apbx 1>;
418 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800419 status = "disabled";
420 };
421
422 audio-in@8004c000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300423 reg = <0x8004c000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800424 dmas = <&dma_apbx 0>;
425 dma-names = "rx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800426 status = "disabled";
427 };
428
429 lradc@80050000 {
Marek Vasut1f451882013-01-21 20:05:00 +0000430 compatible = "fsl,imx23-lradc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300431 reg = <0x80050000 0x2000>;
Marek Vasut1f451882013-01-21 20:05:00 +0000432 interrupts = <36 37 38 39 40 41 42 43 44>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800433 status = "disabled";
434 };
435
436 spdif@80054000 {
437 reg = <0x80054000 2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800438 dmas = <&dma_apbx 2>;
439 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800440 status = "disabled";
441 };
442
443 i2c@80058000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300444 reg = <0x80058000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800445 dmas = <&dma_apbx 3>;
446 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800447 status = "disabled";
448 };
449
450 rtc@8005c000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800451 compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300452 reg = <0x8005c000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800453 interrupts = <22>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800454 };
455
Shawn Guo52f71762012-06-28 11:45:06 +0800456 pwm: pwm@80064000 {
457 compatible = "fsl,imx23-pwm";
Fabio Estevam640bf062012-07-30 21:29:18 -0300458 reg = <0x80064000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800459 clocks = <&clks 30>;
Shawn Guo52f71762012-06-28 11:45:06 +0800460 #pwm-cells = <2>;
461 fsl,pwm-number = <5>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800462 status = "disabled";
463 };
464
465 timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800466 compatible = "fsl,imx23-timrot", "fsl,timrot";
Fabio Estevam640bf062012-07-30 21:29:18 -0300467 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800468 interrupts = <28 29 30 31>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800469 clocks = <&clks 28>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800470 };
471
472 auart0: serial@8006c000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800473 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800474 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800475 interrupts = <24>;
Shawn Guo53f94432012-08-22 21:36:30 +0800476 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800477 dmas = <&dma_apbx 6>, <&dma_apbx 7>;
478 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800479 status = "disabled";
480 };
481
482 auart1: serial@8006e000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800483 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800484 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800485 interrupts = <59>;
Shawn Guo53f94432012-08-22 21:36:30 +0800486 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800487 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
488 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800489 status = "disabled";
490 };
491
492 duart: serial@80070000 {
493 compatible = "arm,pl011", "arm,primecell";
494 reg = <0x80070000 0x2000>;
495 interrupts = <0>;
Shawn Guo53f94432012-08-22 21:36:30 +0800496 clocks = <&clks 32>, <&clks 16>;
497 clock-names = "uart", "apb_pclk";
Shawn Guo2954ff32012-05-04 21:33:42 +0800498 status = "disabled";
499 };
500
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300501 usbphy0: usbphy@8007c000 {
502 compatible = "fsl,imx23-usbphy";
Shawn Guo2954ff32012-05-04 21:33:42 +0800503 reg = <0x8007c000 0x2000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300504 clocks = <&clks 41>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800505 status = "disabled";
506 };
507 };
508 };
509
510 ahb@80080000 {
511 compatible = "simple-bus";
512 #address-cells = <1>;
513 #size-cells = <1>;
514 reg = <0x80080000 0x80000>;
515 ranges;
516
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300517 usb0: usb@80080000 {
518 compatible = "fsl,imx23-usb", "fsl,imx27-usb";
Fabio Estevam640bf062012-07-30 21:29:18 -0300519 reg = <0x80080000 0x40000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300520 interrupts = <11>;
521 fsl,usbphy = <&usbphy0>;
522 clocks = <&clks 40>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800523 status = "disabled";
524 };
525 };
526};