Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Jonathan Austin | a2b45b0 | 2013-02-21 17:49:24 +0000 | [diff] [blame] | 2 | #ifndef __ARM_MPU_H |
| 3 | #define __ARM_MPU_H |
| 4 | |
Jonathan Austin | a2b45b0 | 2013-02-21 17:49:24 +0000 | [diff] [blame] | 5 | /* MPUIR layout */ |
| 6 | #define MPUIR_nU 1 |
| 7 | #define MPUIR_DREGION 8 |
| 8 | #define MPUIR_IREGION 16 |
| 9 | #define MPUIR_DREGION_SZMASK (0xFF << MPUIR_DREGION) |
| 10 | #define MPUIR_IREGION_SZMASK (0xFF << MPUIR_IREGION) |
| 11 | |
| 12 | /* ID_MMFR0 data relevant to MPU */ |
| 13 | #define MMFR0_PMSA (0xF << 4) |
| 14 | #define MMFR0_PMSAv7 (3 << 4) |
| 15 | |
| 16 | /* MPU D/I Size Register fields */ |
| 17 | #define MPU_RSR_SZ 1 |
| 18 | #define MPU_RSR_EN 0 |
Vladimir Murzin | 5c9d9a1 | 2017-10-16 12:59:15 +0100 | [diff] [blame] | 19 | #define MPU_RSR_SD 8 |
| 20 | |
| 21 | /* Number of subregions (SD) */ |
| 22 | #define MPU_NR_SUBREGS 8 |
| 23 | #define MPU_MIN_SUBREG_SIZE 256 |
Jonathan Austin | a2b45b0 | 2013-02-21 17:49:24 +0000 | [diff] [blame] | 24 | |
| 25 | /* The D/I RSR value for an enabled region spanning the whole of memory */ |
| 26 | #define MPU_RSR_ALL_MEM 63 |
| 27 | |
| 28 | /* Individual bits in the DR/IR ACR */ |
| 29 | #define MPU_ACR_XN (1 << 12) |
| 30 | #define MPU_ACR_SHARED (1 << 2) |
| 31 | |
| 32 | /* C, B and TEX[2:0] bits only have semantic meanings when grouped */ |
| 33 | #define MPU_RGN_CACHEABLE 0xB |
| 34 | #define MPU_RGN_SHARED_CACHEABLE (MPU_RGN_CACHEABLE | MPU_ACR_SHARED) |
| 35 | #define MPU_RGN_STRONGLY_ORDERED 0 |
| 36 | |
| 37 | /* Main region should only be shared for SMP */ |
| 38 | #ifdef CONFIG_SMP |
| 39 | #define MPU_RGN_NORMAL (MPU_RGN_CACHEABLE | MPU_ACR_SHARED) |
| 40 | #else |
| 41 | #define MPU_RGN_NORMAL MPU_RGN_CACHEABLE |
| 42 | #endif |
| 43 | |
| 44 | /* Access permission bits of ACR (only define those that we use)*/ |
Vladimir Murzin | 2162183 | 2017-10-16 13:00:45 +0100 | [diff] [blame] | 45 | #define MPU_AP_PL1RO_PL0NA (0x5 << 8) |
Jonathan Austin | a2b45b0 | 2013-02-21 17:49:24 +0000 | [diff] [blame] | 46 | #define MPU_AP_PL1RW_PL0RW (0x3 << 8) |
| 47 | #define MPU_AP_PL1RW_PL0R0 (0x2 << 8) |
| 48 | #define MPU_AP_PL1RW_PL0NA (0x1 << 8) |
| 49 | |
| 50 | /* For minimal static MPU region configurations */ |
| 51 | #define MPU_PROBE_REGION 0 |
| 52 | #define MPU_BG_REGION 1 |
| 53 | #define MPU_RAM_REGION 2 |
Vladimir Murzin | 2162183 | 2017-10-16 13:00:45 +0100 | [diff] [blame] | 54 | #define MPU_ROM_REGION 3 |
Jonathan Austin | a2b45b0 | 2013-02-21 17:49:24 +0000 | [diff] [blame] | 55 | |
| 56 | /* Maximum number of regions Linux is interested in */ |
| 57 | #define MPU_MAX_REGIONS 16 |
| 58 | |
Jonathan Austin | 67c9845 | 2013-02-22 17:48:56 +0000 | [diff] [blame] | 59 | #define MPU_DATA_SIDE 0 |
| 60 | #define MPU_INSTR_SIDE 1 |
| 61 | |
Jonathan Austin | a2b45b0 | 2013-02-21 17:49:24 +0000 | [diff] [blame] | 62 | #ifndef __ASSEMBLY__ |
| 63 | |
| 64 | struct mpu_rgn { |
| 65 | /* Assume same attributes for d/i-side */ |
| 66 | u32 drbar; |
| 67 | u32 drsr; |
| 68 | u32 dracr; |
| 69 | }; |
| 70 | |
| 71 | struct mpu_rgn_info { |
Vladimir Murzin | a0995c08 | 2017-10-16 12:54:05 +0100 | [diff] [blame] | 72 | unsigned int used; |
Jonathan Austin | a2b45b0 | 2013-02-21 17:49:24 +0000 | [diff] [blame] | 73 | struct mpu_rgn rgns[MPU_MAX_REGIONS]; |
| 74 | }; |
| 75 | extern struct mpu_rgn_info mpu_rgn_info; |
| 76 | |
Vladimir Murzin | 877ec11 | 2017-10-16 12:52:35 +0100 | [diff] [blame] | 77 | #ifdef CONFIG_ARM_MPU |
Jonathan Austin | a2b45b0 | 2013-02-21 17:49:24 +0000 | [diff] [blame] | 78 | |
Vladimir Murzin | 877ec11 | 2017-10-16 12:52:35 +0100 | [diff] [blame] | 79 | extern void __init adjust_lowmem_bounds_mpu(void); |
| 80 | extern void __init mpu_setup(void); |
| 81 | |
| 82 | #else |
| 83 | |
| 84 | static inline void adjust_lowmem_bounds_mpu(void) {} |
| 85 | static inline void mpu_setup(void) {} |
| 86 | |
| 87 | #endif /* !CONFIG_ARM_MPU */ |
| 88 | |
| 89 | #endif /* __ASSEMBLY__ */ |
Jonathan Austin | a2b45b0 | 2013-02-21 17:49:24 +0000 | [diff] [blame] | 90 | |
| 91 | #endif |