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Andi Shyti78b5d702017-12-14 15:28:27 +09001/* SPDX-License-Identifier: GPL-2.0 */
2
Sachin Kamat963eb4b2014-02-14 12:26:17 +05303/*
Jassi Brar398cccc2010-01-18 17:45:52 +09004 * Copyright (C) 2009 Samsung Electronics Ltd.
5 * Jaswinder Singh <jassi.brar@samsung.com>
Jassi Brar398cccc2010-01-18 17:45:52 +09006 */
7
Sachin Kamat963eb4b2014-02-14 12:26:17 +05308#ifndef __SPI_S3C64XX_H
9#define __SPI_S3C64XX_H
Jassi Brar398cccc2010-01-18 17:45:52 +090010
Arnd Bergmann78843722013-04-11 22:42:03 +020011#include <linux/dmaengine.h>
12
Mark Brown5b0b34e2011-12-29 18:01:08 +090013struct platform_device;
14
Jassi Brar398cccc2010-01-18 17:45:52 +090015/**
16 * struct s3c64xx_spi_csinfo - ChipSelect description
17 * @fb_delay: Slave specific feedback delay.
18 * Refer to FB_CLK_SEL register definition in SPI chapter.
19 * @line: Custom 'identity' of the CS line.
Jassi Brar398cccc2010-01-18 17:45:52 +090020 *
21 * This is per SPI-Slave Chipselect information.
22 * Allocate and initialize one in machine init code and make the
23 * spi_board_info.controller_data point to it.
24 */
25struct s3c64xx_spi_csinfo {
26 u8 fb_delay;
27 unsigned line;
Jassi Brar398cccc2010-01-18 17:45:52 +090028};
29
30/**
31 * struct s3c64xx_spi_info - SPI Controller defining structure
32 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
Jassi Brar398cccc2010-01-18 17:45:52 +090033 * @num_cs: Number of CS this controller emulates.
34 * @cfg_gpio: Configure pins for this SPI controller.
Jassi Brar398cccc2010-01-18 17:45:52 +090035 */
36struct s3c64xx_spi_info {
37 int src_clk_nr;
Jassi Brar398cccc2010-01-18 17:45:52 +090038 int num_cs;
Andi Shytia92e7c32016-06-28 11:41:12 +090039 bool no_cs;
Thomas Abraham868dee92012-07-13 07:15:14 +090040 int (*cfg_gpio)(void);
Jassi Brar398cccc2010-01-18 17:45:52 +090041};
42
43/**
Padmavathi Venna875a5932011-12-23 10:14:31 +090044 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
Jassi Brar398cccc2010-01-18 17:45:52 +090045 * initialization code.
Thomas Abraham4d0efdd2012-07-13 07:15:14 +090046 * @cfg_gpio: Pointer to gpio setup function.
Jassi Brar398cccc2010-01-18 17:45:52 +090047 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
48 * @num_cs: Number of elements in the 'cs' array.
49 *
50 * Call this from machine init code for each SPI Controller that
51 * has some chips attached to it.
52 */
Thomas Abraham4d0efdd2012-07-13 07:15:14 +090053extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
54 int num_cs);
55extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
56 int num_cs);
57extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
58 int num_cs);
Padmavathi Venna4566c7f2011-12-23 10:14:36 +090059
60/* defined by architecture to configure gpio */
Thomas Abraham868dee92012-07-13 07:15:14 +090061extern int s3c64xx_spi0_cfg_gpio(void);
62extern int s3c64xx_spi1_cfg_gpio(void);
63extern int s3c64xx_spi2_cfg_gpio(void);
Padmavathi Venna4566c7f2011-12-23 10:14:36 +090064
65extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
66extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
Padmavathi Venna323d7712011-12-23 10:14:45 +090067extern struct s3c64xx_spi_info s3c64xx_spi2_pdata;
Sachin Kamat963eb4b2014-02-14 12:26:17 +053068#endif /*__SPI_S3C64XX_H */