| Holger Schurig | 260a1fd | 2009-01-26 16:34:53 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de |
| 4 | * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de |
| 5 | * |
| 6 | * This contains i.MX21-specific hardware definitions. For those |
| 7 | * hardware pieces that are common between i.MX21 and i.MX27, have a |
| 8 | * look at mx2x.h. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License |
| 12 | * as published by the Free Software Foundation; either version 2 |
| 13 | * of the License, or (at your option) any later version. |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
| 22 | * MA 02110-1301, USA. |
| 23 | */ |
| 24 | |
| 25 | #ifndef __ASM_ARCH_MXC_MX21_H__ |
| 26 | #define __ASM_ARCH_MXC_MX21_H__ |
| 27 | |
| 28 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ |
| 29 | #error "Do not include directly." |
| 30 | #endif |
| 31 | |
| 32 | |
| 33 | /* Memory regions and CS */ |
| 34 | #define SDRAM_BASE_ADDR 0xC0000000 |
| 35 | #define CSD1_BASE_ADDR 0xC4000000 |
| 36 | |
| 37 | #define CS0_BASE_ADDR 0xC8000000 |
| 38 | #define CS1_BASE_ADDR 0xCC000000 |
| 39 | #define CS2_BASE_ADDR 0xD0000000 |
| 40 | #define CS3_BASE_ADDR 0xD1000000 |
| 41 | #define CS4_BASE_ADDR 0xD2000000 |
| 42 | #define CS5_BASE_ADDR 0xDD000000 |
| 43 | #define PCMCIA_MEM_BASE_ADDR 0xD4000000 |
| 44 | |
| 45 | /* NAND, SDRAM, WEIM etc controllers */ |
| 46 | #define X_MEMC_BASE_ADDR 0xDF000000 |
| 47 | #define X_MEMC_BASE_ADDR_VIRT 0xF4200000 |
| 48 | #define X_MEMC_SIZE SZ_256K |
| 49 | |
| 50 | #define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) |
| 51 | #define EIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) |
| 52 | #define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) |
| 53 | #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) |
| 54 | |
| 55 | #define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */ |
| 56 | |
| 57 | /* this is an i.MX21 CPU */ |
| 58 | #define cpu_is_mx21() (1) |
| 59 | |
| 60 | /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ |
| 61 | #define ARCH_NR_GPIOS (6*32 + 16) |
| 62 | |
| 63 | /* fixed interrupt numbers */ |
| 64 | #define MXC_INT_USBCTRL 58 |
| 65 | #define MXC_INT_USBCTRL 58 |
| 66 | #define MXC_INT_USBMNP 57 |
| 67 | #define MXC_INT_USBFUNC 56 |
| 68 | #define MXC_INT_USBHOST 55 |
| 69 | #define MXC_INT_USBDMA 54 |
| 70 | #define MXC_INT_USBWKUP 53 |
| 71 | #define MXC_INT_EMMADEC 50 |
| 72 | #define MXC_INT_EMMAENC 49 |
| 73 | #define MXC_INT_BMI 30 |
| 74 | #define MXC_INT_FIRI 9 |
| 75 | |
| 76 | /* fixed DMA request numbers */ |
| 77 | #define DMA_REQ_BMI_RX 29 |
| 78 | #define DMA_REQ_BMI_TX 28 |
| 79 | #define DMA_REQ_FIRI_RX 4 |
| 80 | |
| 81 | #endif /* __ASM_ARCH_MXC_MX21_H__ */ |