blob: d45df17635988307ce3aa34cdf9023fe95008e92 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090033#include <linux/slab.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020034#include <drm/drmP.h>
35#include "radeon_drm.h"
36#include "radeon.h"
Dave Airlie99ee7fa2010-11-23 11:47:49 +100037#include "radeon_trace.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020038
Jerome Glisse771fe6b2009-06-05 14:42:42 +020039
40int radeon_ttm_init(struct radeon_device *rdev);
41void radeon_ttm_fini(struct radeon_device *rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +010042static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020043
44/*
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
47 */
48
Jerome Glisse721604a2012-01-05 22:11:05 -050049void radeon_bo_clear_va(struct radeon_bo *bo)
50{
51 struct radeon_bo_va *bo_va, *tmp;
52
53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
54 /* remove from all vm address space */
55 mutex_lock(&bo_va->vm->mutex);
56 list_del(&bo_va->vm_list);
57 mutex_unlock(&bo_va->vm->mutex);
58 list_del(&bo_va->bo_list);
59 kfree(bo_va);
60 }
61}
62
Jerome Glisse4c788672009-11-20 14:29:23 +010063static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020064{
Jerome Glisse4c788672009-11-20 14:29:23 +010065 struct radeon_bo *bo;
66
67 bo = container_of(tbo, struct radeon_bo, tbo);
68 mutex_lock(&bo->rdev->gem.mutex);
69 list_del_init(&bo->list);
70 mutex_unlock(&bo->rdev->gem.mutex);
71 radeon_bo_clear_surface_reg(bo);
Jerome Glisse721604a2012-01-05 22:11:05 -050072 radeon_bo_clear_va(bo);
Daniel Vetter441921d2011-02-18 17:59:16 +010073 drm_gem_object_release(&bo->gem_base);
Jerome Glisse4c788672009-11-20 14:29:23 +010074 kfree(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020075}
76
Jerome Glissed03d8582009-12-14 21:02:09 +010077bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
78{
79 if (bo->destroy == &radeon_ttm_bo_destroy)
80 return true;
81 return false;
82}
83
Jerome Glisse312ea8d2009-12-07 15:52:58 +010084void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
85{
86 u32 c = 0;
87
88 rbo->placement.fpfn = 0;
Jerome Glisse93225b02010-12-03 16:38:19 -050089 rbo->placement.lpfn = 0;
Jerome Glisse312ea8d2009-12-07 15:52:58 +010090 rbo->placement.placement = rbo->placements;
91 rbo->placement.busy_placement = rbo->placements;
92 if (domain & RADEON_GEM_DOMAIN_VRAM)
93 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
94 TTM_PL_FLAG_VRAM;
95 if (domain & RADEON_GEM_DOMAIN_GTT)
96 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
97 if (domain & RADEON_GEM_DOMAIN_CPU)
98 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
Jerome Glisse9fb03e62009-12-11 15:13:22 +010099 if (!c)
100 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100101 rbo->placement.num_placement = c;
102 rbo->placement.num_busy_placement = c;
103}
104
Daniel Vetter441921d2011-02-18 17:59:16 +0100105int radeon_bo_create(struct radeon_device *rdev,
Alex Deucher268b2512010-11-17 19:00:26 -0500106 unsigned long size, int byte_align, bool kernel, u32 domain,
107 struct radeon_bo **bo_ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200108{
Jerome Glisse4c788672009-11-20 14:29:23 +0100109 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200110 enum ttm_bo_type type;
Jerome Glisse93225b02010-12-03 16:38:19 -0500111 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
112 unsigned long max_size = 0;
Jerome Glisse57de4ba2011-11-11 15:42:57 -0500113 size_t acc_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200114 int r;
115
Daniel Vetter441921d2011-02-18 17:59:16 +0100116 size = ALIGN(size, PAGE_SIZE);
117
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200118 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
119 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
120 }
121 if (kernel) {
122 type = ttm_bo_type_kernel;
123 } else {
124 type = ttm_bo_type_device;
125 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100126 *bo_ptr = NULL;
Michel Dänzer2b66b502010-11-09 11:50:05 +0100127
Jerome Glisse93225b02010-12-03 16:38:19 -0500128 /* maximun bo size is the minimun btw visible vram and gtt size */
129 max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
130 if ((page_align << PAGE_SHIFT) >= max_size) {
131 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
132 __func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20);
133 return -ENOMEM;
134 }
135
Jerome Glisse57de4ba2011-11-11 15:42:57 -0500136 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
137 sizeof(struct radeon_bo));
138
Michel Dänzer2b66b502010-11-09 11:50:05 +0100139retry:
Jerome Glisse4c788672009-11-20 14:29:23 +0100140 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
141 if (bo == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200142 return -ENOMEM;
Daniel Vetter441921d2011-02-18 17:59:16 +0100143 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
144 if (unlikely(r)) {
145 kfree(bo);
146 return r;
147 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100148 bo->rdev = rdev;
Daniel Vetter7e4d15d2011-02-18 17:59:17 +0100149 bo->gem_base.driver_private = NULL;
Jerome Glisse4c788672009-11-20 14:29:23 +0100150 bo->surface_reg = -1;
151 INIT_LIST_HEAD(&bo->list);
Jerome Glisse721604a2012-01-05 22:11:05 -0500152 INIT_LIST_HEAD(&bo->va);
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100153 radeon_ttm_placement_from_domain(bo, domain);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100154 /* Kernel allocation are uninterruptible */
Matthew Garrett5876dd22010-04-26 15:52:20 -0400155 mutex_lock(&rdev->vram_mutex);
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100156 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
Jerome Glisse57de4ba2011-11-11 15:42:57 -0500157 &bo->placement, page_align, 0, !kernel, NULL,
158 acc_size, &radeon_ttm_bo_destroy);
Matthew Garrett5876dd22010-04-26 15:52:20 -0400159 mutex_unlock(&rdev->vram_mutex);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200160 if (unlikely(r != 0)) {
Michel Dänzere376573f2010-07-08 12:43:28 +1000161 if (r != -ERESTARTSYS) {
162 if (domain == RADEON_GEM_DOMAIN_VRAM) {
163 domain |= RADEON_GEM_DOMAIN_GTT;
164 goto retry;
165 }
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100166 dev_err(rdev->dev,
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100167 "object_init failed for (%lu, 0x%08X)\n",
168 size, domain);
Michel Dänzere376573f2010-07-08 12:43:28 +1000169 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200170 return r;
171 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100172 *bo_ptr = bo;
Daniel Vetter441921d2011-02-18 17:59:16 +0100173
Dave Airlie99ee7fa2010-11-23 11:47:49 +1000174 trace_radeon_bo_create(bo);
Daniel Vetter441921d2011-02-18 17:59:16 +0100175
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200176 return 0;
177}
178
Jerome Glisse4c788672009-11-20 14:29:23 +0100179int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200180{
Jerome Glisse4c788672009-11-20 14:29:23 +0100181 bool is_iomem;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200182 int r;
183
Jerome Glisse4c788672009-11-20 14:29:23 +0100184 if (bo->kptr) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200185 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100186 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200187 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200188 return 0;
189 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100190 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200191 if (r) {
192 return r;
193 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100194 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200195 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100196 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200197 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100198 radeon_bo_check_tiling(bo, 0, 0);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200199 return 0;
200}
201
Jerome Glisse4c788672009-11-20 14:29:23 +0100202void radeon_bo_kunmap(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200203{
Jerome Glisse4c788672009-11-20 14:29:23 +0100204 if (bo->kptr == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200205 return;
Jerome Glisse4c788672009-11-20 14:29:23 +0100206 bo->kptr = NULL;
207 radeon_bo_check_tiling(bo, 0, 0);
208 ttm_bo_kunmap(&bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200209}
210
Jerome Glisse4c788672009-11-20 14:29:23 +0100211void radeon_bo_unref(struct radeon_bo **bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200212{
Jerome Glisse4c788672009-11-20 14:29:23 +0100213 struct ttm_buffer_object *tbo;
Dave Airlief4b7fb92010-04-29 18:37:59 +1000214 struct radeon_device *rdev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200215
Jerome Glisse4c788672009-11-20 14:29:23 +0100216 if ((*bo) == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200217 return;
Dave Airlief4b7fb92010-04-29 18:37:59 +1000218 rdev = (*bo)->rdev;
Jerome Glisse4c788672009-11-20 14:29:23 +0100219 tbo = &((*bo)->tbo);
Dave Airlief4b7fb92010-04-29 18:37:59 +1000220 mutex_lock(&rdev->vram_mutex);
Jerome Glisse4c788672009-11-20 14:29:23 +0100221 ttm_bo_unref(&tbo);
Dave Airlief4b7fb92010-04-29 18:37:59 +1000222 mutex_unlock(&rdev->vram_mutex);
Jerome Glisse4c788672009-11-20 14:29:23 +0100223 if (tbo == NULL)
224 *bo = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200225}
226
Jerome Glisse4c788672009-11-20 14:29:23 +0100227int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200228{
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100229 int r, i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200230
Jerome Glisse4c788672009-11-20 14:29:23 +0100231 if (bo->pin_count) {
232 bo->pin_count++;
233 if (gpu_addr)
234 *gpu_addr = radeon_bo_gpu_offset(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200235 return 0;
236 }
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100237 radeon_ttm_placement_from_domain(bo, domain);
Michel Dänzer3ca82da2010-03-26 19:18:55 +0000238 if (domain == RADEON_GEM_DOMAIN_VRAM) {
239 /* force to pin into visible video ram */
240 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
241 }
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100242 for (i = 0; i < bo->placement.num_placement; i++)
243 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
Jerome Glisse9d87fa22010-04-07 10:21:19 +0000244 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
Jerome Glisse4c788672009-11-20 14:29:23 +0100245 if (likely(r == 0)) {
246 bo->pin_count = 1;
247 if (gpu_addr != NULL)
248 *gpu_addr = radeon_bo_gpu_offset(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200249 }
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100250 if (unlikely(r != 0))
Jerome Glisse4c788672009-11-20 14:29:23 +0100251 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200252 return r;
253}
254
Jerome Glisse4c788672009-11-20 14:29:23 +0100255int radeon_bo_unpin(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200256{
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100257 int r, i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200258
Jerome Glisse4c788672009-11-20 14:29:23 +0100259 if (!bo->pin_count) {
260 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
261 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200262 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100263 bo->pin_count--;
264 if (bo->pin_count)
265 return 0;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100266 for (i = 0; i < bo->placement.num_placement; i++)
267 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
Jerome Glisse9d87fa22010-04-07 10:21:19 +0000268 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100269 if (unlikely(r != 0))
Jerome Glisse4c788672009-11-20 14:29:23 +0100270 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100271 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200272}
273
Jerome Glisse4c788672009-11-20 14:29:23 +0100274int radeon_bo_evict_vram(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200275{
Dave Airlied796d842010-01-25 13:08:08 +1000276 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
277 if (0 && (rdev->flags & RADEON_IS_IGP)) {
Alex Deucher06b64762010-01-05 11:27:29 -0500278 if (rdev->mc.igp_sideport_enabled == false)
279 /* Useless to evict on IGP chips */
280 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200281 }
282 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
283}
284
Jerome Glisse4c788672009-11-20 14:29:23 +0100285void radeon_bo_force_delete(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200286{
Jerome Glisse4c788672009-11-20 14:29:23 +0100287 struct radeon_bo *bo, *n;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200288
289 if (list_empty(&rdev->gem.objects)) {
290 return;
291 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100292 dev_err(rdev->dev, "Userspace still has active objects !\n");
293 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200294 mutex_lock(&rdev->ddev->struct_mutex);
Jerome Glisse4c788672009-11-20 14:29:23 +0100295 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
Daniel Vetter31c36032011-02-18 17:59:18 +0100296 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
297 *((unsigned long *)&bo->gem_base.refcount));
Jerome Glisse4c788672009-11-20 14:29:23 +0100298 mutex_lock(&bo->rdev->gem.mutex);
299 list_del_init(&bo->list);
300 mutex_unlock(&bo->rdev->gem.mutex);
Dave Airlie91132d62011-03-01 13:40:06 +1000301 /* this should unref the ttm bo */
Daniel Vetter31c36032011-02-18 17:59:18 +0100302 drm_gem_object_unreference(&bo->gem_base);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200303 mutex_unlock(&rdev->ddev->struct_mutex);
304 }
305}
306
Jerome Glisse4c788672009-11-20 14:29:23 +0100307int radeon_bo_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200308{
Jerome Glissea4d68272009-09-11 13:00:43 +0200309 /* Add an MTRR for the VRAM */
310 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
311 MTRR_TYPE_WRCOMB, 1);
312 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
313 rdev->mc.mc_vram_size >> 20,
314 (unsigned long long)rdev->mc.aper_size >> 20);
315 DRM_INFO("RAM width %dbits %cDR\n",
316 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200317 return radeon_ttm_init(rdev);
318}
319
Jerome Glisse4c788672009-11-20 14:29:23 +0100320void radeon_bo_fini(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200321{
322 radeon_ttm_fini(rdev);
323}
324
Jerome Glisse4c788672009-11-20 14:29:23 +0100325void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
326 struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200327{
328 if (lobj->wdomain) {
Thomas Hellstrom147666f2010-11-17 12:38:32 +0000329 list_add(&lobj->tv.head, head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200330 } else {
Thomas Hellstrom147666f2010-11-17 12:38:32 +0000331 list_add_tail(&lobj->tv.head, head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200332 }
333}
334
Jerome Glisse6cb8e1f2010-02-15 21:36:33 +0100335int radeon_bo_list_validate(struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200336{
Jerome Glisse4c788672009-11-20 14:29:23 +0100337 struct radeon_bo_list *lobj;
338 struct radeon_bo *bo;
Michel Dänzere376573f2010-07-08 12:43:28 +1000339 u32 domain;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200340 int r;
341
Thomas Hellstrom147666f2010-11-17 12:38:32 +0000342 r = ttm_eu_reserve_buffers(head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200343 if (unlikely(r != 0)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200344 return r;
345 }
Thomas Hellstrom147666f2010-11-17 12:38:32 +0000346 list_for_each_entry(lobj, head, tv.head) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100347 bo = lobj->bo;
348 if (!bo->pin_count) {
Michel Dänzere376573f2010-07-08 12:43:28 +1000349 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
350
351 retry:
352 radeon_ttm_placement_from_domain(bo, domain);
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100353 r = ttm_bo_validate(&bo->tbo, &bo->placement,
Jerome Glisse9d87fa22010-04-07 10:21:19 +0000354 true, false, false);
Michel Dänzere376573f2010-07-08 12:43:28 +1000355 if (unlikely(r)) {
356 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
357 domain |= RADEON_GEM_DOMAIN_GTT;
358 goto retry;
359 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200360 return r;
Michel Dänzere376573f2010-07-08 12:43:28 +1000361 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200362 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100363 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
364 lobj->tiling_flags = bo->tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200365 }
366 return 0;
367}
368
Jerome Glisse4c788672009-11-20 14:29:23 +0100369int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200370 struct vm_area_struct *vma)
371{
Jerome Glisse4c788672009-11-20 14:29:23 +0100372 return ttm_fbdev_mmap(vma, &bo->tbo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200373}
374
Dave Airlie550e2d92009-12-09 14:15:38 +1000375int radeon_bo_get_surface_reg(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200376{
Jerome Glisse4c788672009-11-20 14:29:23 +0100377 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000378 struct radeon_surface_reg *reg;
Jerome Glisse4c788672009-11-20 14:29:23 +0100379 struct radeon_bo *old_object;
Dave Airliee024e112009-06-24 09:48:08 +1000380 int steal;
381 int i;
382
Jerome Glisse4c788672009-11-20 14:29:23 +0100383 BUG_ON(!atomic_read(&bo->tbo.reserved));
384
385 if (!bo->tiling_flags)
Dave Airliee024e112009-06-24 09:48:08 +1000386 return 0;
387
Jerome Glisse4c788672009-11-20 14:29:23 +0100388 if (bo->surface_reg >= 0) {
389 reg = &rdev->surface_regs[bo->surface_reg];
390 i = bo->surface_reg;
Dave Airliee024e112009-06-24 09:48:08 +1000391 goto out;
392 }
393
394 steal = -1;
395 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
396
397 reg = &rdev->surface_regs[i];
Jerome Glisse4c788672009-11-20 14:29:23 +0100398 if (!reg->bo)
Dave Airliee024e112009-06-24 09:48:08 +1000399 break;
400
Jerome Glisse4c788672009-11-20 14:29:23 +0100401 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000402 if (old_object->pin_count == 0)
403 steal = i;
404 }
405
406 /* if we are all out */
407 if (i == RADEON_GEM_MAX_SURFACES) {
408 if (steal == -1)
409 return -ENOMEM;
410 /* find someone with a surface reg and nuke their BO */
411 reg = &rdev->surface_regs[steal];
Jerome Glisse4c788672009-11-20 14:29:23 +0100412 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000413 /* blow away the mapping */
414 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
Jerome Glisse4c788672009-11-20 14:29:23 +0100415 ttm_bo_unmap_virtual(&old_object->tbo);
Dave Airliee024e112009-06-24 09:48:08 +1000416 old_object->surface_reg = -1;
417 i = steal;
418 }
419
Jerome Glisse4c788672009-11-20 14:29:23 +0100420 bo->surface_reg = i;
421 reg->bo = bo;
Dave Airliee024e112009-06-24 09:48:08 +1000422
423out:
Jerome Glisse4c788672009-11-20 14:29:23 +0100424 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
Ben Skeggsd961db72010-08-05 10:48:18 +1000425 bo->tbo.mem.start << PAGE_SHIFT,
Jerome Glisse4c788672009-11-20 14:29:23 +0100426 bo->tbo.num_pages << PAGE_SHIFT);
Dave Airliee024e112009-06-24 09:48:08 +1000427 return 0;
428}
429
Jerome Glisse4c788672009-11-20 14:29:23 +0100430static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
Dave Airliee024e112009-06-24 09:48:08 +1000431{
Jerome Glisse4c788672009-11-20 14:29:23 +0100432 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000433 struct radeon_surface_reg *reg;
434
Jerome Glisse4c788672009-11-20 14:29:23 +0100435 if (bo->surface_reg == -1)
Dave Airliee024e112009-06-24 09:48:08 +1000436 return;
437
Jerome Glisse4c788672009-11-20 14:29:23 +0100438 reg = &rdev->surface_regs[bo->surface_reg];
439 radeon_clear_surface_reg(rdev, bo->surface_reg);
Dave Airliee024e112009-06-24 09:48:08 +1000440
Jerome Glisse4c788672009-11-20 14:29:23 +0100441 reg->bo = NULL;
442 bo->surface_reg = -1;
Dave Airliee024e112009-06-24 09:48:08 +1000443}
444
Jerome Glisse4c788672009-11-20 14:29:23 +0100445int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
446 uint32_t tiling_flags, uint32_t pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000447{
Jerome Glisse4c788672009-11-20 14:29:23 +0100448 int r;
449
450 r = radeon_bo_reserve(bo, false);
451 if (unlikely(r != 0))
452 return r;
453 bo->tiling_flags = tiling_flags;
454 bo->pitch = pitch;
455 radeon_bo_unreserve(bo);
456 return 0;
Dave Airliee024e112009-06-24 09:48:08 +1000457}
458
Jerome Glisse4c788672009-11-20 14:29:23 +0100459void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
460 uint32_t *tiling_flags,
461 uint32_t *pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000462{
Jerome Glisse4c788672009-11-20 14:29:23 +0100463 BUG_ON(!atomic_read(&bo->tbo.reserved));
Dave Airliee024e112009-06-24 09:48:08 +1000464 if (tiling_flags)
Jerome Glisse4c788672009-11-20 14:29:23 +0100465 *tiling_flags = bo->tiling_flags;
Dave Airliee024e112009-06-24 09:48:08 +1000466 if (pitch)
Jerome Glisse4c788672009-11-20 14:29:23 +0100467 *pitch = bo->pitch;
Dave Airliee024e112009-06-24 09:48:08 +1000468}
469
Jerome Glisse4c788672009-11-20 14:29:23 +0100470int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
471 bool force_drop)
Dave Airliee024e112009-06-24 09:48:08 +1000472{
Jerome Glisse4c788672009-11-20 14:29:23 +0100473 BUG_ON(!atomic_read(&bo->tbo.reserved));
474
475 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
Dave Airliee024e112009-06-24 09:48:08 +1000476 return 0;
477
478 if (force_drop) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100479 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000480 return 0;
481 }
482
Jerome Glisse4c788672009-11-20 14:29:23 +0100483 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
Dave Airliee024e112009-06-24 09:48:08 +1000484 if (!has_moved)
485 return 0;
486
Jerome Glisse4c788672009-11-20 14:29:23 +0100487 if (bo->surface_reg >= 0)
488 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000489 return 0;
490 }
491
Jerome Glisse4c788672009-11-20 14:29:23 +0100492 if ((bo->surface_reg >= 0) && !has_moved)
Dave Airliee024e112009-06-24 09:48:08 +1000493 return 0;
494
Jerome Glisse4c788672009-11-20 14:29:23 +0100495 return radeon_bo_get_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000496}
497
498void radeon_bo_move_notify(struct ttm_buffer_object *bo,
Jerome Glissed03d8582009-12-14 21:02:09 +0100499 struct ttm_mem_reg *mem)
Dave Airliee024e112009-06-24 09:48:08 +1000500{
Jerome Glissed03d8582009-12-14 21:02:09 +0100501 struct radeon_bo *rbo;
502 if (!radeon_ttm_bo_is_radeon_bo(bo))
503 return;
504 rbo = container_of(bo, struct radeon_bo, tbo);
Jerome Glisse4c788672009-11-20 14:29:23 +0100505 radeon_bo_check_tiling(rbo, 0, 1);
Jerome Glisse721604a2012-01-05 22:11:05 -0500506 radeon_vm_bo_invalidate(rbo->rdev, rbo);
Dave Airliee024e112009-06-24 09:48:08 +1000507}
508
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200509int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
Dave Airliee024e112009-06-24 09:48:08 +1000510{
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200511 struct radeon_device *rdev;
Jerome Glissed03d8582009-12-14 21:02:09 +0100512 struct radeon_bo *rbo;
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200513 unsigned long offset, size;
514 int r;
515
Jerome Glissed03d8582009-12-14 21:02:09 +0100516 if (!radeon_ttm_bo_is_radeon_bo(bo))
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200517 return 0;
Jerome Glissed03d8582009-12-14 21:02:09 +0100518 rbo = container_of(bo, struct radeon_bo, tbo);
Jerome Glisse4c788672009-11-20 14:29:23 +0100519 radeon_bo_check_tiling(rbo, 0, 0);
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200520 rdev = rbo->rdev;
521 if (bo->mem.mem_type == TTM_PL_VRAM) {
522 size = bo->mem.num_pages << PAGE_SHIFT;
Ben Skeggsd961db72010-08-05 10:48:18 +1000523 offset = bo->mem.start << PAGE_SHIFT;
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200524 if ((offset + size) > rdev->mc.visible_vram_size) {
525 /* hurrah the memory is not visible ! */
526 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
527 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
528 r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
529 if (unlikely(r != 0))
530 return r;
Ben Skeggsd961db72010-08-05 10:48:18 +1000531 offset = bo->mem.start << PAGE_SHIFT;
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200532 /* this should not happen */
533 if ((offset + size) > rdev->mc.visible_vram_size)
534 return -EINVAL;
535 }
536 }
537 return 0;
Dave Airliee024e112009-06-24 09:48:08 +1000538}
Andi Kleence580fa2011-10-13 16:08:47 -0700539
Dave Airlie83f30d02011-10-27 18:15:10 +0200540int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
Andi Kleence580fa2011-10-13 16:08:47 -0700541{
542 int r;
543
544 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
545 if (unlikely(r != 0))
546 return r;
547 spin_lock(&bo->tbo.bdev->fence_lock);
548 if (mem_type)
549 *mem_type = bo->tbo.mem.mem_type;
550 if (bo->tbo.sync_obj)
Dave Airlie1717c0e2011-10-27 18:28:37 +0200551 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
Andi Kleence580fa2011-10-13 16:08:47 -0700552 spin_unlock(&bo->tbo.bdev->fence_lock);
553 ttm_bo_unreserve(&bo->tbo);
554 return r;
555}
556
557
558/**
559 * radeon_bo_reserve - reserve bo
560 * @bo: bo structure
561 * @no_wait: don't sleep while trying to reserve (return -EBUSY)
562 *
563 * Returns:
564 * -EBUSY: buffer is busy and @no_wait is true
565 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
566 * a signal. Release all buffer reservations and return to user-space.
567 */
568int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait)
569{
570 int r;
571
572 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
573 if (unlikely(r != 0)) {
574 if (r != -ERESTARTSYS)
575 dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
576 return r;
577 }
578 return 0;
579}
Jerome Glisse721604a2012-01-05 22:11:05 -0500580
581/* object have to be reserved */
582struct radeon_bo_va *radeon_bo_va(struct radeon_bo *rbo, struct radeon_vm *vm)
583{
584 struct radeon_bo_va *bo_va;
585
586 list_for_each_entry(bo_va, &rbo->va, bo_list) {
587 if (bo_va->vm == vm) {
588 return bo_va;
589 }
590 }
591 return NULL;
592}