| Zhi Wang | 28c4c6c | 2016-05-01 05:22:47 -0400 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 21 | * SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #ifndef _GVT_SCHEDULER_H_ |
| 25 | #define _GVT_SCHEDULER_H_ |
| 26 | |
| 27 | struct intel_gvt_workload_scheduler { |
| 28 | struct list_head workload_q_head[I915_NUM_ENGINES]; |
| 29 | }; |
| 30 | |
| 31 | struct intel_vgpu_workload { |
| 32 | struct intel_vgpu *vgpu; |
| 33 | int ring_id; |
| 34 | struct drm_i915_gem_request *req; |
| 35 | /* if this workload has been dispatched to i915? */ |
| 36 | bool dispatched; |
| 37 | int status; |
| 38 | |
| 39 | struct intel_vgpu_mm *shadow_mm; |
| 40 | |
| 41 | /* different submission model may need different handler */ |
| 42 | int (*prepare)(struct intel_vgpu_workload *); |
| 43 | int (*complete)(struct intel_vgpu_workload *); |
| 44 | struct list_head list; |
| 45 | |
| 46 | /* execlist context information */ |
| 47 | struct execlist_ctx_descriptor_format ctx_desc; |
| 48 | struct execlist_ring_context *ring_context; |
| 49 | unsigned long rb_head, rb_tail, rb_ctl, rb_start; |
| 50 | struct intel_vgpu_elsp_dwords elsp_dwords; |
| 51 | bool emulate_schedule_in; |
| 52 | atomic_t shadow_ctx_active; |
| 53 | wait_queue_head_t shadow_ctx_status_wq; |
| 54 | u64 ring_context_gpa; |
| 55 | }; |
| 56 | |
| 57 | #define workload_q_head(vgpu, ring_id) \ |
| 58 | (&(vgpu->workload_q_head[ring_id])) |
| 59 | |
| 60 | #define queue_workload(workload) \ |
| 61 | list_add_tail(&workload->list, \ |
| 62 | workload_q_head(workload->vgpu, workload->ring_id)) |
| 63 | |
| 64 | #endif |