blob: dae200c5fe0dd560c7a4cca663f8eb4d1547aef2 [file] [log] [blame]
Sujithf1dc5602008-10-29 10:16:30 +05301/*
Sujithcee075a2009-03-13 09:07:23 +05302 * Copyright (c) 2008-2009 Atheros Communications Inc.
Sujithf1dc5602008-10-29 10:16:30 +05303 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -070017#include "hw.h"
Felix Fietkau641d9922010-04-15 17:38:49 -040018#include "hw-ops.h"
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -040019#include "ar9002_phy.h"
Sujithf1dc5602008-10-29 10:16:30 +053020
Sujithf1dc5602008-10-29 10:16:30 +053021/* We can tune this as we go by monitoring really low values */
22#define ATH9K_NF_TOO_LOW -60
Vivek Natarajan53bc7aa2010-04-05 14:48:04 +053023#define AR9285_CLCAL_REDO_THRESH 1
Sujithf1dc5602008-10-29 10:16:30 +053024
25/* AR5416 may return very high value (like -31 dBm), in those cases the nf
26 * is incorrect and we should use the static NF value. Later we can try to
27 * find out why they are reporting these values */
28
Sujithcbe61d82009-02-09 13:27:12 +053029static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
Sujithf1dc5602008-10-29 10:16:30 +053030{
31 if (nf > ATH9K_NF_TOO_LOW) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -070032 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
33 "noise floor value detected (%d) is "
34 "lower than what we think is a "
35 "reasonable value (%d)\n",
36 nf, ATH9K_NF_TOO_LOW);
Sujithf1dc5602008-10-29 10:16:30 +053037 return false;
38 }
39 return true;
40}
41
42static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
43{
44 int16_t nfval;
45 int16_t sort[ATH9K_NF_CAL_HIST_MAX];
46 int i, j;
47
48 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
49 sort[i] = nfCalBuffer[i];
50
51 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
52 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
53 if (sort[j] > sort[j - 1]) {
54 nfval = sort[j];
55 sort[j] = sort[j - 1];
56 sort[j - 1] = nfval;
57 }
58 }
59 }
60 nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
61
62 return nfval;
63}
64
65static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
66 int16_t *nfarray)
67{
68 int i;
69
70 for (i = 0; i < NUM_NF_READINGS; i++) {
71 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
72
73 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
74 h[i].currIndex = 0;
75
76 if (h[i].invalidNFcount > 0) {
77 if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE ||
78 nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
79 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
80 } else {
81 h[i].invalidNFcount--;
82 h[i].privNF = nfarray[i];
83 }
84 } else {
85 h[i].privNF =
86 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
87 }
88 }
89 return;
90}
91
Sujithcbe61d82009-02-09 13:27:12 +053092static bool getNoiseFloorThresh(struct ath_hw *ah,
Luis R. Rodriguez76061ab2008-12-23 15:58:41 -080093 enum ieee80211_band band,
Sujithf1dc5602008-10-29 10:16:30 +053094 int16_t *nft)
95{
Luis R. Rodriguez76061ab2008-12-23 15:58:41 -080096 switch (band) {
97 case IEEE80211_BAND_5GHZ:
Sujithf74df6f2009-02-09 13:27:24 +053098 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5);
Sujithf1dc5602008-10-29 10:16:30 +053099 break;
Luis R. Rodriguez76061ab2008-12-23 15:58:41 -0800100 case IEEE80211_BAND_2GHZ:
Sujithf74df6f2009-02-09 13:27:24 +0530101 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2);
Sujithf1dc5602008-10-29 10:16:30 +0530102 break;
103 default:
Luis R. Rodriguez76061ab2008-12-23 15:58:41 -0800104 BUG_ON(1);
Sujithf1dc5602008-10-29 10:16:30 +0530105 return false;
106 }
107
108 return true;
109}
110
Sujithcbe61d82009-02-09 13:27:12 +0530111static void ath9k_hw_setup_calibration(struct ath_hw *ah,
Sujithcbfe9462009-04-13 21:56:56 +0530112 struct ath9k_cal_list *currCal)
Sujithf1dc5602008-10-29 10:16:30 +0530113{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700114 struct ath_common *common = ath9k_hw_common(ah);
115
Sujithf1dc5602008-10-29 10:16:30 +0530116 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
117 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
118 currCal->calData->calCountMax);
119
120 switch (currCal->calData->calType) {
121 case IQ_MISMATCH_CAL:
122 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700123 ath_print(common, ATH_DBG_CALIBRATE,
124 "starting IQ Mismatch Calibration\n");
Sujithf1dc5602008-10-29 10:16:30 +0530125 break;
126 case ADC_GAIN_CAL:
127 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700128 ath_print(common, ATH_DBG_CALIBRATE,
129 "starting ADC Gain Calibration\n");
Sujithf1dc5602008-10-29 10:16:30 +0530130 break;
131 case ADC_DC_CAL:
132 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700133 ath_print(common, ATH_DBG_CALIBRATE,
134 "starting ADC DC Calibration\n");
Sujithf1dc5602008-10-29 10:16:30 +0530135 break;
136 case ADC_DC_INIT_CAL:
137 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700138 ath_print(common, ATH_DBG_CALIBRATE,
139 "starting Init ADC DC Calibration\n");
Sujithf1dc5602008-10-29 10:16:30 +0530140 break;
141 }
142
143 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
144 AR_PHY_TIMING_CTRL4_DO_CAL);
145}
146
Sujithcbe61d82009-02-09 13:27:12 +0530147static void ath9k_hw_reset_calibration(struct ath_hw *ah,
Sujithcbfe9462009-04-13 21:56:56 +0530148 struct ath9k_cal_list *currCal)
Sujithf1dc5602008-10-29 10:16:30 +0530149{
Sujithf1dc5602008-10-29 10:16:30 +0530150 int i;
151
152 ath9k_hw_setup_calibration(ah, currCal);
153
154 currCal->calState = CAL_RUNNING;
155
156 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
Sujith2660b812009-02-09 13:27:26 +0530157 ah->meas0.sign[i] = 0;
158 ah->meas1.sign[i] = 0;
159 ah->meas2.sign[i] = 0;
160 ah->meas3.sign[i] = 0;
Sujithf1dc5602008-10-29 10:16:30 +0530161 }
162
Sujith2660b812009-02-09 13:27:26 +0530163 ah->cal_samples = 0;
Sujithf1dc5602008-10-29 10:16:30 +0530164}
165
Sujith379f0442009-04-13 21:56:48 +0530166static bool ath9k_hw_per_calibration(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530167 struct ath9k_channel *ichan,
168 u8 rxchainmask,
Sujithcbfe9462009-04-13 21:56:56 +0530169 struct ath9k_cal_list *currCal)
Sujithf1dc5602008-10-29 10:16:30 +0530170{
Sujith379f0442009-04-13 21:56:48 +0530171 bool iscaldone = false;
Sujithf1dc5602008-10-29 10:16:30 +0530172
173 if (currCal->calState == CAL_RUNNING) {
174 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
175 AR_PHY_TIMING_CTRL4_DO_CAL)) {
176
177 currCal->calData->calCollect(ah);
Sujith2660b812009-02-09 13:27:26 +0530178 ah->cal_samples++;
Sujithf1dc5602008-10-29 10:16:30 +0530179
Sujith2660b812009-02-09 13:27:26 +0530180 if (ah->cal_samples >= currCal->calData->calNumSamples) {
Sujithf1dc5602008-10-29 10:16:30 +0530181 int i, numChains = 0;
182 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
183 if (rxchainmask & (1 << i))
184 numChains++;
185 }
186
187 currCal->calData->calPostProc(ah, numChains);
188 ichan->CalValid |= currCal->calData->calType;
189 currCal->calState = CAL_DONE;
Sujith379f0442009-04-13 21:56:48 +0530190 iscaldone = true;
Sujithf1dc5602008-10-29 10:16:30 +0530191 } else {
192 ath9k_hw_setup_calibration(ah, currCal);
193 }
194 }
195 } else if (!(ichan->CalValid & currCal->calData->calType)) {
196 ath9k_hw_reset_calibration(ah, currCal);
197 }
Sujith379f0442009-04-13 21:56:48 +0530198
199 return iscaldone;
Sujithf1dc5602008-10-29 10:16:30 +0530200}
201
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800202/* Assumes you are talking about the currently configured channel */
Sujithcbe61d82009-02-09 13:27:12 +0530203static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
Sujithcbfe9462009-04-13 21:56:56 +0530204 enum ath9k_cal_types calType)
Sujithf1dc5602008-10-29 10:16:30 +0530205{
Luis R. Rodriguezb002a4a2009-09-13 00:03:27 -0700206 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
Sujithf1dc5602008-10-29 10:16:30 +0530207
Sujith2660b812009-02-09 13:27:26 +0530208 switch (calType & ah->supp_cals) {
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800209 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
210 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530211 case ADC_GAIN_CAL:
212 case ADC_DC_CAL:
Sujitha451aa62009-04-13 21:56:43 +0530213 if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
214 conf_is_ht20(conf)))
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800215 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530216 break;
217 }
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800218 return false;
Sujithf1dc5602008-10-29 10:16:30 +0530219}
220
Sujithcbe61d82009-02-09 13:27:12 +0530221static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530222{
Sujithf1dc5602008-10-29 10:16:30 +0530223 int i;
224
225 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
Sujith2660b812009-02-09 13:27:26 +0530226 ah->totalPowerMeasI[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530227 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
Sujith2660b812009-02-09 13:27:26 +0530228 ah->totalPowerMeasQ[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530229 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
Sujith2660b812009-02-09 13:27:26 +0530230 ah->totalIqCorrMeas[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530231 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700232 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
233 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
234 ah->cal_samples, i, ah->totalPowerMeasI[i],
235 ah->totalPowerMeasQ[i],
236 ah->totalIqCorrMeas[i]);
Sujithf1dc5602008-10-29 10:16:30 +0530237 }
238}
239
Sujithcbe61d82009-02-09 13:27:12 +0530240static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530241{
Sujithf1dc5602008-10-29 10:16:30 +0530242 int i;
243
244 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
Sujith2660b812009-02-09 13:27:26 +0530245 ah->totalAdcIOddPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530246 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
Sujith2660b812009-02-09 13:27:26 +0530247 ah->totalAdcIEvenPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530248 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
Sujith2660b812009-02-09 13:27:26 +0530249 ah->totalAdcQOddPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530250 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
Sujith2660b812009-02-09 13:27:26 +0530251 ah->totalAdcQEvenPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530252 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
253
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700254 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
255 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
256 "oddq=0x%08x; evenq=0x%08x;\n",
257 ah->cal_samples, i,
258 ah->totalAdcIOddPhase[i],
259 ah->totalAdcIEvenPhase[i],
260 ah->totalAdcQOddPhase[i],
261 ah->totalAdcQEvenPhase[i]);
Sujithf1dc5602008-10-29 10:16:30 +0530262 }
263}
264
Sujithcbe61d82009-02-09 13:27:12 +0530265static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530266{
Sujithf1dc5602008-10-29 10:16:30 +0530267 int i;
268
269 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
Sujith2660b812009-02-09 13:27:26 +0530270 ah->totalAdcDcOffsetIOddPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530271 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
Sujith2660b812009-02-09 13:27:26 +0530272 ah->totalAdcDcOffsetIEvenPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530273 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
Sujith2660b812009-02-09 13:27:26 +0530274 ah->totalAdcDcOffsetQOddPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530275 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
Sujith2660b812009-02-09 13:27:26 +0530276 ah->totalAdcDcOffsetQEvenPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530277 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
278
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700279 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
280 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
281 "oddq=0x%08x; evenq=0x%08x;\n",
282 ah->cal_samples, i,
283 ah->totalAdcDcOffsetIOddPhase[i],
284 ah->totalAdcDcOffsetIEvenPhase[i],
285 ah->totalAdcDcOffsetQOddPhase[i],
286 ah->totalAdcDcOffsetQEvenPhase[i]);
Sujithf1dc5602008-10-29 10:16:30 +0530287 }
288}
289
Sujithcbe61d82009-02-09 13:27:12 +0530290static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
Sujithf1dc5602008-10-29 10:16:30 +0530291{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700292 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530293 u32 powerMeasQ, powerMeasI, iqCorrMeas;
294 u32 qCoffDenom, iCoffDenom;
295 int32_t qCoff, iCoff;
296 int iqCorrNeg, i;
297
298 for (i = 0; i < numChains; i++) {
Sujith2660b812009-02-09 13:27:26 +0530299 powerMeasI = ah->totalPowerMeasI[i];
300 powerMeasQ = ah->totalPowerMeasQ[i];
301 iqCorrMeas = ah->totalIqCorrMeas[i];
Sujithf1dc5602008-10-29 10:16:30 +0530302
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700303 ath_print(common, ATH_DBG_CALIBRATE,
304 "Starting IQ Cal and Correction for Chain %d\n",
305 i);
Sujithf1dc5602008-10-29 10:16:30 +0530306
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700307 ath_print(common, ATH_DBG_CALIBRATE,
308 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
309 i, ah->totalIqCorrMeas[i]);
Sujithf1dc5602008-10-29 10:16:30 +0530310
311 iqCorrNeg = 0;
312
313 if (iqCorrMeas > 0x80000000) {
314 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
315 iqCorrNeg = 1;
316 }
317
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700318 ath_print(common, ATH_DBG_CALIBRATE,
319 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
320 ath_print(common, ATH_DBG_CALIBRATE,
321 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
322 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
323 iqCorrNeg);
Sujithf1dc5602008-10-29 10:16:30 +0530324
325 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
326 qCoffDenom = powerMeasQ / 64;
327
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530328 if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
329 (qCoffDenom != 0)) {
Sujithf1dc5602008-10-29 10:16:30 +0530330 iCoff = iqCorrMeas / iCoffDenom;
331 qCoff = powerMeasI / qCoffDenom - 64;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700332 ath_print(common, ATH_DBG_CALIBRATE,
333 "Chn %d iCoff = 0x%08x\n", i, iCoff);
334 ath_print(common, ATH_DBG_CALIBRATE,
335 "Chn %d qCoff = 0x%08x\n", i, qCoff);
Sujithf1dc5602008-10-29 10:16:30 +0530336
337 iCoff = iCoff & 0x3f;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700338 ath_print(common, ATH_DBG_CALIBRATE,
339 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
Sujithf1dc5602008-10-29 10:16:30 +0530340 if (iqCorrNeg == 0x0)
341 iCoff = 0x40 - iCoff;
342
343 if (qCoff > 15)
344 qCoff = 15;
345 else if (qCoff <= -16)
346 qCoff = 16;
347
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700348 ath_print(common, ATH_DBG_CALIBRATE,
349 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
350 i, iCoff, qCoff);
Sujithf1dc5602008-10-29 10:16:30 +0530351
352 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
353 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
354 iCoff);
355 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
356 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
357 qCoff);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700358 ath_print(common, ATH_DBG_CALIBRATE,
359 "IQ Cal and Correction done for Chain %d\n",
360 i);
Sujithf1dc5602008-10-29 10:16:30 +0530361 }
362 }
363
364 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
365 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
366}
367
Sujithcbe61d82009-02-09 13:27:12 +0530368static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
Sujithf1dc5602008-10-29 10:16:30 +0530369{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700370 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530371 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
372 u32 qGainMismatch, iGainMismatch, val, i;
373
374 for (i = 0; i < numChains; i++) {
Sujith2660b812009-02-09 13:27:26 +0530375 iOddMeasOffset = ah->totalAdcIOddPhase[i];
376 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
377 qOddMeasOffset = ah->totalAdcQOddPhase[i];
378 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
Sujithf1dc5602008-10-29 10:16:30 +0530379
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700380 ath_print(common, ATH_DBG_CALIBRATE,
381 "Starting ADC Gain Cal for Chain %d\n", i);
Sujithf1dc5602008-10-29 10:16:30 +0530382
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700383 ath_print(common, ATH_DBG_CALIBRATE,
384 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
385 iOddMeasOffset);
386 ath_print(common, ATH_DBG_CALIBRATE,
387 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
388 iEvenMeasOffset);
389 ath_print(common, ATH_DBG_CALIBRATE,
390 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
391 qOddMeasOffset);
392 ath_print(common, ATH_DBG_CALIBRATE,
393 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
394 qEvenMeasOffset);
Sujithf1dc5602008-10-29 10:16:30 +0530395
396 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
397 iGainMismatch =
398 ((iEvenMeasOffset * 32) /
399 iOddMeasOffset) & 0x3f;
400 qGainMismatch =
401 ((qOddMeasOffset * 32) /
402 qEvenMeasOffset) & 0x3f;
403
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700404 ath_print(common, ATH_DBG_CALIBRATE,
405 "Chn %d gain_mismatch_i = 0x%08x\n", i,
406 iGainMismatch);
407 ath_print(common, ATH_DBG_CALIBRATE,
408 "Chn %d gain_mismatch_q = 0x%08x\n", i,
409 qGainMismatch);
Sujithf1dc5602008-10-29 10:16:30 +0530410
411 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
412 val &= 0xfffff000;
413 val |= (qGainMismatch) | (iGainMismatch << 6);
414 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
415
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700416 ath_print(common, ATH_DBG_CALIBRATE,
417 "ADC Gain Cal done for Chain %d\n", i);
Sujithf1dc5602008-10-29 10:16:30 +0530418 }
419 }
420
421 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
422 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
423 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
424}
425
Sujithcbe61d82009-02-09 13:27:12 +0530426static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
Sujithf1dc5602008-10-29 10:16:30 +0530427{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700428 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530429 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
430 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
Sujithcbfe9462009-04-13 21:56:56 +0530431 const struct ath9k_percal_data *calData =
Sujith2660b812009-02-09 13:27:26 +0530432 ah->cal_list_curr->calData;
Sujithf1dc5602008-10-29 10:16:30 +0530433 u32 numSamples =
434 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
435
436 for (i = 0; i < numChains; i++) {
Sujith2660b812009-02-09 13:27:26 +0530437 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
438 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
439 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
440 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
Sujithf1dc5602008-10-29 10:16:30 +0530441
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700442 ath_print(common, ATH_DBG_CALIBRATE,
443 "Starting ADC DC Offset Cal for Chain %d\n", i);
Sujithf1dc5602008-10-29 10:16:30 +0530444
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700445 ath_print(common, ATH_DBG_CALIBRATE,
446 "Chn %d pwr_meas_odd_i = %d\n", i,
447 iOddMeasOffset);
448 ath_print(common, ATH_DBG_CALIBRATE,
449 "Chn %d pwr_meas_even_i = %d\n", i,
450 iEvenMeasOffset);
451 ath_print(common, ATH_DBG_CALIBRATE,
452 "Chn %d pwr_meas_odd_q = %d\n", i,
453 qOddMeasOffset);
454 ath_print(common, ATH_DBG_CALIBRATE,
455 "Chn %d pwr_meas_even_q = %d\n", i,
456 qEvenMeasOffset);
Sujithf1dc5602008-10-29 10:16:30 +0530457
458 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
459 numSamples) & 0x1ff;
460 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
461 numSamples) & 0x1ff;
462
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700463 ath_print(common, ATH_DBG_CALIBRATE,
464 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
465 iDcMismatch);
466 ath_print(common, ATH_DBG_CALIBRATE,
467 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
468 qDcMismatch);
Sujithf1dc5602008-10-29 10:16:30 +0530469
470 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
471 val &= 0xc0000fff;
472 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
473 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
474
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700475 ath_print(common, ATH_DBG_CALIBRATE,
476 "ADC DC Offset Cal done for Chain %d\n", i);
Sujithf1dc5602008-10-29 10:16:30 +0530477 }
478
479 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
480 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
481 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
482}
483
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800484/* This is done for the currently configured channel */
Sujithcbe61d82009-02-09 13:27:12 +0530485bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530486{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700487 struct ath_common *common = ath9k_hw_common(ah);
488 struct ieee80211_conf *conf = &common->hw->conf;
Sujithcbfe9462009-04-13 21:56:56 +0530489 struct ath9k_cal_list *currCal = ah->cal_list_curr;
Sujithf1dc5602008-10-29 10:16:30 +0530490
Sujith2660b812009-02-09 13:27:26 +0530491 if (!ah->curchan)
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800492 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530493
494 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800495 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530496
497 if (currCal == NULL)
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800498 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530499
500 if (currCal->calState != CAL_DONE) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700501 ath_print(common, ATH_DBG_CALIBRATE,
502 "Calibration state incorrect, %d\n",
503 currCal->calState);
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800504 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530505 }
506
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800507 if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
508 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530509
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700510 ath_print(common, ATH_DBG_CALIBRATE,
511 "Resetting Cal %d state for channel %u\n",
512 currCal->calData->calType, conf->channel->center_freq);
Sujithf1dc5602008-10-29 10:16:30 +0530513
Sujith2660b812009-02-09 13:27:26 +0530514 ah->curchan->CalValid &= ~currCal->calData->calType;
Sujithf1dc5602008-10-29 10:16:30 +0530515 currCal->calState = CAL_WAITING;
516
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800517 return false;
Sujithf1dc5602008-10-29 10:16:30 +0530518}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400519EXPORT_SYMBOL(ath9k_hw_reset_calvalid);
Sujithf1dc5602008-10-29 10:16:30 +0530520
Sujithcbe61d82009-02-09 13:27:12 +0530521void ath9k_hw_start_nfcal(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530522{
523 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
524 AR_PHY_AGC_CONTROL_ENABLE_NF);
525 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
526 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
527 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
528}
529
Sujithcbe61d82009-02-09 13:27:12 +0530530void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +0530531{
532 struct ath9k_nfcal_hist *h;
533 int i, j;
534 int32_t val;
535 const u32 ar5416_cca_regs[6] = {
536 AR_PHY_CCA,
537 AR_PHY_CH1_CCA,
538 AR_PHY_CH2_CCA,
539 AR_PHY_EXT_CCA,
540 AR_PHY_CH1_EXT_CCA,
541 AR_PHY_CH2_EXT_CCA
542 };
Senthil Balasubramaniance143bb2009-09-17 09:27:33 +0530543 u8 chainmask, rx_chain_status;
Sujithf1dc5602008-10-29 10:16:30 +0530544
Senthil Balasubramaniance143bb2009-09-17 09:27:33 +0530545 rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
Sujith6398dc02010-03-17 14:25:19 +0530546 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
Sujith5dad40c2009-01-23 11:20:55 +0530547 chainmask = 0x9;
Senthil Balasubramaniance143bb2009-09-17 09:27:33 +0530548 else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
549 if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
550 chainmask = 0x1B;
551 else
552 chainmask = 0x09;
553 } else {
554 if (rx_chain_status & 0x4)
555 chainmask = 0x3F;
556 else if (rx_chain_status & 0x2)
557 chainmask = 0x1B;
558 else
559 chainmask = 0x09;
560 }
Sujithf1dc5602008-10-29 10:16:30 +0530561
Sujithf1dc5602008-10-29 10:16:30 +0530562 h = ah->nfCalHist;
Sujithf1dc5602008-10-29 10:16:30 +0530563
564 for (i = 0; i < NUM_NF_READINGS; i++) {
565 if (chainmask & (1 << i)) {
566 val = REG_READ(ah, ar5416_cca_regs[i]);
567 val &= 0xFFFFFE00;
568 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
569 REG_WRITE(ah, ar5416_cca_regs[i], val);
570 }
571 }
572
573 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
574 AR_PHY_AGC_CONTROL_ENABLE_NF);
575 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
576 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
577 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
578
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +0530579 for (j = 0; j < 5; j++) {
Sujithf1dc5602008-10-29 10:16:30 +0530580 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
581 AR_PHY_AGC_CONTROL_NF) == 0)
582 break;
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +0530583 udelay(50);
Sujithf1dc5602008-10-29 10:16:30 +0530584 }
585
586 for (i = 0; i < NUM_NF_READINGS; i++) {
587 if (chainmask & (1 << i)) {
588 val = REG_READ(ah, ar5416_cca_regs[i]);
589 val &= 0xFFFFFE00;
590 val |= (((u32) (-50) << 1) & 0x1ff);
591 REG_WRITE(ah, ar5416_cca_regs[i], val);
592 }
593 }
594}
595
Sujithcbe61d82009-02-09 13:27:12 +0530596int16_t ath9k_hw_getnf(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530597 struct ath9k_channel *chan)
598{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700599 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530600 int16_t nf, nfThresh;
601 int16_t nfarray[NUM_NF_READINGS] = { 0 };
602 struct ath9k_nfcal_hist *h;
Luis R. Rodriguez76061ab2008-12-23 15:58:41 -0800603 struct ieee80211_channel *c = chan->chan;
Sujithf1dc5602008-10-29 10:16:30 +0530604
605 chan->channelFlags &= (~CHANNEL_CW_INT);
606 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700607 ath_print(common, ATH_DBG_CALIBRATE,
608 "NF did not complete in calibration window\n");
Sujithf1dc5602008-10-29 10:16:30 +0530609 nf = 0;
610 chan->rawNoiseFloor = nf;
611 return chan->rawNoiseFloor;
612 } else {
613 ath9k_hw_do_getnf(ah, nfarray);
614 nf = nfarray[0];
Luis R. Rodriguez76061ab2008-12-23 15:58:41 -0800615 if (getNoiseFloorThresh(ah, c->band, &nfThresh)
Sujithf1dc5602008-10-29 10:16:30 +0530616 && nf > nfThresh) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700617 ath_print(common, ATH_DBG_CALIBRATE,
618 "noise floor failed detected; "
619 "detected %d, threshold %d\n",
620 nf, nfThresh);
Sujithf1dc5602008-10-29 10:16:30 +0530621 chan->channelFlags |= CHANNEL_CW_INT;
622 }
623 }
624
Sujithf1dc5602008-10-29 10:16:30 +0530625 h = ah->nfCalHist;
Sujithf1dc5602008-10-29 10:16:30 +0530626
627 ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
628 chan->rawNoiseFloor = h[0].privNF;
629
630 return chan->rawNoiseFloor;
631}
632
Sujithcbe61d82009-02-09 13:27:12 +0530633void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530634{
635 int i, j;
Senthil Balasubramaniana59b5a52009-07-14 20:17:07 -0400636 s16 noise_floor;
637
638 if (AR_SREV_9280(ah))
639 noise_floor = AR_PHY_CCA_MAX_AR9280_GOOD_VALUE;
Sujith6398dc02010-03-17 14:25:19 +0530640 else if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
Senthil Balasubramaniana59b5a52009-07-14 20:17:07 -0400641 noise_floor = AR_PHY_CCA_MAX_AR9285_GOOD_VALUE;
Vivek Natarajan6170cd52009-09-17 09:24:24 +0530642 else if (AR_SREV_9287(ah))
643 noise_floor = AR_PHY_CCA_MAX_AR9287_GOOD_VALUE;
Senthil Balasubramaniana59b5a52009-07-14 20:17:07 -0400644 else
645 noise_floor = AR_PHY_CCA_MAX_AR5416_GOOD_VALUE;
Sujithf1dc5602008-10-29 10:16:30 +0530646
647 for (i = 0; i < NUM_NF_READINGS; i++) {
648 ah->nfCalHist[i].currIndex = 0;
Senthil Balasubramaniana59b5a52009-07-14 20:17:07 -0400649 ah->nfCalHist[i].privNF = noise_floor;
Sujithf1dc5602008-10-29 10:16:30 +0530650 ah->nfCalHist[i].invalidNFcount =
651 AR_PHY_CCA_FILTERWINDOW_LENGTH;
652 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
Senthil Balasubramaniana59b5a52009-07-14 20:17:07 -0400653 ah->nfCalHist[i].nfCalBuffer[j] = noise_floor;
Sujithf1dc5602008-10-29 10:16:30 +0530654 }
655 }
Sujithf1dc5602008-10-29 10:16:30 +0530656}
657
Sujithcbe61d82009-02-09 13:27:12 +0530658s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +0530659{
Sujithf1dc5602008-10-29 10:16:30 +0530660 s16 nf;
661
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -0800662 if (chan->rawNoiseFloor == 0)
Luis R. Rodrigueze56db712008-12-23 15:58:47 -0800663 nf = -96;
664 else
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -0800665 nf = chan->rawNoiseFloor;
Sujithf1dc5602008-10-29 10:16:30 +0530666
667 if (!ath9k_hw_nf_in_range(ah, nf))
668 nf = ATH_DEFAULT_NOISE_FLOOR;
669
670 return nf;
671}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400672EXPORT_SYMBOL(ath9k_hw_getchan_noise);
Sujithf1dc5602008-10-29 10:16:30 +0530673
Luis R. Rodriguezbecdbc542010-04-15 17:38:53 -0400674static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530675{
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530676 u32 rddata;
677 int32_t delta, currPDADC, slope;
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530678
679 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530680 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
681
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530682 if (ah->initPDADC == 0 || currPDADC == 0) {
683 /*
684 * Zero value indicates that no frames have been transmitted yet,
685 * can't do temperature compensation until frames are transmitted.
686 */
687 return;
688 } else {
689 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
690
691 if (slope == 0) { /* to avoid divide by zero case */
692 delta = 0;
693 } else {
694 delta = ((currPDADC - ah->initPDADC)*4) / slope;
695 }
696 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
697 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
698 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
699 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
700 }
701}
702
Luis R. Rodriguez2b5facf2010-04-15 17:38:55 -0400703static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530704{
705 u32 rddata, i;
706 int delta, currPDADC, regval;
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530707
Luis R. Rodriguez2b5facf2010-04-15 17:38:55 -0400708 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
709 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530710
Luis R. Rodriguez2b5facf2010-04-15 17:38:55 -0400711 if (ah->initPDADC == 0 || currPDADC == 0)
712 return;
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530713
Luis R. Rodriguez2b5facf2010-04-15 17:38:55 -0400714 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
715 delta = (currPDADC - ah->initPDADC + 4) / 8;
716 else
717 delta = (currPDADC - ah->initPDADC + 5) / 10;
Vivek Natarajandb91f2e2009-08-14 11:27:16 +0530718
Luis R. Rodriguez2b5facf2010-04-15 17:38:55 -0400719 if (delta != ah->PDADCdelta) {
720 ah->PDADCdelta = delta;
721 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
722 regval = ah->originalGain[i] - delta;
723 if (regval < 0)
724 regval = 0;
Luis R. Rodriguez80b99932010-04-15 17:38:54 -0400725
Luis R. Rodriguez2b5facf2010-04-15 17:38:55 -0400726 REG_RMW_FIELD(ah,
727 AR_PHY_TX_GAIN_TBL1 + i * 4,
728 AR_PHY_TX_GAIN, regval);
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530729 }
730 }
731}
732
Luis R. Rodriguez2b5facf2010-04-15 17:38:55 -0400733static void ath9k_olc_temp_compensation(struct ath_hw *ah)
734{
735 if (OLC_FOR_AR9287_10_LATER)
736 ar9287_hw_olc_temp_compensation(ah);
737 else
738 ar9280_hw_olc_temp_compensation(ah);
739}
740
Luis R. Rodriguez62268112009-10-07 16:22:19 -0400741static void ath9k_hw_9271_pa_cal(struct ath_hw *ah, bool is_reset)
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400742{
743 u32 regVal;
744 unsigned int i;
745 u32 regList [][2] = {
746 { 0x786c, 0 },
747 { 0x7854, 0 },
748 { 0x7820, 0 },
749 { 0x7824, 0 },
750 { 0x7868, 0 },
751 { 0x783c, 0 },
752 { 0x7838, 0 } ,
753 { 0x7828, 0 } ,
754 };
755
756 for (i = 0; i < ARRAY_SIZE(regList); i++)
757 regList[i][1] = REG_READ(ah, regList[i][0]);
758
759 regVal = REG_READ(ah, 0x7834);
760 regVal &= (~(0x1));
761 REG_WRITE(ah, 0x7834, regVal);
762 regVal = REG_READ(ah, 0x9808);
763 regVal |= (0x1 << 27);
764 REG_WRITE(ah, 0x9808, regVal);
765
766 /* 786c,b23,1, pwddac=1 */
767 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
768 /* 7854, b5,1, pdrxtxbb=1 */
769 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
770 /* 7854, b7,1, pdv2i=1 */
771 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
772 /* 7854, b8,1, pddacinterface=1 */
773 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
774 /* 7824,b12,0, offcal=0 */
775 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
776 /* 7838, b1,0, pwddb=0 */
777 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
778 /* 7820,b11,0, enpacal=0 */
779 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
780 /* 7820,b25,1, pdpadrv1=0 */
781 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
782 /* 7820,b24,0, pdpadrv2=0 */
783 REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
784 /* 7820,b23,0, pdpaout=0 */
785 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
786 /* 783c,b14-16,7, padrvgn2tab_0=7 */
787 REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
788 /*
789 * 7838,b29-31,0, padrvgn1tab_0=0
790 * does not matter since we turn it off
791 */
792 REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
793
794 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
795
796 /* Set:
797 * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
798 * txon=1,paon=1,oscon=1,synthon_force=1
799 */
800 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
801 udelay(30);
802 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
803
804 /* find off_6_1; */
Luis R. Rodriguez1d9c1852009-10-27 12:59:37 -0400805 for (i = 6; i > 0; i--) {
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400806 regVal = REG_READ(ah, 0x7834);
807 regVal |= (1 << (20 + i));
808 REG_WRITE(ah, 0x7834, regVal);
809 udelay(1);
810 //regVal = REG_READ(ah, 0x7834);
811 regVal &= (~(0x1 << (20 + i)));
812 regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
813 << (20 + i));
814 REG_WRITE(ah, 0x7834, regVal);
815 }
816
Luis R. Rodriguez62268112009-10-07 16:22:19 -0400817 regVal = (regVal >>20) & 0x7f;
818
819 /* Update PA cal info */
820 if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
821 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
822 ah->pacal_info.max_skipcount =
823 2 * ah->pacal_info.max_skipcount;
824 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
825 } else {
826 ah->pacal_info.max_skipcount = 1;
827 ah->pacal_info.skipcount = 0;
828 ah->pacal_info.prev_offset = regVal;
829 }
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400830
831 regVal = REG_READ(ah, 0x7834);
832 regVal |= 0x1;
833 REG_WRITE(ah, 0x7834, regVal);
834 regVal = REG_READ(ah, 0x9808);
835 regVal &= (~(0x1 << 27));
836 REG_WRITE(ah, 0x9808, regVal);
837
838 for (i = 0; i < ARRAY_SIZE(regList); i++)
839 REG_WRITE(ah, regList[i][0], regList[i][1]);
840}
841
Sujitha13883b2009-08-26 08:39:40 +0530842static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530843{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700844 struct ath_common *common = ath9k_hw_common(ah);
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530845 u32 regVal;
846 int i, offset, offs_6_1, offs_0;
847 u32 ccomp_org, reg_field;
848 u32 regList[][2] = {
849 { 0x786c, 0 },
850 { 0x7854, 0 },
851 { 0x7820, 0 },
852 { 0x7824, 0 },
853 { 0x7868, 0 },
854 { 0x783c, 0 },
855 { 0x7838, 0 },
856 };
857
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700858 ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
Sujitha13883b2009-08-26 08:39:40 +0530859
Sujith20caf0d2009-08-26 08:39:52 +0530860 /* PA CAL is not needed for high power solution */
861 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
862 AR5416_EEP_TXGAIN_HIGH_POWER)
863 return;
864
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530865 if (AR_SREV_9285_11(ah)) {
866 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
867 udelay(10);
868 }
869
870 for (i = 0; i < ARRAY_SIZE(regList); i++)
871 regList[i][1] = REG_READ(ah, regList[i][0]);
872
873 regVal = REG_READ(ah, 0x7834);
874 regVal &= (~(0x1));
875 REG_WRITE(ah, 0x7834, regVal);
876 regVal = REG_READ(ah, 0x9808);
877 regVal |= (0x1 << 27);
878 REG_WRITE(ah, 0x9808, regVal);
879
880 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
881 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
882 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
883 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
884 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
885 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
886 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
Sujith0abb0962009-08-26 08:39:50 +0530887 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530888 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
889 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
890 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
891 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
892 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
Sujith0abb0962009-08-26 08:39:50 +0530893 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530894
895 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
896 udelay(30);
897 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
898 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
899
900 for (i = 6; i > 0; i--) {
901 regVal = REG_READ(ah, 0x7834);
902 regVal |= (1 << (19 + i));
903 REG_WRITE(ah, 0x7834, regVal);
904 udelay(1);
Sujithedbf51f2009-09-17 09:28:41 +0530905 regVal = REG_READ(ah, 0x7834);
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530906 regVal &= (~(0x1 << (19 + i)));
907 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
908 regVal |= (reg_field << (19 + i));
909 REG_WRITE(ah, 0x7834, regVal);
910 }
911
912 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
913 udelay(1);
914 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
915 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
916 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
917 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
918
919 offset = (offs_6_1<<1) | offs_0;
920 offset = offset - 0;
921 offs_6_1 = offset>>1;
922 offs_0 = offset & 1;
923
Sujitha13883b2009-08-26 08:39:40 +0530924 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
925 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
926 ah->pacal_info.max_skipcount =
927 2 * ah->pacal_info.max_skipcount;
928 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
929 } else {
930 ah->pacal_info.max_skipcount = 1;
931 ah->pacal_info.skipcount = 0;
932 ah->pacal_info.prev_offset = offset;
933 }
934
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530935 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
936 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
937
938 regVal = REG_READ(ah, 0x7834);
939 regVal |= 0x1;
940 REG_WRITE(ah, 0x7834, regVal);
941 regVal = REG_READ(ah, 0x9808);
942 regVal &= (~(0x1 << 27));
943 REG_WRITE(ah, 0x9808, regVal);
944
945 for (i = 0; i < ARRAY_SIZE(regList); i++)
946 REG_WRITE(ah, regList[i][0], regList[i][1]);
947
948 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
949
950 if (AR_SREV_9285_11(ah))
951 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
952
953}
954
Luis R. Rodriguez4d001d12010-04-15 17:38:51 -0400955static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
956{
957 if (AR_SREV_9271(ah)) {
958 if (is_reset || !ah->pacal_info.skipcount)
959 ath9k_hw_9271_pa_cal(ah, is_reset);
960 else
961 ah->pacal_info.skipcount--;
962 } else if (AR_SREV_9285_11_OR_LATER(ah)) {
963 if (is_reset || !ah->pacal_info.skipcount)
964 ath9k_hw_9285_pa_cal(ah, is_reset);
965 else
966 ah->pacal_info.skipcount--;
967 }
968}
969
Luis R. Rodrigueze83a1132010-04-15 17:38:52 -0400970static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
971{
972 if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER)
973 ath9k_olc_temp_compensation(ah);
974}
975
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530976bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
Sujith379f0442009-04-13 21:56:48 +0530977 u8 rxchainmask, bool longcal)
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530978{
Sujith379f0442009-04-13 21:56:48 +0530979 bool iscaldone = true;
Sujithcbfe9462009-04-13 21:56:56 +0530980 struct ath9k_cal_list *currCal = ah->cal_list_curr;
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530981
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530982 if (currCal &&
983 (currCal->calState == CAL_RUNNING ||
984 currCal->calState == CAL_WAITING)) {
Sujith379f0442009-04-13 21:56:48 +0530985 iscaldone = ath9k_hw_per_calibration(ah, chan,
986 rxchainmask, currCal);
987 if (iscaldone) {
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530988 ah->cal_list_curr = currCal = currCal->calNext;
989
990 if (currCal->calState == CAL_WAITING) {
Sujith379f0442009-04-13 21:56:48 +0530991 iscaldone = false;
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530992 ath9k_hw_reset_calibration(ah, currCal);
993 }
994 }
995 }
996
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400997 /* Do NF cal only at longer intervals */
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530998 if (longcal) {
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400999 /* Do periodic PAOffset Cal */
Luis R. Rodriguez4d001d12010-04-15 17:38:51 -04001000 ar9002_hw_pa_cal(ah, false);
Luis R. Rodrigueze83a1132010-04-15 17:38:52 -04001001 ar9002_hw_olc_temp_compensation(ah);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001002
1003 /* Get the value from the previous NF cal and update history buffer */
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301004 ath9k_hw_getnf(ah, chan);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001005
1006 /*
1007 * Load the NF from history buffer of the current channel.
1008 * NF is slow time-variant, so it is OK to use a historical value.
1009 */
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301010 ath9k_hw_loadnf(ah, ah->curchan);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001011
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301012 ath9k_hw_start_nfcal(ah);
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301013 }
1014
Sujith379f0442009-04-13 21:56:48 +05301015 return iscaldone;
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301016}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04001017EXPORT_SYMBOL(ath9k_hw_calibrate);
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301018
Luis R. Rodriguezb57df122009-10-07 16:22:18 -04001019/* Carrier leakage Calibration fix */
Vivek Natarajan53bc7aa2010-04-05 14:48:04 +05301020static bool ar9285_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301021{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001022 struct ath_common *common = ath9k_hw_common(ah);
1023
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301024 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
Sujithdb2f63f2009-04-13 21:56:41 +05301025 if (IS_CHAN_HT20(chan)) {
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301026 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
1027 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
1028 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1029 AR_PHY_AGC_CONTROL_FLTR_CAL);
1030 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
1031 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1032 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1033 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001034 ath_print(common, ATH_DBG_CALIBRATE, "offset "
1035 "calibration failed to complete in "
1036 "1ms; noisy ??\n");
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301037 return false;
1038 }
1039 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
1040 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
1041 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1042 }
1043 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
1044 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
1045 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
1046 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1047 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1048 0, AH_WAIT_TIMEOUT)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001049 ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
1050 "failed to complete in 1ms; noisy ??\n");
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301051 return false;
1052 }
1053
1054 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
1055 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1056 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
1057
1058 return true;
1059}
1060
Vivek Natarajan53bc7aa2010-04-05 14:48:04 +05301061static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1062{
1063 int i;
1064 u_int32_t txgain_max;
1065 u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
1066 u_int32_t reg_clc_I0, reg_clc_Q0;
1067 u_int32_t i0_num = 0;
1068 u_int32_t q0_num = 0;
1069 u_int32_t total_num = 0;
1070 u_int32_t reg_rf2g5_org;
1071 bool retv = true;
1072
1073 if (!(ar9285_cl_cal(ah, chan)))
1074 return false;
1075
1076 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
1077 AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
1078
1079 for (i = 0; i < (txgain_max+1); i++) {
1080 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
1081 AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
1082 if (!(gain_mask & (1 << clc_gain))) {
1083 gain_mask |= (1 << clc_gain);
1084 clc_num++;
1085 }
1086 }
1087
1088 for (i = 0; i < clc_num; i++) {
1089 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
1090 & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
1091 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
1092 & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
1093 if (reg_clc_I0 == 0)
1094 i0_num++;
1095
1096 if (reg_clc_Q0 == 0)
1097 q0_num++;
1098 }
1099 total_num = i0_num + q0_num;
1100 if (total_num > AR9285_CLCAL_REDO_THRESH) {
1101 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
1102 if (AR_SREV_9285E_20(ah)) {
1103 REG_WRITE(ah, AR9285_RF2G5,
1104 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
1105 AR9285_RF2G5_IC50TX_XE_SET);
1106 } else {
1107 REG_WRITE(ah, AR9285_RF2G5,
1108 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
1109 AR9285_RF2G5_IC50TX_SET);
1110 }
1111 retv = ar9285_cl_cal(ah, chan);
1112 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
1113 }
1114 return retv;
1115}
1116
Sujith04d19dd2009-04-13 21:56:59 +05301117bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05301118{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001119 struct ath_common *common = ath9k_hw_common(ah);
1120
Luis R. Rodriguezb57df122009-10-07 16:22:18 -04001121 if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301122 if (!ar9285_clc(ah, chan))
1123 return false;
Sujith04d19dd2009-04-13 21:56:59 +05301124 } else {
1125 if (AR_SREV_9280_10_OR_LATER(ah)) {
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05301126 if (!AR_SREV_9287_10_OR_LATER(ah))
1127 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
1128 AR_PHY_ADC_CTL_OFF_PWDADC);
1129 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1130 AR_PHY_AGC_CONTROL_FLTR_CAL);
Sujith04d19dd2009-04-13 21:56:59 +05301131 }
Sujithedf7c062009-02-12 10:06:49 +05301132
Sujith04d19dd2009-04-13 21:56:59 +05301133 /* Calibrate the AGC */
Sujithedf7c062009-02-12 10:06:49 +05301134 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
Sujith04d19dd2009-04-13 21:56:59 +05301135 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1136 AR_PHY_AGC_CONTROL_CAL);
Sujithedf7c062009-02-12 10:06:49 +05301137
Sujith04d19dd2009-04-13 21:56:59 +05301138 /* Poll for offset calibration complete */
1139 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1140 0, AH_WAIT_TIMEOUT)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001141 ath_print(common, ATH_DBG_CALIBRATE,
1142 "offset calibration failed to "
1143 "complete in 1ms; noisy environment?\n");
Sujithedf7c062009-02-12 10:06:49 +05301144 return false;
1145 }
1146
Sujith04d19dd2009-04-13 21:56:59 +05301147 if (AR_SREV_9280_10_OR_LATER(ah)) {
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05301148 if (!AR_SREV_9287_10_OR_LATER(ah))
1149 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
1150 AR_PHY_ADC_CTL_OFF_PWDADC);
1151 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1152 AR_PHY_AGC_CONTROL_FLTR_CAL);
Sujith04d19dd2009-04-13 21:56:59 +05301153 }
Sujithedf7c062009-02-12 10:06:49 +05301154 }
1155
1156 /* Do PA Calibration */
Luis R. Rodriguez4d001d12010-04-15 17:38:51 -04001157 ar9002_hw_pa_cal(ah, true);
Senthil Balasubramaniane7594072008-12-08 19:43:48 +05301158
Sujith04d19dd2009-04-13 21:56:59 +05301159 /* Do NF Calibration after DC offset and other calibrations */
Sujithf1dc5602008-10-29 10:16:30 +05301160 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
Sujith04d19dd2009-04-13 21:56:59 +05301161 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
Sujithf1dc5602008-10-29 10:16:30 +05301162
Sujith2660b812009-02-09 13:27:26 +05301163 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
Sujithf1dc5602008-10-29 10:16:30 +05301164
Sujith04d19dd2009-04-13 21:56:59 +05301165 /* Enable IQ, ADC Gain and ADC DC offset CALs */
Sujithf1dc5602008-10-29 10:16:30 +05301166 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -08001167 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
Sujith2660b812009-02-09 13:27:26 +05301168 INIT_CAL(&ah->adcgain_caldata);
1169 INSERT_CAL(ah, &ah->adcgain_caldata);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001170 ath_print(common, ATH_DBG_CALIBRATE,
1171 "enabling ADC Gain Calibration.\n");
Sujithf1dc5602008-10-29 10:16:30 +05301172 }
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -08001173 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
Sujith2660b812009-02-09 13:27:26 +05301174 INIT_CAL(&ah->adcdc_caldata);
1175 INSERT_CAL(ah, &ah->adcdc_caldata);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001176 ath_print(common, ATH_DBG_CALIBRATE,
1177 "enabling ADC DC Calibration.\n");
Sujithf1dc5602008-10-29 10:16:30 +05301178 }
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -08001179 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
Sujith2660b812009-02-09 13:27:26 +05301180 INIT_CAL(&ah->iq_caldata);
1181 INSERT_CAL(ah, &ah->iq_caldata);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001182 ath_print(common, ATH_DBG_CALIBRATE,
1183 "enabling IQ Calibration.\n");
Sujithf1dc5602008-10-29 10:16:30 +05301184 }
1185
Sujith2660b812009-02-09 13:27:26 +05301186 ah->cal_list_curr = ah->cal_list;
Sujithf1dc5602008-10-29 10:16:30 +05301187
Sujith2660b812009-02-09 13:27:26 +05301188 if (ah->cal_list_curr)
1189 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
Sujithf1dc5602008-10-29 10:16:30 +05301190 }
1191
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001192 chan->CalValid = 0;
Sujithf1dc5602008-10-29 10:16:30 +05301193
1194 return true;
1195}
1196
Sujithcbfe9462009-04-13 21:56:56 +05301197const struct ath9k_percal_data iq_cal_multi_sample = {
Sujithf1dc5602008-10-29 10:16:30 +05301198 IQ_MISMATCH_CAL,
1199 MAX_CAL_SAMPLES,
1200 PER_MIN_LOG_COUNT,
1201 ath9k_hw_iqcal_collect,
1202 ath9k_hw_iqcalibrate
1203};
Sujithcbfe9462009-04-13 21:56:56 +05301204const struct ath9k_percal_data iq_cal_single_sample = {
Sujithf1dc5602008-10-29 10:16:30 +05301205 IQ_MISMATCH_CAL,
1206 MIN_CAL_SAMPLES,
1207 PER_MAX_LOG_COUNT,
1208 ath9k_hw_iqcal_collect,
1209 ath9k_hw_iqcalibrate
1210};
Sujithcbfe9462009-04-13 21:56:56 +05301211const struct ath9k_percal_data adc_gain_cal_multi_sample = {
Sujithf1dc5602008-10-29 10:16:30 +05301212 ADC_GAIN_CAL,
1213 MAX_CAL_SAMPLES,
1214 PER_MIN_LOG_COUNT,
1215 ath9k_hw_adc_gaincal_collect,
1216 ath9k_hw_adc_gaincal_calibrate
1217};
Sujithcbfe9462009-04-13 21:56:56 +05301218const struct ath9k_percal_data adc_gain_cal_single_sample = {
Sujithf1dc5602008-10-29 10:16:30 +05301219 ADC_GAIN_CAL,
1220 MIN_CAL_SAMPLES,
1221 PER_MAX_LOG_COUNT,
1222 ath9k_hw_adc_gaincal_collect,
1223 ath9k_hw_adc_gaincal_calibrate
1224};
Sujithcbfe9462009-04-13 21:56:56 +05301225const struct ath9k_percal_data adc_dc_cal_multi_sample = {
Sujithf1dc5602008-10-29 10:16:30 +05301226 ADC_DC_CAL,
1227 MAX_CAL_SAMPLES,
1228 PER_MIN_LOG_COUNT,
1229 ath9k_hw_adc_dccal_collect,
1230 ath9k_hw_adc_dccal_calibrate
1231};
Sujithcbfe9462009-04-13 21:56:56 +05301232const struct ath9k_percal_data adc_dc_cal_single_sample = {
Sujithf1dc5602008-10-29 10:16:30 +05301233 ADC_DC_CAL,
1234 MIN_CAL_SAMPLES,
1235 PER_MAX_LOG_COUNT,
1236 ath9k_hw_adc_dccal_collect,
1237 ath9k_hw_adc_dccal_calibrate
1238};
Sujithcbfe9462009-04-13 21:56:56 +05301239const struct ath9k_percal_data adc_init_dc_cal = {
Sujithf1dc5602008-10-29 10:16:30 +05301240 ADC_DC_INIT_CAL,
1241 MIN_CAL_SAMPLES,
1242 INIT_LOG_COUNT,
1243 ath9k_hw_adc_dccal_collect,
1244 ath9k_hw_adc_dccal_calibrate
1245};