blob: f2e073af5dd258742482bc458d2cc7bd3412c2de [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the names of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * Alternatively, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") version 2 as published by the Free
20 * Software Foundation.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/types.h>
Ido Schimmeldd6cb0f2016-04-06 17:10:01 +020037#include <linux/dcbnl.h>
Ido Schimmelff6551e2016-04-06 17:10:03 +020038#include <linux/if_ether.h>
Jiri Pirko2d0ed392016-04-14 18:19:30 +020039#include <linux/list.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020040
41#include "spectrum.h"
42#include "core.h"
43#include "port.h"
44#include "reg.h"
45
Jiri Pirko078f9c72016-04-14 18:19:19 +020046static struct mlxsw_sp_sb_pr *mlxsw_sp_sb_pr_get(struct mlxsw_sp *mlxsw_sp,
47 u8 pool,
48 enum mlxsw_reg_sbxx_dir dir)
49{
50 return &mlxsw_sp->sb.prs[dir][pool];
51}
52
53static struct mlxsw_sp_sb_cm *mlxsw_sp_sb_cm_get(struct mlxsw_sp *mlxsw_sp,
54 u8 local_port, u8 pg_buff,
55 enum mlxsw_reg_sbxx_dir dir)
56{
57 return &mlxsw_sp->sb.ports[local_port].cms[dir][pg_buff];
58}
59
60static struct mlxsw_sp_sb_pm *mlxsw_sp_sb_pm_get(struct mlxsw_sp *mlxsw_sp,
61 u8 local_port, u8 pool,
62 enum mlxsw_reg_sbxx_dir dir)
63{
64 return &mlxsw_sp->sb.ports[local_port].pms[dir][pool];
65}
66
Jiri Pirko94266e32016-04-14 18:19:16 +020067static int mlxsw_sp_sb_pr_write(struct mlxsw_sp *mlxsw_sp, u8 pool,
68 enum mlxsw_reg_sbxx_dir dir,
69 enum mlxsw_reg_sbpr_mode mode, u32 size)
70{
71 char sbpr_pl[MLXSW_REG_SBPR_LEN];
Jiri Pirko078f9c72016-04-14 18:19:19 +020072 struct mlxsw_sp_sb_pr *pr;
73 int err;
Jiri Pirko94266e32016-04-14 18:19:16 +020074
75 mlxsw_reg_sbpr_pack(sbpr_pl, pool, dir, mode, size);
Jiri Pirko078f9c72016-04-14 18:19:19 +020076 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpr), sbpr_pl);
77 if (err)
78 return err;
79
80 pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool, dir);
81 pr->mode = mode;
82 pr->size = size;
83 return 0;
Jiri Pirko94266e32016-04-14 18:19:16 +020084}
85
86static int mlxsw_sp_sb_cm_write(struct mlxsw_sp *mlxsw_sp, u8 local_port,
87 u8 pg_buff, enum mlxsw_reg_sbxx_dir dir,
88 u32 min_buff, u32 max_buff, u8 pool)
89{
90 char sbcm_pl[MLXSW_REG_SBCM_LEN];
Jiri Pirko078f9c72016-04-14 18:19:19 +020091 int err;
Jiri Pirko94266e32016-04-14 18:19:16 +020092
93 mlxsw_reg_sbcm_pack(sbcm_pl, local_port, pg_buff, dir,
94 min_buff, max_buff, pool);
Jiri Pirko078f9c72016-04-14 18:19:19 +020095 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbcm), sbcm_pl);
96 if (err)
97 return err;
98 if (pg_buff < MLXSW_SP_SB_TC_COUNT) {
99 struct mlxsw_sp_sb_cm *cm;
100
101 cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port, pg_buff, dir);
102 cm->min_buff = min_buff;
103 cm->max_buff = max_buff;
104 cm->pool = pool;
105 }
106 return 0;
Jiri Pirko94266e32016-04-14 18:19:16 +0200107}
108
109static int mlxsw_sp_sb_pm_write(struct mlxsw_sp *mlxsw_sp, u8 local_port,
110 u8 pool, enum mlxsw_reg_sbxx_dir dir,
111 u32 min_buff, u32 max_buff)
112{
113 char sbpm_pl[MLXSW_REG_SBPM_LEN];
Jiri Pirko078f9c72016-04-14 18:19:19 +0200114 struct mlxsw_sp_sb_pm *pm;
115 int err;
Jiri Pirko94266e32016-04-14 18:19:16 +0200116
Jiri Pirko42a7f1d2016-04-14 18:19:27 +0200117 mlxsw_reg_sbpm_pack(sbpm_pl, local_port, pool, dir, false,
118 min_buff, max_buff);
Jiri Pirko078f9c72016-04-14 18:19:19 +0200119 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpm), sbpm_pl);
120 if (err)
121 return err;
122
123 pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port, pool, dir);
124 pm->min_buff = min_buff;
125 pm->max_buff = max_buff;
126 return 0;
Jiri Pirko94266e32016-04-14 18:19:16 +0200127}
128
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200129static int mlxsw_sp_sb_pm_occ_clear(struct mlxsw_sp *mlxsw_sp, u8 local_port,
130 u8 pool, enum mlxsw_reg_sbxx_dir dir,
131 struct list_head *bulk_list)
132{
133 char sbpm_pl[MLXSW_REG_SBPM_LEN];
134
135 mlxsw_reg_sbpm_pack(sbpm_pl, local_port, pool, dir, true, 0, 0);
136 return mlxsw_reg_trans_query(mlxsw_sp->core, MLXSW_REG(sbpm), sbpm_pl,
137 bulk_list, NULL, 0);
138}
139
140static void mlxsw_sp_sb_pm_occ_query_cb(struct mlxsw_core *mlxsw_core,
141 char *sbpm_pl, size_t sbpm_pl_len,
142 unsigned long cb_priv)
143{
144 struct mlxsw_sp_sb_pm *pm = (struct mlxsw_sp_sb_pm *) cb_priv;
145
146 mlxsw_reg_sbpm_unpack(sbpm_pl, &pm->occ.cur, &pm->occ.max);
147}
148
149static int mlxsw_sp_sb_pm_occ_query(struct mlxsw_sp *mlxsw_sp, u8 local_port,
150 u8 pool, enum mlxsw_reg_sbxx_dir dir,
151 struct list_head *bulk_list)
152{
153 char sbpm_pl[MLXSW_REG_SBPM_LEN];
154 struct mlxsw_sp_sb_pm *pm;
155
156 pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port, pool, dir);
157 mlxsw_reg_sbpm_pack(sbpm_pl, local_port, pool, dir, false, 0, 0);
158 return mlxsw_reg_trans_query(mlxsw_sp->core, MLXSW_REG(sbpm), sbpm_pl,
159 bulk_list,
160 mlxsw_sp_sb_pm_occ_query_cb,
161 (unsigned long) pm);
162}
163
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200164static const u16 mlxsw_sp_pbs[] = {
165 2 * MLXSW_SP_BYTES_TO_CELLS(ETH_FRAME_LEN),
166 0,
167 0,
168 0,
169 0,
170 0,
171 0,
172 0,
173 0, /* Unused */
174 2 * MLXSW_SP_BYTES_TO_CELLS(MLXSW_PORT_MAX_MTU),
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200175};
176
177#define MLXSW_SP_PBS_LEN ARRAY_SIZE(mlxsw_sp_pbs)
178
179static int mlxsw_sp_port_pb_init(struct mlxsw_sp_port *mlxsw_sp_port)
180{
181 char pbmc_pl[MLXSW_REG_PBMC_LEN];
182 int i;
183
184 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port,
185 0xffff, 0xffff / 2);
186 for (i = 0; i < MLXSW_SP_PBS_LEN; i++) {
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200187 if (i == 8)
188 continue;
189 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, i, mlxsw_sp_pbs[i]);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200190 }
Ido Schimmeld6b7c132016-04-06 17:10:05 +0200191 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl,
192 MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200193 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
194 MLXSW_REG(pbmc), pbmc_pl);
195}
196
Ido Schimmeldd6cb0f2016-04-06 17:10:01 +0200197static int mlxsw_sp_port_pb_prio_init(struct mlxsw_sp_port *mlxsw_sp_port)
198{
199 char pptb_pl[MLXSW_REG_PPTB_LEN];
200 int i;
201
202 mlxsw_reg_pptb_pack(pptb_pl, mlxsw_sp_port->local_port);
203 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
204 mlxsw_reg_pptb_prio_to_buff_set(pptb_pl, i, 0);
205 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pptb),
206 pptb_pl);
207}
208
209static int mlxsw_sp_port_headroom_init(struct mlxsw_sp_port *mlxsw_sp_port)
210{
211 int err;
212
213 err = mlxsw_sp_port_pb_init(mlxsw_sp_port);
214 if (err)
215 return err;
216 return mlxsw_sp_port_pb_prio_init(mlxsw_sp_port);
217}
218
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200219#define MLXSW_SP_SB_PR_INGRESS_SIZE \
Ido Schimmel1a198442016-04-06 17:10:02 +0200220 (15000000 - (2 * 20000 * MLXSW_PORT_MAX_PORTS))
Jiri Pirkobc872502016-04-14 18:19:21 +0200221#define MLXSW_SP_SB_PR_INGRESS_MNG_SIZE (200 * 1000)
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200222#define MLXSW_SP_SB_PR_EGRESS_SIZE \
Ido Schimmel1a198442016-04-06 17:10:02 +0200223 (14000000 - (8 * 1500 * MLXSW_PORT_MAX_PORTS))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200224
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200225#define MLXSW_SP_SB_PR(_mode, _size) \
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200226 { \
227 .mode = _mode, \
228 .size = _size, \
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200229 }
230
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200231static const struct mlxsw_sp_sb_pr mlxsw_sp_sb_prs_ingress[] = {
232 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
233 MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_PR_INGRESS_SIZE)),
234 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
235 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
Jiri Pirkobc872502016-04-14 18:19:21 +0200236 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
237 MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_PR_INGRESS_MNG_SIZE)),
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200238};
239
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200240#define MLXSW_SP_SB_PRS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_prs_ingress)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200241
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200242static const struct mlxsw_sp_sb_pr mlxsw_sp_sb_prs_egress[] = {
243 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
244 MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_PR_EGRESS_SIZE)),
245 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
246 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
Jiri Pirko5408f7c2016-04-14 18:19:20 +0200247 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200248};
249
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200250#define MLXSW_SP_SB_PRS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_prs_egress)
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200251
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200252static int __mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp,
253 enum mlxsw_reg_sbxx_dir dir,
254 const struct mlxsw_sp_sb_pr *prs,
255 size_t prs_len)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200256{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200257 int i;
258 int err;
259
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200260 for (i = 0; i < prs_len; i++) {
261 const struct mlxsw_sp_sb_pr *pr;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200262
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200263 pr = &prs[i];
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200264 err = mlxsw_sp_sb_pr_write(mlxsw_sp, i, dir,
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200265 pr->mode, pr->size);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200266 if (err)
267 return err;
268 }
269 return 0;
270}
271
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200272static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp)
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200273{
274 int err;
275
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200276 err = __mlxsw_sp_sb_prs_init(mlxsw_sp, MLXSW_REG_SBXX_DIR_INGRESS,
277 mlxsw_sp_sb_prs_ingress,
278 MLXSW_SP_SB_PRS_INGRESS_LEN);
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200279 if (err)
280 return err;
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200281 return __mlxsw_sp_sb_prs_init(mlxsw_sp, MLXSW_REG_SBXX_DIR_EGRESS,
282 mlxsw_sp_sb_prs_egress,
283 MLXSW_SP_SB_PRS_EGRESS_LEN);
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200284}
285
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200286#define MLXSW_SP_SB_CM(_min_buff, _max_buff, _pool) \
287 { \
288 .min_buff = _min_buff, \
289 .max_buff = _max_buff, \
290 .pool = _pool, \
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200291 }
292
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200293static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_ingress[] = {
294 MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(10000), 8, 0),
Jiri Pirkoc30a53c2016-04-14 18:19:22 +0200295 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
296 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
297 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
298 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
299 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
300 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
301 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200302 MLXSW_SP_SB_CM(0, 0, 0), /* dummy, this PG does not exist */
Jiri Pirkobc872502016-04-14 18:19:21 +0200303 MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(20000), 1, 3),
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200304};
305
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200306#define MLXSW_SP_SB_CMS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms_ingress)
307
308static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_egress[] = {
309 MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
310 MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
311 MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
312 MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
313 MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
314 MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
315 MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
316 MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
317 MLXSW_SP_SB_CM(0, 0, 0),
318 MLXSW_SP_SB_CM(0, 0, 0),
319 MLXSW_SP_SB_CM(0, 0, 0),
320 MLXSW_SP_SB_CM(0, 0, 0),
321 MLXSW_SP_SB_CM(0, 0, 0),
322 MLXSW_SP_SB_CM(0, 0, 0),
323 MLXSW_SP_SB_CM(0, 0, 0),
324 MLXSW_SP_SB_CM(0, 0, 0),
325 MLXSW_SP_SB_CM(1, 0xff, 0),
326};
327
328#define MLXSW_SP_SB_CMS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms_egress)
329
Jiri Pirko5408f7c2016-04-14 18:19:20 +0200330#define MLXSW_SP_CPU_PORT_SB_CM MLXSW_SP_SB_CM(0, 0, 0)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200331
332static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200333 MLXSW_SP_CPU_PORT_SB_CM,
334 MLXSW_SP_CPU_PORT_SB_CM,
335 MLXSW_SP_CPU_PORT_SB_CM,
336 MLXSW_SP_CPU_PORT_SB_CM,
337 MLXSW_SP_CPU_PORT_SB_CM,
338 MLXSW_SP_CPU_PORT_SB_CM,
339 MLXSW_SP_CPU_PORT_SB_CM,
340 MLXSW_SP_CPU_PORT_SB_CM,
341 MLXSW_SP_CPU_PORT_SB_CM,
342 MLXSW_SP_CPU_PORT_SB_CM,
343 MLXSW_SP_CPU_PORT_SB_CM,
344 MLXSW_SP_CPU_PORT_SB_CM,
345 MLXSW_SP_CPU_PORT_SB_CM,
346 MLXSW_SP_CPU_PORT_SB_CM,
347 MLXSW_SP_CPU_PORT_SB_CM,
348 MLXSW_SP_CPU_PORT_SB_CM,
349 MLXSW_SP_CPU_PORT_SB_CM,
350 MLXSW_SP_CPU_PORT_SB_CM,
351 MLXSW_SP_CPU_PORT_SB_CM,
352 MLXSW_SP_CPU_PORT_SB_CM,
353 MLXSW_SP_CPU_PORT_SB_CM,
354 MLXSW_SP_CPU_PORT_SB_CM,
355 MLXSW_SP_CPU_PORT_SB_CM,
356 MLXSW_SP_CPU_PORT_SB_CM,
357 MLXSW_SP_CPU_PORT_SB_CM,
358 MLXSW_SP_CPU_PORT_SB_CM,
359 MLXSW_SP_CPU_PORT_SB_CM,
360 MLXSW_SP_CPU_PORT_SB_CM,
361 MLXSW_SP_CPU_PORT_SB_CM,
362 MLXSW_SP_CPU_PORT_SB_CM,
363 MLXSW_SP_CPU_PORT_SB_CM,
364 MLXSW_SP_CPU_PORT_SB_CM,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200365};
366
367#define MLXSW_SP_CPU_PORT_SB_MCS_LEN \
368 ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms)
369
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200370static int __mlxsw_sp_sb_cms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
371 enum mlxsw_reg_sbxx_dir dir,
372 const struct mlxsw_sp_sb_cm *cms,
373 size_t cms_len)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200374{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200375 int i;
376 int err;
377
378 for (i = 0; i < cms_len; i++) {
379 const struct mlxsw_sp_sb_cm *cm;
380
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200381 if (i == 8 && dir == MLXSW_REG_SBXX_DIR_INGRESS)
382 continue; /* PG number 8 does not exist, skip it */
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200383 cm = &cms[i];
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200384 err = mlxsw_sp_sb_cm_write(mlxsw_sp, local_port, i, dir,
385 cm->min_buff, cm->max_buff,
386 cm->pool);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200387 if (err)
388 return err;
389 }
390 return 0;
391}
392
393static int mlxsw_sp_port_sb_cms_init(struct mlxsw_sp_port *mlxsw_sp_port)
394{
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200395 int err;
396
397 err = __mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
398 mlxsw_sp_port->local_port,
399 MLXSW_REG_SBXX_DIR_INGRESS,
400 mlxsw_sp_sb_cms_ingress,
401 MLXSW_SP_SB_CMS_INGRESS_LEN);
402 if (err)
403 return err;
404 return __mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
405 mlxsw_sp_port->local_port,
406 MLXSW_REG_SBXX_DIR_EGRESS,
407 mlxsw_sp_sb_cms_egress,
408 MLXSW_SP_SB_CMS_EGRESS_LEN);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200409}
410
411static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
412{
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200413 return __mlxsw_sp_sb_cms_init(mlxsw_sp, 0, MLXSW_REG_SBXX_DIR_EGRESS,
414 mlxsw_sp_cpu_port_sb_cms,
415 MLXSW_SP_CPU_PORT_SB_MCS_LEN);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200416}
417
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200418#define MLXSW_SP_SB_PM(_min_buff, _max_buff) \
419 { \
420 .min_buff = _min_buff, \
421 .max_buff = _max_buff, \
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200422 }
423
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200424static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms_ingress[] = {
Jiri Pirkoc30a53c2016-04-14 18:19:22 +0200425 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
426 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
427 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
428 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200429};
430
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200431#define MLXSW_SP_SB_PMS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms_ingress)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200432
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200433static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms_egress[] = {
434 MLXSW_SP_SB_PM(0, 7),
Jiri Pirkoc30a53c2016-04-14 18:19:22 +0200435 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
436 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
437 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200438};
439
440#define MLXSW_SP_SB_PMS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms_egress)
441
442static int __mlxsw_sp_port_sb_pms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
443 enum mlxsw_reg_sbxx_dir dir,
444 const struct mlxsw_sp_sb_pm *pms,
445 size_t pms_len)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200446{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200447 int i;
448 int err;
449
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200450 for (i = 0; i < pms_len; i++) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200451 const struct mlxsw_sp_sb_pm *pm;
452
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200453 pm = &pms[i];
454 err = mlxsw_sp_sb_pm_write(mlxsw_sp, local_port, i, dir,
Jiri Pirko94266e32016-04-14 18:19:16 +0200455 pm->min_buff, pm->max_buff);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200456 if (err)
457 return err;
458 }
459 return 0;
460}
461
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200462static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
463{
464 int err;
465
466 err = __mlxsw_sp_port_sb_pms_init(mlxsw_sp_port->mlxsw_sp,
467 mlxsw_sp_port->local_port,
468 MLXSW_REG_SBXX_DIR_INGRESS,
469 mlxsw_sp_sb_pms_ingress,
470 MLXSW_SP_SB_PMS_INGRESS_LEN);
471 if (err)
472 return err;
473 return __mlxsw_sp_port_sb_pms_init(mlxsw_sp_port->mlxsw_sp,
474 mlxsw_sp_port->local_port,
475 MLXSW_REG_SBXX_DIR_EGRESS,
476 mlxsw_sp_sb_pms_egress,
477 MLXSW_SP_SB_PMS_EGRESS_LEN);
478}
479
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200480struct mlxsw_sp_sb_mm {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200481 u32 min_buff;
482 u32 max_buff;
483 u8 pool;
484};
485
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200486#define MLXSW_SP_SB_MM(_min_buff, _max_buff, _pool) \
487 { \
488 .min_buff = _min_buff, \
489 .max_buff = _max_buff, \
490 .pool = _pool, \
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200491 }
492
493static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = {
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200494 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
495 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
496 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
497 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
498 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
499 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
500 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
501 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
502 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
503 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
504 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
505 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
506 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
507 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
508 MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200509};
510
511#define MLXSW_SP_SB_MMS_LEN ARRAY_SIZE(mlxsw_sp_sb_mms)
512
513static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp)
514{
515 char sbmm_pl[MLXSW_REG_SBMM_LEN];
516 int i;
517 int err;
518
519 for (i = 0; i < MLXSW_SP_SB_MMS_LEN; i++) {
520 const struct mlxsw_sp_sb_mm *mc;
521
522 mc = &mlxsw_sp_sb_mms[i];
Jiri Pirkob11c3b42016-04-14 18:19:17 +0200523 mlxsw_reg_sbmm_pack(sbmm_pl, i, mc->min_buff,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200524 mc->max_buff, mc->pool);
525 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbmm), sbmm_pl);
526 if (err)
527 return err;
528 }
529 return 0;
530}
531
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200532#define MLXSW_SP_SB_SIZE (16 * 1024 * 1024)
533
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200534int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
535{
536 int err;
537
Jiri Pirkoaa99bc72016-04-14 18:19:18 +0200538 err = mlxsw_sp_sb_prs_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200539 if (err)
540 return err;
541 err = mlxsw_sp_cpu_port_sb_cms_init(mlxsw_sp);
542 if (err)
543 return err;
544 err = mlxsw_sp_sb_mms_init(mlxsw_sp);
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200545 if (err)
546 return err;
547 return devlink_sb_register(priv_to_devlink(mlxsw_sp->core), 0,
548 MLXSW_SP_SB_SIZE,
549 MLXSW_SP_SB_POOL_COUNT,
550 MLXSW_SP_SB_POOL_COUNT,
551 MLXSW_SP_SB_TC_COUNT,
552 MLXSW_SP_SB_TC_COUNT);
553}
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200554
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200555void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp)
556{
557 devlink_sb_unregister(priv_to_devlink(mlxsw_sp->core), 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200558}
559
560int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port)
561{
562 int err;
563
Ido Schimmeldd6cb0f2016-04-06 17:10:01 +0200564 err = mlxsw_sp_port_headroom_init(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200565 if (err)
566 return err;
567 err = mlxsw_sp_port_sb_cms_init(mlxsw_sp_port);
568 if (err)
569 return err;
570 err = mlxsw_sp_port_sb_pms_init(mlxsw_sp_port);
571
572 return err;
573}
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200574
575static u8 pool_get(u16 pool_index)
576{
577 return pool_index % MLXSW_SP_SB_POOL_COUNT;
578}
579
580static u16 pool_index_get(u8 pool, enum mlxsw_reg_sbxx_dir dir)
581{
582 u16 pool_index;
583
584 pool_index = pool;
585 if (dir == MLXSW_REG_SBXX_DIR_EGRESS)
586 pool_index += MLXSW_SP_SB_POOL_COUNT;
587 return pool_index;
588}
589
590static enum mlxsw_reg_sbxx_dir dir_get(u16 pool_index)
591{
592 return pool_index < MLXSW_SP_SB_POOL_COUNT ?
593 MLXSW_REG_SBXX_DIR_INGRESS : MLXSW_REG_SBXX_DIR_EGRESS;
594}
595
596int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
597 unsigned int sb_index, u16 pool_index,
598 struct devlink_sb_pool_info *pool_info)
599{
600 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
601 u8 pool = pool_get(pool_index);
602 enum mlxsw_reg_sbxx_dir dir = dir_get(pool_index);
603 struct mlxsw_sp_sb_pr *pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool, dir);
604
605 pool_info->pool_type = dir;
606 pool_info->size = MLXSW_SP_CELLS_TO_BYTES(pr->size);
607 pool_info->threshold_type = pr->mode;
608 return 0;
609}
610
611int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
612 unsigned int sb_index, u16 pool_index, u32 size,
613 enum devlink_sb_threshold_type threshold_type)
614{
615 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
616 u8 pool = pool_get(pool_index);
617 enum mlxsw_reg_sbxx_dir dir = dir_get(pool_index);
618 enum mlxsw_reg_sbpr_mode mode = threshold_type;
619 u32 pool_size = MLXSW_SP_BYTES_TO_CELLS(size);
620
621 return mlxsw_sp_sb_pr_write(mlxsw_sp, pool, dir, mode, pool_size);
622}
623
624#define MLXSW_SP_SB_THRESHOLD_TO_ALPHA_OFFSET (-2) /* 3->1, 16->14 */
625
626static u32 mlxsw_sp_sb_threshold_out(struct mlxsw_sp *mlxsw_sp, u8 pool,
627 enum mlxsw_reg_sbxx_dir dir, u32 max_buff)
628{
629 struct mlxsw_sp_sb_pr *pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool, dir);
630
631 if (pr->mode == MLXSW_REG_SBPR_MODE_DYNAMIC)
632 return max_buff - MLXSW_SP_SB_THRESHOLD_TO_ALPHA_OFFSET;
633 return MLXSW_SP_CELLS_TO_BYTES(max_buff);
634}
635
636static int mlxsw_sp_sb_threshold_in(struct mlxsw_sp *mlxsw_sp, u8 pool,
637 enum mlxsw_reg_sbxx_dir dir, u32 threshold,
638 u32 *p_max_buff)
639{
640 struct mlxsw_sp_sb_pr *pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool, dir);
641
642 if (pr->mode == MLXSW_REG_SBPR_MODE_DYNAMIC) {
643 int val;
644
645 val = threshold + MLXSW_SP_SB_THRESHOLD_TO_ALPHA_OFFSET;
646 if (val < MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN ||
647 val > MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX)
648 return -EINVAL;
649 *p_max_buff = val;
650 } else {
651 *p_max_buff = MLXSW_SP_BYTES_TO_CELLS(threshold);
652 }
653 return 0;
654}
655
656int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
657 unsigned int sb_index, u16 pool_index,
658 u32 *p_threshold)
659{
660 struct mlxsw_sp_port *mlxsw_sp_port =
661 mlxsw_core_port_driver_priv(mlxsw_core_port);
662 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
663 u8 local_port = mlxsw_sp_port->local_port;
664 u8 pool = pool_get(pool_index);
665 enum mlxsw_reg_sbxx_dir dir = dir_get(pool_index);
666 struct mlxsw_sp_sb_pm *pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port,
667 pool, dir);
668
669 *p_threshold = mlxsw_sp_sb_threshold_out(mlxsw_sp, pool, dir,
670 pm->max_buff);
671 return 0;
672}
673
674int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
675 unsigned int sb_index, u16 pool_index,
676 u32 threshold)
677{
678 struct mlxsw_sp_port *mlxsw_sp_port =
679 mlxsw_core_port_driver_priv(mlxsw_core_port);
680 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
681 u8 local_port = mlxsw_sp_port->local_port;
682 u8 pool = pool_get(pool_index);
683 enum mlxsw_reg_sbxx_dir dir = dir_get(pool_index);
684 u32 max_buff;
685 int err;
686
687 err = mlxsw_sp_sb_threshold_in(mlxsw_sp, pool, dir,
688 threshold, &max_buff);
689 if (err)
690 return err;
691
692 return mlxsw_sp_sb_pm_write(mlxsw_sp, local_port, pool, dir,
693 0, max_buff);
694}
695
696int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
697 unsigned int sb_index, u16 tc_index,
698 enum devlink_sb_pool_type pool_type,
699 u16 *p_pool_index, u32 *p_threshold)
700{
701 struct mlxsw_sp_port *mlxsw_sp_port =
702 mlxsw_core_port_driver_priv(mlxsw_core_port);
703 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
704 u8 local_port = mlxsw_sp_port->local_port;
705 u8 pg_buff = tc_index;
706 enum mlxsw_reg_sbxx_dir dir = pool_type;
707 struct mlxsw_sp_sb_cm *cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port,
708 pg_buff, dir);
709
710 *p_threshold = mlxsw_sp_sb_threshold_out(mlxsw_sp, cm->pool, dir,
711 cm->max_buff);
712 *p_pool_index = pool_index_get(cm->pool, pool_type);
713 return 0;
714}
715
716int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
717 unsigned int sb_index, u16 tc_index,
718 enum devlink_sb_pool_type pool_type,
719 u16 pool_index, u32 threshold)
720{
721 struct mlxsw_sp_port *mlxsw_sp_port =
722 mlxsw_core_port_driver_priv(mlxsw_core_port);
723 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
724 u8 local_port = mlxsw_sp_port->local_port;
725 u8 pg_buff = tc_index;
726 enum mlxsw_reg_sbxx_dir dir = pool_type;
727 u8 pool = pool_index;
728 u32 max_buff;
729 int err;
730
731 err = mlxsw_sp_sb_threshold_in(mlxsw_sp, pool, dir,
732 threshold, &max_buff);
733 if (err)
734 return err;
735
736 if (pool_type == DEVLINK_SB_POOL_TYPE_EGRESS) {
737 if (pool < MLXSW_SP_SB_POOL_COUNT)
738 return -EINVAL;
739 pool -= MLXSW_SP_SB_POOL_COUNT;
740 } else if (pool >= MLXSW_SP_SB_POOL_COUNT) {
741 return -EINVAL;
742 }
743 return mlxsw_sp_sb_cm_write(mlxsw_sp, local_port, pg_buff, dir,
744 0, max_buff, pool);
745}
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200746
747#define MASKED_COUNT_MAX \
748 (MLXSW_REG_SBSR_REC_MAX_COUNT / (MLXSW_SP_SB_TC_COUNT * 2))
749
750struct mlxsw_sp_sb_sr_occ_query_cb_ctx {
751 u8 masked_count;
752 u8 local_port_1;
753};
754
755static void mlxsw_sp_sb_sr_occ_query_cb(struct mlxsw_core *mlxsw_core,
756 char *sbsr_pl, size_t sbsr_pl_len,
757 unsigned long cb_priv)
758{
759 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
760 struct mlxsw_sp_sb_sr_occ_query_cb_ctx cb_ctx;
761 u8 masked_count;
762 u8 local_port;
763 int rec_index = 0;
764 struct mlxsw_sp_sb_cm *cm;
765 int i;
766
767 memcpy(&cb_ctx, &cb_priv, sizeof(cb_ctx));
768
769 masked_count = 0;
770 for (local_port = cb_ctx.local_port_1;
771 local_port < MLXSW_PORT_MAX_PORTS; local_port++) {
772 if (!mlxsw_sp->ports[local_port])
773 continue;
774 for (i = 0; i < MLXSW_SP_SB_TC_COUNT; i++) {
775 cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port, i,
776 MLXSW_REG_SBXX_DIR_INGRESS);
777 mlxsw_reg_sbsr_rec_unpack(sbsr_pl, rec_index++,
778 &cm->occ.cur, &cm->occ.max);
779 }
780 if (++masked_count == cb_ctx.masked_count)
781 break;
782 }
783 masked_count = 0;
784 for (local_port = cb_ctx.local_port_1;
785 local_port < MLXSW_PORT_MAX_PORTS; local_port++) {
786 if (!mlxsw_sp->ports[local_port])
787 continue;
788 for (i = 0; i < MLXSW_SP_SB_TC_COUNT; i++) {
789 cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port, i,
790 MLXSW_REG_SBXX_DIR_EGRESS);
791 mlxsw_reg_sbsr_rec_unpack(sbsr_pl, rec_index++,
792 &cm->occ.cur, &cm->occ.max);
793 }
794 if (++masked_count == cb_ctx.masked_count)
795 break;
796 }
797}
798
799int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
800 unsigned int sb_index)
801{
802 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
803 struct mlxsw_sp_sb_sr_occ_query_cb_ctx cb_ctx;
804 unsigned long cb_priv;
805 LIST_HEAD(bulk_list);
806 char *sbsr_pl;
807 u8 masked_count;
808 u8 local_port_1;
809 u8 local_port = 0;
810 int i;
811 int err;
812 int err2;
813
814 sbsr_pl = kmalloc(MLXSW_REG_SBSR_LEN, GFP_KERNEL);
815 if (!sbsr_pl)
816 return -ENOMEM;
817
818next_batch:
819 local_port++;
820 local_port_1 = local_port;
821 masked_count = 0;
822 mlxsw_reg_sbsr_pack(sbsr_pl, false);
823 for (i = 0; i < MLXSW_SP_SB_TC_COUNT; i++) {
824 mlxsw_reg_sbsr_pg_buff_mask_set(sbsr_pl, i, 1);
825 mlxsw_reg_sbsr_tclass_mask_set(sbsr_pl, i, 1);
826 }
827 for (; local_port < MLXSW_PORT_MAX_PORTS; local_port++) {
828 if (!mlxsw_sp->ports[local_port])
829 continue;
830 mlxsw_reg_sbsr_ingress_port_mask_set(sbsr_pl, local_port, 1);
831 mlxsw_reg_sbsr_egress_port_mask_set(sbsr_pl, local_port, 1);
832 for (i = 0; i < MLXSW_SP_SB_POOL_COUNT; i++) {
833 err = mlxsw_sp_sb_pm_occ_query(mlxsw_sp, local_port, i,
834 MLXSW_REG_SBXX_DIR_INGRESS,
835 &bulk_list);
836 if (err)
837 goto out;
838 err = mlxsw_sp_sb_pm_occ_query(mlxsw_sp, local_port, i,
839 MLXSW_REG_SBXX_DIR_EGRESS,
840 &bulk_list);
841 if (err)
842 goto out;
843 }
844 if (++masked_count == MASKED_COUNT_MAX)
845 goto do_query;
846 }
847
848do_query:
849 cb_ctx.masked_count = masked_count;
850 cb_ctx.local_port_1 = local_port_1;
851 memcpy(&cb_priv, &cb_ctx, sizeof(cb_ctx));
852 err = mlxsw_reg_trans_query(mlxsw_core, MLXSW_REG(sbsr), sbsr_pl,
853 &bulk_list, mlxsw_sp_sb_sr_occ_query_cb,
854 cb_priv);
855 if (err)
856 goto out;
857 if (local_port < MLXSW_PORT_MAX_PORTS)
858 goto next_batch;
859
860out:
861 err2 = mlxsw_reg_trans_bulk_wait(&bulk_list);
862 if (!err)
863 err = err2;
864 kfree(sbsr_pl);
865 return err;
866}
867
868int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
869 unsigned int sb_index)
870{
871 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
872 LIST_HEAD(bulk_list);
873 char *sbsr_pl;
874 unsigned int masked_count;
875 u8 local_port = 0;
876 int i;
877 int err;
878 int err2;
879
880 sbsr_pl = kmalloc(MLXSW_REG_SBSR_LEN, GFP_KERNEL);
881 if (!sbsr_pl)
882 return -ENOMEM;
883
884next_batch:
885 local_port++;
886 masked_count = 0;
887 mlxsw_reg_sbsr_pack(sbsr_pl, true);
888 for (i = 0; i < MLXSW_SP_SB_TC_COUNT; i++) {
889 mlxsw_reg_sbsr_pg_buff_mask_set(sbsr_pl, i, 1);
890 mlxsw_reg_sbsr_tclass_mask_set(sbsr_pl, i, 1);
891 }
892 for (; local_port < MLXSW_PORT_MAX_PORTS; local_port++) {
893 if (!mlxsw_sp->ports[local_port])
894 continue;
895 mlxsw_reg_sbsr_ingress_port_mask_set(sbsr_pl, local_port, 1);
896 mlxsw_reg_sbsr_egress_port_mask_set(sbsr_pl, local_port, 1);
897 for (i = 0; i < MLXSW_SP_SB_POOL_COUNT; i++) {
898 err = mlxsw_sp_sb_pm_occ_clear(mlxsw_sp, local_port, i,
899 MLXSW_REG_SBXX_DIR_INGRESS,
900 &bulk_list);
901 if (err)
902 goto out;
903 err = mlxsw_sp_sb_pm_occ_clear(mlxsw_sp, local_port, i,
904 MLXSW_REG_SBXX_DIR_EGRESS,
905 &bulk_list);
906 if (err)
907 goto out;
908 }
909 if (++masked_count == MASKED_COUNT_MAX)
910 goto do_query;
911 }
912
913do_query:
914 err = mlxsw_reg_trans_query(mlxsw_core, MLXSW_REG(sbsr), sbsr_pl,
915 &bulk_list, NULL, 0);
916 if (err)
917 goto out;
918 if (local_port < MLXSW_PORT_MAX_PORTS)
919 goto next_batch;
920
921out:
922 err2 = mlxsw_reg_trans_bulk_wait(&bulk_list);
923 if (!err)
924 err = err2;
925 kfree(sbsr_pl);
926 return err;
927}
928
929int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
930 unsigned int sb_index, u16 pool_index,
931 u32 *p_cur, u32 *p_max)
932{
933 struct mlxsw_sp_port *mlxsw_sp_port =
934 mlxsw_core_port_driver_priv(mlxsw_core_port);
935 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
936 u8 local_port = mlxsw_sp_port->local_port;
937 u8 pool = pool_get(pool_index);
938 enum mlxsw_reg_sbxx_dir dir = dir_get(pool_index);
939 struct mlxsw_sp_sb_pm *pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port,
940 pool, dir);
941
942 *p_cur = MLXSW_SP_CELLS_TO_BYTES(pm->occ.cur);
943 *p_max = MLXSW_SP_CELLS_TO_BYTES(pm->occ.max);
944 return 0;
945}
946
947int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
948 unsigned int sb_index, u16 tc_index,
949 enum devlink_sb_pool_type pool_type,
950 u32 *p_cur, u32 *p_max)
951{
952 struct mlxsw_sp_port *mlxsw_sp_port =
953 mlxsw_core_port_driver_priv(mlxsw_core_port);
954 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
955 u8 local_port = mlxsw_sp_port->local_port;
956 u8 pg_buff = tc_index;
957 enum mlxsw_reg_sbxx_dir dir = pool_type;
958 struct mlxsw_sp_sb_cm *cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port,
959 pg_buff, dir);
960
961 *p_cur = MLXSW_SP_CELLS_TO_BYTES(cm->occ.cur);
962 *p_max = MLXSW_SP_CELLS_TO_BYTES(cm->occ.max);
963 return 0;
964}