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gerrit-public.fairphone.software / kernel / msm-5.4 / 2d5a3c803deedfa60014be8c0d933591c53db419 / . / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
blob: 817dbd87ce6742ae87e7a794d7f88e07c6266ecc [file] [log] [blame]
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
Andreas Fenkart551434382014-11-08 15:33:09 +0100[diff] [blame]22#include <linux/platform_data/hsmmc-omap.h>
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]23#include <linux/power/smartreflex.h>
24#include <linux/i2c-omap.h>
25
26#include <linux/omap-dma.h>
27#include <linux/platform_data/spi-omap2-mcspi.h>
28#include <linux/platform_data/asoc-ti-mcbsp.h>
29#include <plat/dmtimer.h>
30
31#include "omap_hwmod.h"
32#include "omap_hwmod_common_data.h"
33#include "cm1_7xx.h"
34#include "cm2_7xx.h"
35#include "prm7xx.h"
36#include "i2c.h"
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]37#include "wd_timer.h"
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]38#include "soc.h"
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]39
40/* Base offset for all DRA7XX interrupts external to MPUSS */
41#define DRA7XX_IRQ_GIC_START 32
42
43/* Base offset for all DRA7XX dma requests */
44#define DRA7XX_DMA_REQ_START 1
45
46
47/*
48 * IP blocks
49 */
50
51/*
52 * 'l3' class
53 * instance(s): l3_instr, l3_main_1, l3_main_2
54 */
55static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
56 .name = "l3",
57};
58
59/* l3_instr */
60static struct omap_hwmod dra7xx_l3_instr_hwmod = {
61 .name = "l3_instr",
62 .class = &dra7xx_l3_hwmod_class,
63 .clkdm_name = "l3instr_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
68 .modulemode = MODULEMODE_HWCTRL,
69 },
70 },
71};
72
73/* l3_main_1 */
74static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
75 .name = "l3_main_1",
76 .class = &dra7xx_l3_hwmod_class,
77 .clkdm_name = "l3main1_clkdm",
78 .prcm = {
79 .omap4 = {
80 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
81 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
82 },
83 },
84};
85
86/* l3_main_2 */
87static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
88 .name = "l3_main_2",
89 .class = &dra7xx_l3_hwmod_class,
90 .clkdm_name = "l3instr_clkdm",
91 .prcm = {
92 .omap4 = {
93 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
94 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
95 .modulemode = MODULEMODE_HWCTRL,
96 },
97 },
98};
99
100/*
101 * 'l4' class
102 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
103 */
104static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
105 .name = "l4",
106};
107
108/* l4_cfg */
109static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
110 .name = "l4_cfg",
111 .class = &dra7xx_l4_hwmod_class,
112 .clkdm_name = "l4cfg_clkdm",
113 .prcm = {
114 .omap4 = {
115 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
116 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
117 },
118 },
119};
120
121/* l4_per1 */
122static struct omap_hwmod dra7xx_l4_per1_hwmod = {
123 .name = "l4_per1",
124 .class = &dra7xx_l4_hwmod_class,
125 .clkdm_name = "l4per_clkdm",
126 .prcm = {
127 .omap4 = {
128 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
129 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
130 },
131 },
132};
133
134/* l4_per2 */
135static struct omap_hwmod dra7xx_l4_per2_hwmod = {
136 .name = "l4_per2",
137 .class = &dra7xx_l4_hwmod_class,
138 .clkdm_name = "l4per2_clkdm",
139 .prcm = {
140 .omap4 = {
141 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
142 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
143 },
144 },
145};
146
147/* l4_per3 */
148static struct omap_hwmod dra7xx_l4_per3_hwmod = {
149 .name = "l4_per3",
150 .class = &dra7xx_l4_hwmod_class,
151 .clkdm_name = "l4per3_clkdm",
152 .prcm = {
153 .omap4 = {
154 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
155 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
156 },
157 },
158};
159
160/* l4_wkup */
161static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
162 .name = "l4_wkup",
163 .class = &dra7xx_l4_hwmod_class,
164 .clkdm_name = "wkupaon_clkdm",
165 .prcm = {
166 .omap4 = {
167 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
168 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
169 },
170 },
171};
172
173/*
174 * 'atl' class
175 *
176 */
177
178static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
179 .name = "atl",
180};
181
182/* atl */
183static struct omap_hwmod dra7xx_atl_hwmod = {
184 .name = "atl",
185 .class = &dra7xx_atl_hwmod_class,
186 .clkdm_name = "atl_clkdm",
187 .main_clk = "atl_gfclk_mux",
188 .prcm = {
189 .omap4 = {
190 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
191 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
192 .modulemode = MODULEMODE_SWCTRL,
193 },
194 },
195};
196
197/*
198 * 'bb2d' class
199 *
200 */
201
202static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
203 .name = "bb2d",
204};
205
206/* bb2d */
207static struct omap_hwmod dra7xx_bb2d_hwmod = {
208 .name = "bb2d",
209 .class = &dra7xx_bb2d_hwmod_class,
210 .clkdm_name = "dss_clkdm",
211 .main_clk = "dpll_core_h24x2_ck",
212 .prcm = {
213 .omap4 = {
214 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
215 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
216 .modulemode = MODULEMODE_SWCTRL,
217 },
218 },
219};
220
221/*
222 * 'counter' class
223 *
224 */
225
226static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
227 .rev_offs = 0x0000,
228 .sysc_offs = 0x0010,
229 .sysc_flags = SYSC_HAS_SIDLEMODE,
230 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
231 SIDLE_SMART_WKUP),
232 .sysc_fields = &omap_hwmod_sysc_type1,
233};
234
235static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
236 .name = "counter",
237 .sysc = &dra7xx_counter_sysc,
238};
239
240/* counter_32k */
241static struct omap_hwmod dra7xx_counter_32k_hwmod = {
242 .name = "counter_32k",
243 .class = &dra7xx_counter_hwmod_class,
244 .clkdm_name = "wkupaon_clkdm",
245 .flags = HWMOD_SWSUP_SIDLE,
246 .main_clk = "wkupaon_iclk_mux",
247 .prcm = {
248 .omap4 = {
249 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
250 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
251 },
252 },
253};
254
255/*
256 * 'ctrl_module' class
257 *
258 */
259
260static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
261 .name = "ctrl_module",
262};
263
264/* ctrl_module_wkup */
265static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
266 .name = "ctrl_module_wkup",
267 .class = &dra7xx_ctrl_module_hwmod_class,
268 .clkdm_name = "wkupaon_clkdm",
269 .prcm = {
270 .omap4 = {
271 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
272 },
273 },
274};
275
276/*
Mugunthan V N077c42f2014-07-08 18:46:39 +0530[diff] [blame]277 * 'gmac' class
278 * cpsw/gmac sub system
279 */
280static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
281 .rev_offs = 0x0,
282 .sysc_offs = 0x8,
283 .syss_offs = 0x4,
284 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
285 SYSS_HAS_RESET_STATUS),
286 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
287 MSTANDBY_NO),
288 .sysc_fields = &omap_hwmod_sysc_type3,
289};
290
291static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
292 .name = "gmac",
293 .sysc = &dra7xx_gmac_sysc,
294};
295
296static struct omap_hwmod dra7xx_gmac_hwmod = {
297 .name = "gmac",
298 .class = &dra7xx_gmac_hwmod_class,
299 .clkdm_name = "gmac_clkdm",
300 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
301 .main_clk = "dpll_gmac_ck",
302 .mpu_rt_idx = 1,
303 .prcm = {
304 .omap4 = {
305 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
306 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
307 .modulemode = MODULEMODE_SWCTRL,
308 },
309 },
310};
311
312/*
313 * 'mdio' class
314 */
315static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
316 .name = "davinci_mdio",
317};
318
319static struct omap_hwmod dra7xx_mdio_hwmod = {
320 .name = "davinci_mdio",
321 .class = &dra7xx_mdio_hwmod_class,
322 .clkdm_name = "gmac_clkdm",
323 .main_clk = "dpll_gmac_ck",
324};
325
326/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]327 * 'dcan' class
328 *
329 */
330
331static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
332 .name = "dcan",
333};
334
335/* dcan1 */
336static struct omap_hwmod dra7xx_dcan1_hwmod = {
337 .name = "dcan1",
338 .class = &dra7xx_dcan_hwmod_class,
339 .clkdm_name = "wkupaon_clkdm",
340 .main_clk = "dcan1_sys_clk_mux",
341 .prcm = {
342 .omap4 = {
343 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
344 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
345 .modulemode = MODULEMODE_SWCTRL,
346 },
347 },
348};
349
350/* dcan2 */
351static struct omap_hwmod dra7xx_dcan2_hwmod = {
352 .name = "dcan2",
353 .class = &dra7xx_dcan_hwmod_class,
354 .clkdm_name = "l4per2_clkdm",
355 .main_clk = "sys_clkin1",
356 .prcm = {
357 .omap4 = {
358 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
359 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
360 .modulemode = MODULEMODE_SWCTRL,
361 },
362 },
363};
364
365/*
366 * 'dma' class
367 *
368 */
369
370static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
371 .rev_offs = 0x0000,
372 .sysc_offs = 0x002c,
373 .syss_offs = 0x0028,
374 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
375 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
376 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
377 SYSS_HAS_RESET_STATUS),
378 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
379 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
380 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
381 .sysc_fields = &omap_hwmod_sysc_type1,
382};
383
384static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
385 .name = "dma",
386 .sysc = &dra7xx_dma_sysc,
387};
388
389/* dma dev_attr */
390static struct omap_dma_dev_attr dma_dev_attr = {
391 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
392 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
393 .lch_count = 32,
394};
395
396/* dma_system */
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]397static struct omap_hwmod dra7xx_dma_system_hwmod = {
398 .name = "dma_system",
399 .class = &dra7xx_dma_hwmod_class,
400 .clkdm_name = "dma_clkdm",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]401 .main_clk = "l3_iclk_div",
402 .prcm = {
403 .omap4 = {
404 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
405 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
406 },
407 },
408 .dev_attr = &dma_dev_attr,
409};
410
411/*
412 * 'dss' class
413 *
414 */
415
416static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
417 .rev_offs = 0x0000,
418 .syss_offs = 0x0014,
419 .sysc_flags = SYSS_HAS_RESET_STATUS,
420};
421
422static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
423 .name = "dss",
424 .sysc = &dra7xx_dss_sysc,
425 .reset = omap_dss_reset,
426};
427
428/* dss */
429static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
430 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
431 { .dma_req = -1 }
432};
433
434static struct omap_hwmod_opt_clk dss_opt_clks[] = {
435 { .role = "dss_clk", .clk = "dss_dss_clk" },
436 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
437 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
438 { .role = "video2_clk", .clk = "dss_video2_clk" },
439 { .role = "video1_clk", .clk = "dss_video1_clk" },
440 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
Tomi Valkeinen2d5a3c82015-02-23 12:53:56 +0200[diff] [blame^]441 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]442};
443
444static struct omap_hwmod dra7xx_dss_hwmod = {
445 .name = "dss_core",
446 .class = &dra7xx_dss_hwmod_class,
447 .clkdm_name = "dss_clkdm",
448 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
449 .sdma_reqs = dra7xx_dss_sdma_reqs,
450 .main_clk = "dss_dss_clk",
451 .prcm = {
452 .omap4 = {
453 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
454 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
455 .modulemode = MODULEMODE_SWCTRL,
456 },
457 },
458 .opt_clks = dss_opt_clks,
459 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
460};
461
462/*
463 * 'dispc' class
464 * display controller
465 */
466
467static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
468 .rev_offs = 0x0000,
469 .sysc_offs = 0x0010,
470 .syss_offs = 0x0014,
471 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
472 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
473 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
474 SYSS_HAS_RESET_STATUS),
475 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
476 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
477 .sysc_fields = &omap_hwmod_sysc_type1,
478};
479
480static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
481 .name = "dispc",
482 .sysc = &dra7xx_dispc_sysc,
483};
484
485/* dss_dispc */
486/* dss_dispc dev_attr */
487static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
488 .has_framedonetv_irq = 1,
489 .manager_count = 4,
490};
491
492static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
493 .name = "dss_dispc",
494 .class = &dra7xx_dispc_hwmod_class,
495 .clkdm_name = "dss_clkdm",
496 .main_clk = "dss_dss_clk",
497 .prcm = {
498 .omap4 = {
499 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
500 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
501 },
502 },
503 .dev_attr = &dss_dispc_dev_attr,
504};
505
506/*
507 * 'hdmi' class
508 * hdmi controller
509 */
510
511static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
512 .rev_offs = 0x0000,
513 .sysc_offs = 0x0010,
514 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
515 SYSC_HAS_SOFTRESET),
516 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
517 SIDLE_SMART_WKUP),
518 .sysc_fields = &omap_hwmod_sysc_type2,
519};
520
521static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
522 .name = "hdmi",
523 .sysc = &dra7xx_hdmi_sysc,
524};
525
526/* dss_hdmi */
527
528static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
529 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
530};
531
532static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
533 .name = "dss_hdmi",
534 .class = &dra7xx_hdmi_hwmod_class,
535 .clkdm_name = "dss_clkdm",
536 .main_clk = "dss_48mhz_clk",
537 .prcm = {
538 .omap4 = {
539 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
540 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
541 },
542 },
543 .opt_clks = dss_hdmi_opt_clks,
544 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
545};
546
547/*
548 * 'elm' class
549 *
550 */
551
552static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
553 .rev_offs = 0x0000,
554 .sysc_offs = 0x0010,
555 .syss_offs = 0x0014,
556 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
557 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
558 SYSS_HAS_RESET_STATUS),
559 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
560 SIDLE_SMART_WKUP),
561 .sysc_fields = &omap_hwmod_sysc_type1,
562};
563
564static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
565 .name = "elm",
566 .sysc = &dra7xx_elm_sysc,
567};
568
569/* elm */
570
571static struct omap_hwmod dra7xx_elm_hwmod = {
572 .name = "elm",
573 .class = &dra7xx_elm_hwmod_class,
574 .clkdm_name = "l4per_clkdm",
575 .main_clk = "l3_iclk_div",
576 .prcm = {
577 .omap4 = {
578 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
579 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
580 },
581 },
582};
583
584/*
585 * 'gpio' class
586 *
587 */
588
589static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
590 .rev_offs = 0x0000,
591 .sysc_offs = 0x0010,
592 .syss_offs = 0x0114,
593 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
594 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
595 SYSS_HAS_RESET_STATUS),
596 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
597 SIDLE_SMART_WKUP),
598 .sysc_fields = &omap_hwmod_sysc_type1,
599};
600
601static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
602 .name = "gpio",
603 .sysc = &dra7xx_gpio_sysc,
604 .rev = 2,
605};
606
607/* gpio dev_attr */
608static struct omap_gpio_dev_attr gpio_dev_attr = {
609 .bank_width = 32,
610 .dbck_flag = true,
611};
612
613/* gpio1 */
614static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
615 { .role = "dbclk", .clk = "gpio1_dbclk" },
616};
617
618static struct omap_hwmod dra7xx_gpio1_hwmod = {
619 .name = "gpio1",
620 .class = &dra7xx_gpio_hwmod_class,
621 .clkdm_name = "wkupaon_clkdm",
622 .main_clk = "wkupaon_iclk_mux",
623 .prcm = {
624 .omap4 = {
625 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
626 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
627 .modulemode = MODULEMODE_HWCTRL,
628 },
629 },
630 .opt_clks = gpio1_opt_clks,
631 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
632 .dev_attr = &gpio_dev_attr,
633};
634
635/* gpio2 */
636static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
637 { .role = "dbclk", .clk = "gpio2_dbclk" },
638};
639
640static struct omap_hwmod dra7xx_gpio2_hwmod = {
641 .name = "gpio2",
642 .class = &dra7xx_gpio_hwmod_class,
643 .clkdm_name = "l4per_clkdm",
644 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
645 .main_clk = "l3_iclk_div",
646 .prcm = {
647 .omap4 = {
648 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
649 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
650 .modulemode = MODULEMODE_HWCTRL,
651 },
652 },
653 .opt_clks = gpio2_opt_clks,
654 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
655 .dev_attr = &gpio_dev_attr,
656};
657
658/* gpio3 */
659static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
660 { .role = "dbclk", .clk = "gpio3_dbclk" },
661};
662
663static struct omap_hwmod dra7xx_gpio3_hwmod = {
664 .name = "gpio3",
665 .class = &dra7xx_gpio_hwmod_class,
666 .clkdm_name = "l4per_clkdm",
667 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
668 .main_clk = "l3_iclk_div",
669 .prcm = {
670 .omap4 = {
671 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
672 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
673 .modulemode = MODULEMODE_HWCTRL,
674 },
675 },
676 .opt_clks = gpio3_opt_clks,
677 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
678 .dev_attr = &gpio_dev_attr,
679};
680
681/* gpio4 */
682static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
683 { .role = "dbclk", .clk = "gpio4_dbclk" },
684};
685
686static struct omap_hwmod dra7xx_gpio4_hwmod = {
687 .name = "gpio4",
688 .class = &dra7xx_gpio_hwmod_class,
689 .clkdm_name = "l4per_clkdm",
690 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
691 .main_clk = "l3_iclk_div",
692 .prcm = {
693 .omap4 = {
694 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
695 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
696 .modulemode = MODULEMODE_HWCTRL,
697 },
698 },
699 .opt_clks = gpio4_opt_clks,
700 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
701 .dev_attr = &gpio_dev_attr,
702};
703
704/* gpio5 */
705static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
706 { .role = "dbclk", .clk = "gpio5_dbclk" },
707};
708
709static struct omap_hwmod dra7xx_gpio5_hwmod = {
710 .name = "gpio5",
711 .class = &dra7xx_gpio_hwmod_class,
712 .clkdm_name = "l4per_clkdm",
713 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
714 .main_clk = "l3_iclk_div",
715 .prcm = {
716 .omap4 = {
717 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
718 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
719 .modulemode = MODULEMODE_HWCTRL,
720 },
721 },
722 .opt_clks = gpio5_opt_clks,
723 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
724 .dev_attr = &gpio_dev_attr,
725};
726
727/* gpio6 */
728static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
729 { .role = "dbclk", .clk = "gpio6_dbclk" },
730};
731
732static struct omap_hwmod dra7xx_gpio6_hwmod = {
733 .name = "gpio6",
734 .class = &dra7xx_gpio_hwmod_class,
735 .clkdm_name = "l4per_clkdm",
736 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
737 .main_clk = "l3_iclk_div",
738 .prcm = {
739 .omap4 = {
740 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
741 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
742 .modulemode = MODULEMODE_HWCTRL,
743 },
744 },
745 .opt_clks = gpio6_opt_clks,
746 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
747 .dev_attr = &gpio_dev_attr,
748};
749
750/* gpio7 */
751static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
752 { .role = "dbclk", .clk = "gpio7_dbclk" },
753};
754
755static struct omap_hwmod dra7xx_gpio7_hwmod = {
756 .name = "gpio7",
757 .class = &dra7xx_gpio_hwmod_class,
758 .clkdm_name = "l4per_clkdm",
759 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
760 .main_clk = "l3_iclk_div",
761 .prcm = {
762 .omap4 = {
763 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
764 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
765 .modulemode = MODULEMODE_HWCTRL,
766 },
767 },
768 .opt_clks = gpio7_opt_clks,
769 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
770 .dev_attr = &gpio_dev_attr,
771};
772
773/* gpio8 */
774static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
775 { .role = "dbclk", .clk = "gpio8_dbclk" },
776};
777
778static struct omap_hwmod dra7xx_gpio8_hwmod = {
779 .name = "gpio8",
780 .class = &dra7xx_gpio_hwmod_class,
781 .clkdm_name = "l4per_clkdm",
782 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
783 .main_clk = "l3_iclk_div",
784 .prcm = {
785 .omap4 = {
786 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
787 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
788 .modulemode = MODULEMODE_HWCTRL,
789 },
790 },
791 .opt_clks = gpio8_opt_clks,
792 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
793 .dev_attr = &gpio_dev_attr,
794};
795
796/*
797 * 'gpmc' class
798 *
799 */
800
801static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
802 .rev_offs = 0x0000,
803 .sysc_offs = 0x0010,
804 .syss_offs = 0x0014,
805 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
806 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
807 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
808 SIDLE_SMART_WKUP),
809 .sysc_fields = &omap_hwmod_sysc_type1,
810};
811
812static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
813 .name = "gpmc",
814 .sysc = &dra7xx_gpmc_sysc,
815};
816
817/* gpmc */
818
819static struct omap_hwmod dra7xx_gpmc_hwmod = {
820 .name = "gpmc",
821 .class = &dra7xx_gpmc_hwmod_class,
822 .clkdm_name = "l3main1_clkdm",
Keerthy556708f2015-01-13 14:21:25 +0530[diff] [blame]823 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
824 HWMOD_SWSUP_SIDLE),
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]825 .main_clk = "l3_iclk_div",
826 .prcm = {
827 .omap4 = {
828 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
829 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
830 .modulemode = MODULEMODE_HWCTRL,
831 },
832 },
833};
834
835/*
836 * 'hdq1w' class
837 *
838 */
839
840static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
841 .rev_offs = 0x0000,
842 .sysc_offs = 0x0014,
843 .syss_offs = 0x0018,
844 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
845 SYSS_HAS_RESET_STATUS),
846 .sysc_fields = &omap_hwmod_sysc_type1,
847};
848
849static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
850 .name = "hdq1w",
851 .sysc = &dra7xx_hdq1w_sysc,
852};
853
854/* hdq1w */
855
856static struct omap_hwmod dra7xx_hdq1w_hwmod = {
857 .name = "hdq1w",
858 .class = &dra7xx_hdq1w_hwmod_class,
859 .clkdm_name = "l4per_clkdm",
860 .flags = HWMOD_INIT_NO_RESET,
861 .main_clk = "func_12m_fclk",
862 .prcm = {
863 .omap4 = {
864 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
865 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
866 .modulemode = MODULEMODE_SWCTRL,
867 },
868 },
869};
870
871/*
872 * 'i2c' class
873 *
874 */
875
876static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
877 .sysc_offs = 0x0010,
878 .syss_offs = 0x0090,
879 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
880 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
881 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
882 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
883 SIDLE_SMART_WKUP),
884 .clockact = CLOCKACT_TEST_ICLK,
885 .sysc_fields = &omap_hwmod_sysc_type1,
886};
887
888static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
889 .name = "i2c",
890 .sysc = &dra7xx_i2c_sysc,
891 .reset = &omap_i2c_reset,
892 .rev = OMAP_I2C_IP_VERSION_2,
893};
894
895/* i2c dev_attr */
896static struct omap_i2c_dev_attr i2c_dev_attr = {
897 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
898};
899
900/* i2c1 */
901static struct omap_hwmod dra7xx_i2c1_hwmod = {
902 .name = "i2c1",
903 .class = &dra7xx_i2c_hwmod_class,
904 .clkdm_name = "l4per_clkdm",
905 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
906 .main_clk = "func_96m_fclk",
907 .prcm = {
908 .omap4 = {
909 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
910 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
911 .modulemode = MODULEMODE_SWCTRL,
912 },
913 },
914 .dev_attr = &i2c_dev_attr,
915};
916
917/* i2c2 */
918static struct omap_hwmod dra7xx_i2c2_hwmod = {
919 .name = "i2c2",
920 .class = &dra7xx_i2c_hwmod_class,
921 .clkdm_name = "l4per_clkdm",
922 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
923 .main_clk = "func_96m_fclk",
924 .prcm = {
925 .omap4 = {
926 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
927 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
928 .modulemode = MODULEMODE_SWCTRL,
929 },
930 },
931 .dev_attr = &i2c_dev_attr,
932};
933
934/* i2c3 */
935static struct omap_hwmod dra7xx_i2c3_hwmod = {
936 .name = "i2c3",
937 .class = &dra7xx_i2c_hwmod_class,
938 .clkdm_name = "l4per_clkdm",
939 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
940 .main_clk = "func_96m_fclk",
941 .prcm = {
942 .omap4 = {
943 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
944 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
945 .modulemode = MODULEMODE_SWCTRL,
946 },
947 },
948 .dev_attr = &i2c_dev_attr,
949};
950
951/* i2c4 */
952static struct omap_hwmod dra7xx_i2c4_hwmod = {
953 .name = "i2c4",
954 .class = &dra7xx_i2c_hwmod_class,
955 .clkdm_name = "l4per_clkdm",
956 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
957 .main_clk = "func_96m_fclk",
958 .prcm = {
959 .omap4 = {
960 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
961 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
962 .modulemode = MODULEMODE_SWCTRL,
963 },
964 },
965 .dev_attr = &i2c_dev_attr,
966};
967
968/* i2c5 */
969static struct omap_hwmod dra7xx_i2c5_hwmod = {
970 .name = "i2c5",
971 .class = &dra7xx_i2c_hwmod_class,
972 .clkdm_name = "ipu_clkdm",
973 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
974 .main_clk = "func_96m_fclk",
975 .prcm = {
976 .omap4 = {
977 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
978 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
979 .modulemode = MODULEMODE_SWCTRL,
980 },
981 },
982 .dev_attr = &i2c_dev_attr,
983};
984
985/*
Suman Anna067395d2014-07-11 16:44:39 -0500[diff] [blame]986 * 'mailbox' class
987 *
988 */
989
990static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
991 .rev_offs = 0x0000,
992 .sysc_offs = 0x0010,
993 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
994 SYSC_HAS_SOFTRESET),
995 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
996 .sysc_fields = &omap_hwmod_sysc_type2,
997};
998
999static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1000 .name = "mailbox",
1001 .sysc = &dra7xx_mailbox_sysc,
1002};
1003
1004/* mailbox1 */
1005static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1006 .name = "mailbox1",
1007 .class = &dra7xx_mailbox_hwmod_class,
1008 .clkdm_name = "l4cfg_clkdm",
1009 .prcm = {
1010 .omap4 = {
1011 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1012 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1013 },
1014 },
1015};
1016
1017/* mailbox2 */
1018static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1019 .name = "mailbox2",
1020 .class = &dra7xx_mailbox_hwmod_class,
1021 .clkdm_name = "l4cfg_clkdm",
1022 .prcm = {
1023 .omap4 = {
1024 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1025 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1026 },
1027 },
1028};
1029
1030/* mailbox3 */
1031static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1032 .name = "mailbox3",
1033 .class = &dra7xx_mailbox_hwmod_class,
1034 .clkdm_name = "l4cfg_clkdm",
1035 .prcm = {
1036 .omap4 = {
1037 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1038 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1039 },
1040 },
1041};
1042
1043/* mailbox4 */
1044static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1045 .name = "mailbox4",
1046 .class = &dra7xx_mailbox_hwmod_class,
1047 .clkdm_name = "l4cfg_clkdm",
1048 .prcm = {
1049 .omap4 = {
1050 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1051 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1052 },
1053 },
1054};
1055
1056/* mailbox5 */
1057static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1058 .name = "mailbox5",
1059 .class = &dra7xx_mailbox_hwmod_class,
1060 .clkdm_name = "l4cfg_clkdm",
1061 .prcm = {
1062 .omap4 = {
1063 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1064 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1065 },
1066 },
1067};
1068
1069/* mailbox6 */
1070static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1071 .name = "mailbox6",
1072 .class = &dra7xx_mailbox_hwmod_class,
1073 .clkdm_name = "l4cfg_clkdm",
1074 .prcm = {
1075 .omap4 = {
1076 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1077 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1078 },
1079 },
1080};
1081
1082/* mailbox7 */
1083static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1084 .name = "mailbox7",
1085 .class = &dra7xx_mailbox_hwmod_class,
1086 .clkdm_name = "l4cfg_clkdm",
1087 .prcm = {
1088 .omap4 = {
1089 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1090 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1091 },
1092 },
1093};
1094
1095/* mailbox8 */
1096static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1097 .name = "mailbox8",
1098 .class = &dra7xx_mailbox_hwmod_class,
1099 .clkdm_name = "l4cfg_clkdm",
1100 .prcm = {
1101 .omap4 = {
1102 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1103 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1104 },
1105 },
1106};
1107
1108/* mailbox9 */
1109static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1110 .name = "mailbox9",
1111 .class = &dra7xx_mailbox_hwmod_class,
1112 .clkdm_name = "l4cfg_clkdm",
1113 .prcm = {
1114 .omap4 = {
1115 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1116 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1117 },
1118 },
1119};
1120
1121/* mailbox10 */
1122static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1123 .name = "mailbox10",
1124 .class = &dra7xx_mailbox_hwmod_class,
1125 .clkdm_name = "l4cfg_clkdm",
1126 .prcm = {
1127 .omap4 = {
1128 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1129 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1130 },
1131 },
1132};
1133
1134/* mailbox11 */
1135static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1136 .name = "mailbox11",
1137 .class = &dra7xx_mailbox_hwmod_class,
1138 .clkdm_name = "l4cfg_clkdm",
1139 .prcm = {
1140 .omap4 = {
1141 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1142 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1143 },
1144 },
1145};
1146
1147/* mailbox12 */
1148static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1149 .name = "mailbox12",
1150 .class = &dra7xx_mailbox_hwmod_class,
1151 .clkdm_name = "l4cfg_clkdm",
1152 .prcm = {
1153 .omap4 = {
1154 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1155 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1156 },
1157 },
1158};
1159
1160/* mailbox13 */
1161static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1162 .name = "mailbox13",
1163 .class = &dra7xx_mailbox_hwmod_class,
1164 .clkdm_name = "l4cfg_clkdm",
1165 .prcm = {
1166 .omap4 = {
1167 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1168 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1169 },
1170 },
1171};
1172
1173/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1174 * 'mcspi' class
1175 *
1176 */
1177
1178static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1179 .rev_offs = 0x0000,
1180 .sysc_offs = 0x0010,
1181 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1182 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1183 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1184 SIDLE_SMART_WKUP),
1185 .sysc_fields = &omap_hwmod_sysc_type2,
1186};
1187
1188static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1189 .name = "mcspi",
1190 .sysc = &dra7xx_mcspi_sysc,
1191 .rev = OMAP4_MCSPI_REV,
1192};
1193
1194/* mcspi1 */
1195/* mcspi1 dev_attr */
1196static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1197 .num_chipselect = 4,
1198};
1199
1200static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1201 .name = "mcspi1",
1202 .class = &dra7xx_mcspi_hwmod_class,
1203 .clkdm_name = "l4per_clkdm",
1204 .main_clk = "func_48m_fclk",
1205 .prcm = {
1206 .omap4 = {
1207 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1208 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1209 .modulemode = MODULEMODE_SWCTRL,
1210 },
1211 },
1212 .dev_attr = &mcspi1_dev_attr,
1213};
1214
1215/* mcspi2 */
1216/* mcspi2 dev_attr */
1217static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1218 .num_chipselect = 2,
1219};
1220
1221static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1222 .name = "mcspi2",
1223 .class = &dra7xx_mcspi_hwmod_class,
1224 .clkdm_name = "l4per_clkdm",
1225 .main_clk = "func_48m_fclk",
1226 .prcm = {
1227 .omap4 = {
1228 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1229 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1230 .modulemode = MODULEMODE_SWCTRL,
1231 },
1232 },
1233 .dev_attr = &mcspi2_dev_attr,
1234};
1235
1236/* mcspi3 */
1237/* mcspi3 dev_attr */
1238static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1239 .num_chipselect = 2,
1240};
1241
1242static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1243 .name = "mcspi3",
1244 .class = &dra7xx_mcspi_hwmod_class,
1245 .clkdm_name = "l4per_clkdm",
1246 .main_clk = "func_48m_fclk",
1247 .prcm = {
1248 .omap4 = {
1249 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1250 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1251 .modulemode = MODULEMODE_SWCTRL,
1252 },
1253 },
1254 .dev_attr = &mcspi3_dev_attr,
1255};
1256
1257/* mcspi4 */
1258/* mcspi4 dev_attr */
1259static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1260 .num_chipselect = 1,
1261};
1262
1263static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1264 .name = "mcspi4",
1265 .class = &dra7xx_mcspi_hwmod_class,
1266 .clkdm_name = "l4per_clkdm",
1267 .main_clk = "func_48m_fclk",
1268 .prcm = {
1269 .omap4 = {
1270 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1271 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1272 .modulemode = MODULEMODE_SWCTRL,
1273 },
1274 },
1275 .dev_attr = &mcspi4_dev_attr,
1276};
1277
1278/*
1279 * 'mmc' class
1280 *
1281 */
1282
1283static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1284 .rev_offs = 0x0000,
1285 .sysc_offs = 0x0010,
1286 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1287 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1288 SYSC_HAS_SOFTRESET),
1289 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1290 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1291 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1292 .sysc_fields = &omap_hwmod_sysc_type2,
1293};
1294
1295static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1296 .name = "mmc",
1297 .sysc = &dra7xx_mmc_sysc,
1298};
1299
1300/* mmc1 */
1301static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1302 { .role = "clk32k", .clk = "mmc1_clk32k" },
1303};
1304
1305/* mmc1 dev_attr */
Andreas Fenkart551434382014-11-08 15:33:09 +0100[diff] [blame]1306static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1307 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1308};
1309
1310static struct omap_hwmod dra7xx_mmc1_hwmod = {
1311 .name = "mmc1",
1312 .class = &dra7xx_mmc_hwmod_class,
1313 .clkdm_name = "l3init_clkdm",
1314 .main_clk = "mmc1_fclk_div",
1315 .prcm = {
1316 .omap4 = {
1317 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1318 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1319 .modulemode = MODULEMODE_SWCTRL,
1320 },
1321 },
1322 .opt_clks = mmc1_opt_clks,
1323 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1324 .dev_attr = &mmc1_dev_attr,
1325};
1326
1327/* mmc2 */
1328static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1329 { .role = "clk32k", .clk = "mmc2_clk32k" },
1330};
1331
1332static struct omap_hwmod dra7xx_mmc2_hwmod = {
1333 .name = "mmc2",
1334 .class = &dra7xx_mmc_hwmod_class,
1335 .clkdm_name = "l3init_clkdm",
1336 .main_clk = "mmc2_fclk_div",
1337 .prcm = {
1338 .omap4 = {
1339 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1340 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1341 .modulemode = MODULEMODE_SWCTRL,
1342 },
1343 },
1344 .opt_clks = mmc2_opt_clks,
1345 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1346};
1347
1348/* mmc3 */
1349static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1350 { .role = "clk32k", .clk = "mmc3_clk32k" },
1351};
1352
1353static struct omap_hwmod dra7xx_mmc3_hwmod = {
1354 .name = "mmc3",
1355 .class = &dra7xx_mmc_hwmod_class,
1356 .clkdm_name = "l4per_clkdm",
1357 .main_clk = "mmc3_gfclk_div",
1358 .prcm = {
1359 .omap4 = {
1360 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1361 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1362 .modulemode = MODULEMODE_SWCTRL,
1363 },
1364 },
1365 .opt_clks = mmc3_opt_clks,
1366 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1367};
1368
1369/* mmc4 */
1370static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1371 { .role = "clk32k", .clk = "mmc4_clk32k" },
1372};
1373
1374static struct omap_hwmod dra7xx_mmc4_hwmod = {
1375 .name = "mmc4",
1376 .class = &dra7xx_mmc_hwmod_class,
1377 .clkdm_name = "l4per_clkdm",
1378 .main_clk = "mmc4_gfclk_div",
1379 .prcm = {
1380 .omap4 = {
1381 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1382 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1383 .modulemode = MODULEMODE_SWCTRL,
1384 },
1385 },
1386 .opt_clks = mmc4_opt_clks,
1387 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1388};
1389
1390/*
1391 * 'mpu' class
1392 *
1393 */
1394
1395static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1396 .name = "mpu",
1397};
1398
1399/* mpu */
1400static struct omap_hwmod dra7xx_mpu_hwmod = {
1401 .name = "mpu",
1402 .class = &dra7xx_mpu_hwmod_class,
1403 .clkdm_name = "mpu_clkdm",
1404 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1405 .main_clk = "dpll_mpu_m2_ck",
1406 .prcm = {
1407 .omap4 = {
1408 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1409 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1410 },
1411 },
1412};
1413
1414/*
1415 * 'ocp2scp' class
1416 *
1417 */
1418
1419static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1420 .rev_offs = 0x0000,
1421 .sysc_offs = 0x0010,
1422 .syss_offs = 0x0014,
1423 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1424 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1425 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1426 SIDLE_SMART_WKUP),
1427 .sysc_fields = &omap_hwmod_sysc_type1,
1428};
1429
1430static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1431 .name = "ocp2scp",
1432 .sysc = &dra7xx_ocp2scp_sysc,
1433};
1434
1435/* ocp2scp1 */
1436static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1437 .name = "ocp2scp1",
1438 .class = &dra7xx_ocp2scp_hwmod_class,
1439 .clkdm_name = "l3init_clkdm",
1440 .main_clk = "l4_root_clk_div",
1441 .prcm = {
1442 .omap4 = {
1443 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1444 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1445 .modulemode = MODULEMODE_HWCTRL,
1446 },
1447 },
1448};
1449
Roger Quadrosdf0d0f12014-07-05 17:44:58 -0600[diff] [blame]1450/* ocp2scp3 */
1451static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1452 .name = "ocp2scp3",
1453 .class = &dra7xx_ocp2scp_hwmod_class,
1454 .clkdm_name = "l3init_clkdm",
1455 .main_clk = "l4_root_clk_div",
1456 .prcm = {
1457 .omap4 = {
1458 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1459 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1460 .modulemode = MODULEMODE_HWCTRL,
1461 },
1462 },
1463};
1464
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1465/*
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1466 * 'PCIE' class
1467 *
1468 */
1469
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1470static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1471 .name = "pcie",
1472};
1473
1474/* pcie1 */
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1475static struct omap_hwmod dra7xx_pciess1_hwmod = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1476 .name = "pcie1",
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1477 .class = &dra7xx_pciess_hwmod_class,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1478 .clkdm_name = "pcie_clkdm",
1479 .main_clk = "l4_root_clk_div",
1480 .prcm = {
1481 .omap4 = {
Kishon Vijay Abraham I70c18ef72014-06-25 23:32:45 +0530[diff] [blame]1482 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1483 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1484 .modulemode = MODULEMODE_SWCTRL,
1485 },
1486 },
1487};
1488
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1489/* pcie2 */
1490static struct omap_hwmod dra7xx_pciess2_hwmod = {
1491 .name = "pcie2",
1492 .class = &dra7xx_pciess_hwmod_class,
1493 .clkdm_name = "pcie_clkdm",
Kishon Vijay Abraham I70c18ef72014-06-25 23:32:45 +0530[diff] [blame]1494 .main_clk = "l4_root_clk_div",
1495 .prcm = {
1496 .omap4 = {
1497 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1498 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1499 .modulemode = MODULEMODE_SWCTRL,
1500 },
1501 },
1502};
1503
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1504/*
1505 * 'qspi' class
1506 *
1507 */
1508
1509static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1510 .sysc_offs = 0x0010,
1511 .sysc_flags = SYSC_HAS_SIDLEMODE,
1512 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1513 SIDLE_SMART_WKUP),
1514 .sysc_fields = &omap_hwmod_sysc_type2,
1515};
1516
1517static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1518 .name = "qspi",
1519 .sysc = &dra7xx_qspi_sysc,
1520};
1521
1522/* qspi */
1523static struct omap_hwmod dra7xx_qspi_hwmod = {
1524 .name = "qspi",
1525 .class = &dra7xx_qspi_hwmod_class,
1526 .clkdm_name = "l4per2_clkdm",
1527 .main_clk = "qspi_gfclk_div",
1528 .prcm = {
1529 .omap4 = {
1530 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1531 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1532 .modulemode = MODULEMODE_SWCTRL,
1533 },
1534 },
1535};
1536
1537/*
Lokesh Vutlac913c8a2014-07-22 13:15:57 -0600[diff] [blame]1538 * 'rtcss' class
1539 *
1540 */
1541static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1542 .sysc_offs = 0x0078,
1543 .sysc_flags = SYSC_HAS_SIDLEMODE,
1544 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1545 SIDLE_SMART_WKUP),
1546 .sysc_fields = &omap_hwmod_sysc_type3,
1547};
1548
1549static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1550 .name = "rtcss",
1551 .sysc = &dra7xx_rtcss_sysc,
1552};
1553
1554/* rtcss */
1555static struct omap_hwmod dra7xx_rtcss_hwmod = {
1556 .name = "rtcss",
1557 .class = &dra7xx_rtcss_hwmod_class,
1558 .clkdm_name = "rtc_clkdm",
1559 .main_clk = "sys_32k_ck",
1560 .prcm = {
1561 .omap4 = {
1562 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1563 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1564 .modulemode = MODULEMODE_SWCTRL,
1565 },
1566 },
1567};
1568
1569/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1570 * 'sata' class
1571 *
1572 */
1573
1574static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1575 .sysc_offs = 0x0000,
1576 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1577 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1578 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1579 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1580 .sysc_fields = &omap_hwmod_sysc_type2,
1581};
1582
1583static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1584 .name = "sata",
1585 .sysc = &dra7xx_sata_sysc,
1586};
1587
1588/* sata */
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1589
1590static struct omap_hwmod dra7xx_sata_hwmod = {
1591 .name = "sata",
1592 .class = &dra7xx_sata_hwmod_class,
1593 .clkdm_name = "l3init_clkdm",
1594 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1595 .main_clk = "func_48m_fclk",
Roger Quadros1ea09992014-07-06 15:51:24 -0600[diff] [blame]1596 .mpu_rt_idx = 1,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1597 .prcm = {
1598 .omap4 = {
1599 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1600 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1601 .modulemode = MODULEMODE_SWCTRL,
1602 },
1603 },
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1604};
1605
1606/*
1607 * 'smartreflex' class
1608 *
1609 */
1610
1611/* The IP is not compliant to type1 / type2 scheme */
1612static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1613 .sidle_shift = 24,
1614 .enwkup_shift = 26,
1615};
1616
1617static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1618 .sysc_offs = 0x0038,
1619 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1620 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1621 SIDLE_SMART_WKUP),
1622 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1623};
1624
1625static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1626 .name = "smartreflex",
1627 .sysc = &dra7xx_smartreflex_sysc,
1628 .rev = 2,
1629};
1630
1631/* smartreflex_core */
1632/* smartreflex_core dev_attr */
1633static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1634 .sensor_voltdm_name = "core",
1635};
1636
1637static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1638 .name = "smartreflex_core",
1639 .class = &dra7xx_smartreflex_hwmod_class,
1640 .clkdm_name = "coreaon_clkdm",
1641 .main_clk = "wkupaon_iclk_mux",
1642 .prcm = {
1643 .omap4 = {
1644 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1645 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1646 .modulemode = MODULEMODE_SWCTRL,
1647 },
1648 },
1649 .dev_attr = &smartreflex_core_dev_attr,
1650};
1651
1652/* smartreflex_mpu */
1653/* smartreflex_mpu dev_attr */
1654static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1655 .sensor_voltdm_name = "mpu",
1656};
1657
1658static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1659 .name = "smartreflex_mpu",
1660 .class = &dra7xx_smartreflex_hwmod_class,
1661 .clkdm_name = "coreaon_clkdm",
1662 .main_clk = "wkupaon_iclk_mux",
1663 .prcm = {
1664 .omap4 = {
1665 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1666 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1667 .modulemode = MODULEMODE_SWCTRL,
1668 },
1669 },
1670 .dev_attr = &smartreflex_mpu_dev_attr,
1671};
1672
1673/*
1674 * 'spinlock' class
1675 *
1676 */
1677
1678static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1679 .rev_offs = 0x0000,
1680 .sysc_offs = 0x0010,
1681 .syss_offs = 0x0014,
Suman Annac317d0f2014-01-10 17:43:08 -0600[diff] [blame]1682 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1683 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1684 SYSS_HAS_RESET_STATUS),
1685 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1686 .sysc_fields = &omap_hwmod_sysc_type1,
1687};
1688
1689static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1690 .name = "spinlock",
1691 .sysc = &dra7xx_spinlock_sysc,
1692};
1693
1694/* spinlock */
1695static struct omap_hwmod dra7xx_spinlock_hwmod = {
1696 .name = "spinlock",
1697 .class = &dra7xx_spinlock_hwmod_class,
1698 .clkdm_name = "l4cfg_clkdm",
1699 .main_clk = "l3_iclk_div",
1700 .prcm = {
1701 .omap4 = {
1702 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1703 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1704 },
1705 },
1706};
1707
1708/*
1709 * 'timer' class
1710 *
1711 * This class contains several variants: ['timer_1ms', 'timer_secure',
1712 * 'timer']
1713 */
1714
1715static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1716 .rev_offs = 0x0000,
1717 .sysc_offs = 0x0010,
1718 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1719 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1720 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1721 SIDLE_SMART_WKUP),
1722 .sysc_fields = &omap_hwmod_sysc_type2,
1723};
1724
1725static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1726 .name = "timer",
1727 .sysc = &dra7xx_timer_1ms_sysc,
1728};
1729
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1730static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1731 .rev_offs = 0x0000,
1732 .sysc_offs = 0x0010,
1733 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1734 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1735 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1736 SIDLE_SMART_WKUP),
1737 .sysc_fields = &omap_hwmod_sysc_type2,
1738};
1739
1740static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1741 .name = "timer",
1742 .sysc = &dra7xx_timer_sysc,
1743};
1744
1745/* timer1 */
1746static struct omap_hwmod dra7xx_timer1_hwmod = {
1747 .name = "timer1",
1748 .class = &dra7xx_timer_1ms_hwmod_class,
1749 .clkdm_name = "wkupaon_clkdm",
1750 .main_clk = "timer1_gfclk_mux",
1751 .prcm = {
1752 .omap4 = {
1753 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1754 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1755 .modulemode = MODULEMODE_SWCTRL,
1756 },
1757 },
1758};
1759
1760/* timer2 */
1761static struct omap_hwmod dra7xx_timer2_hwmod = {
1762 .name = "timer2",
1763 .class = &dra7xx_timer_1ms_hwmod_class,
1764 .clkdm_name = "l4per_clkdm",
1765 .main_clk = "timer2_gfclk_mux",
1766 .prcm = {
1767 .omap4 = {
1768 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1769 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1770 .modulemode = MODULEMODE_SWCTRL,
1771 },
1772 },
1773};
1774
1775/* timer3 */
1776static struct omap_hwmod dra7xx_timer3_hwmod = {
1777 .name = "timer3",
1778 .class = &dra7xx_timer_hwmod_class,
1779 .clkdm_name = "l4per_clkdm",
1780 .main_clk = "timer3_gfclk_mux",
1781 .prcm = {
1782 .omap4 = {
1783 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1784 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1785 .modulemode = MODULEMODE_SWCTRL,
1786 },
1787 },
1788};
1789
1790/* timer4 */
1791static struct omap_hwmod dra7xx_timer4_hwmod = {
1792 .name = "timer4",
Suman Annaedec1782015-03-16 15:54:54 -0500[diff] [blame]1793 .class = &dra7xx_timer_hwmod_class,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1794 .clkdm_name = "l4per_clkdm",
1795 .main_clk = "timer4_gfclk_mux",
1796 .prcm = {
1797 .omap4 = {
1798 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1799 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1800 .modulemode = MODULEMODE_SWCTRL,
1801 },
1802 },
1803};
1804
1805/* timer5 */
1806static struct omap_hwmod dra7xx_timer5_hwmod = {
1807 .name = "timer5",
1808 .class = &dra7xx_timer_hwmod_class,
1809 .clkdm_name = "ipu_clkdm",
1810 .main_clk = "timer5_gfclk_mux",
1811 .prcm = {
1812 .omap4 = {
1813 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1814 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1815 .modulemode = MODULEMODE_SWCTRL,
1816 },
1817 },
1818};
1819
1820/* timer6 */
1821static struct omap_hwmod dra7xx_timer6_hwmod = {
1822 .name = "timer6",
1823 .class = &dra7xx_timer_hwmod_class,
1824 .clkdm_name = "ipu_clkdm",
1825 .main_clk = "timer6_gfclk_mux",
1826 .prcm = {
1827 .omap4 = {
1828 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1829 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1830 .modulemode = MODULEMODE_SWCTRL,
1831 },
1832 },
1833};
1834
1835/* timer7 */
1836static struct omap_hwmod dra7xx_timer7_hwmod = {
1837 .name = "timer7",
1838 .class = &dra7xx_timer_hwmod_class,
1839 .clkdm_name = "ipu_clkdm",
1840 .main_clk = "timer7_gfclk_mux",
1841 .prcm = {
1842 .omap4 = {
1843 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1844 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1845 .modulemode = MODULEMODE_SWCTRL,
1846 },
1847 },
1848};
1849
1850/* timer8 */
1851static struct omap_hwmod dra7xx_timer8_hwmod = {
1852 .name = "timer8",
1853 .class = &dra7xx_timer_hwmod_class,
1854 .clkdm_name = "ipu_clkdm",
1855 .main_clk = "timer8_gfclk_mux",
1856 .prcm = {
1857 .omap4 = {
1858 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1859 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1860 .modulemode = MODULEMODE_SWCTRL,
1861 },
1862 },
1863};
1864
1865/* timer9 */
1866static struct omap_hwmod dra7xx_timer9_hwmod = {
1867 .name = "timer9",
1868 .class = &dra7xx_timer_hwmod_class,
1869 .clkdm_name = "l4per_clkdm",
1870 .main_clk = "timer9_gfclk_mux",
1871 .prcm = {
1872 .omap4 = {
1873 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1874 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1875 .modulemode = MODULEMODE_SWCTRL,
1876 },
1877 },
1878};
1879
1880/* timer10 */
1881static struct omap_hwmod dra7xx_timer10_hwmod = {
1882 .name = "timer10",
1883 .class = &dra7xx_timer_1ms_hwmod_class,
1884 .clkdm_name = "l4per_clkdm",
1885 .main_clk = "timer10_gfclk_mux",
1886 .prcm = {
1887 .omap4 = {
1888 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1889 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1890 .modulemode = MODULEMODE_SWCTRL,
1891 },
1892 },
1893};
1894
1895/* timer11 */
1896static struct omap_hwmod dra7xx_timer11_hwmod = {
1897 .name = "timer11",
1898 .class = &dra7xx_timer_hwmod_class,
1899 .clkdm_name = "l4per_clkdm",
1900 .main_clk = "timer11_gfclk_mux",
1901 .prcm = {
1902 .omap4 = {
1903 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1904 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1905 .modulemode = MODULEMODE_SWCTRL,
1906 },
1907 },
1908};
1909
Suman Anna1ac964f2015-03-16 15:54:53 -0500[diff] [blame]1910/* timer13 */
1911static struct omap_hwmod dra7xx_timer13_hwmod = {
1912 .name = "timer13",
1913 .class = &dra7xx_timer_hwmod_class,
1914 .clkdm_name = "l4per3_clkdm",
1915 .main_clk = "timer13_gfclk_mux",
1916 .prcm = {
1917 .omap4 = {
1918 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
1919 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
1920 .modulemode = MODULEMODE_SWCTRL,
1921 },
1922 },
1923};
1924
1925/* timer14 */
1926static struct omap_hwmod dra7xx_timer14_hwmod = {
1927 .name = "timer14",
1928 .class = &dra7xx_timer_hwmod_class,
1929 .clkdm_name = "l4per3_clkdm",
1930 .main_clk = "timer14_gfclk_mux",
1931 .prcm = {
1932 .omap4 = {
1933 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
1934 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
1935 .modulemode = MODULEMODE_SWCTRL,
1936 },
1937 },
1938};
1939
1940/* timer15 */
1941static struct omap_hwmod dra7xx_timer15_hwmod = {
1942 .name = "timer15",
1943 .class = &dra7xx_timer_hwmod_class,
1944 .clkdm_name = "l4per3_clkdm",
1945 .main_clk = "timer15_gfclk_mux",
1946 .prcm = {
1947 .omap4 = {
1948 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
1949 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
1950 .modulemode = MODULEMODE_SWCTRL,
1951 },
1952 },
1953};
1954
1955/* timer16 */
1956static struct omap_hwmod dra7xx_timer16_hwmod = {
1957 .name = "timer16",
1958 .class = &dra7xx_timer_hwmod_class,
1959 .clkdm_name = "l4per3_clkdm",
1960 .main_clk = "timer16_gfclk_mux",
1961 .prcm = {
1962 .omap4 = {
1963 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
1964 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
1965 .modulemode = MODULEMODE_SWCTRL,
1966 },
1967 },
1968};
1969
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1970/*
1971 * 'uart' class
1972 *
1973 */
1974
1975static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1976 .rev_offs = 0x0050,
1977 .sysc_offs = 0x0054,
1978 .syss_offs = 0x0058,
1979 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1980 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1981 SYSS_HAS_RESET_STATUS),
1982 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1983 SIDLE_SMART_WKUP),
1984 .sysc_fields = &omap_hwmod_sysc_type1,
1985};
1986
1987static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1988 .name = "uart",
1989 .sysc = &dra7xx_uart_sysc,
1990};
1991
1992/* uart1 */
1993static struct omap_hwmod dra7xx_uart1_hwmod = {
1994 .name = "uart1",
1995 .class = &dra7xx_uart_hwmod_class,
1996 .clkdm_name = "l4per_clkdm",
1997 .main_clk = "uart1_gfclk_mux",
Rajendra Nayak38958c12013-12-12 15:22:49 +0530[diff] [blame]1998 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1999 .prcm = {
2000 .omap4 = {
2001 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2002 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2003 .modulemode = MODULEMODE_SWCTRL,
2004 },
2005 },
2006};
2007
2008/* uart2 */
2009static struct omap_hwmod dra7xx_uart2_hwmod = {
2010 .name = "uart2",
2011 .class = &dra7xx_uart_hwmod_class,
2012 .clkdm_name = "l4per_clkdm",
2013 .main_clk = "uart2_gfclk_mux",
2014 .flags = HWMOD_SWSUP_SIDLE_ACT,
2015 .prcm = {
2016 .omap4 = {
2017 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2018 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2019 .modulemode = MODULEMODE_SWCTRL,
2020 },
2021 },
2022};
2023
2024/* uart3 */
2025static struct omap_hwmod dra7xx_uart3_hwmod = {
2026 .name = "uart3",
2027 .class = &dra7xx_uart_hwmod_class,
2028 .clkdm_name = "l4per_clkdm",
2029 .main_clk = "uart3_gfclk_mux",
Lokesh Vutla1c7e36b2015-01-08 17:22:04 +0530[diff] [blame]2030 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2031 .prcm = {
2032 .omap4 = {
2033 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2034 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2035 .modulemode = MODULEMODE_SWCTRL,
2036 },
2037 },
2038};
2039
2040/* uart4 */
2041static struct omap_hwmod dra7xx_uart4_hwmod = {
2042 .name = "uart4",
2043 .class = &dra7xx_uart_hwmod_class,
2044 .clkdm_name = "l4per_clkdm",
2045 .main_clk = "uart4_gfclk_mux",
2046 .flags = HWMOD_SWSUP_SIDLE_ACT,
2047 .prcm = {
2048 .omap4 = {
2049 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2050 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2051 .modulemode = MODULEMODE_SWCTRL,
2052 },
2053 },
2054};
2055
2056/* uart5 */
2057static struct omap_hwmod dra7xx_uart5_hwmod = {
2058 .name = "uart5",
2059 .class = &dra7xx_uart_hwmod_class,
2060 .clkdm_name = "l4per_clkdm",
2061 .main_clk = "uart5_gfclk_mux",
2062 .flags = HWMOD_SWSUP_SIDLE_ACT,
2063 .prcm = {
2064 .omap4 = {
2065 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2066 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2067 .modulemode = MODULEMODE_SWCTRL,
2068 },
2069 },
2070};
2071
2072/* uart6 */
2073static struct omap_hwmod dra7xx_uart6_hwmod = {
2074 .name = "uart6",
2075 .class = &dra7xx_uart_hwmod_class,
2076 .clkdm_name = "ipu_clkdm",
2077 .main_clk = "uart6_gfclk_mux",
2078 .flags = HWMOD_SWSUP_SIDLE_ACT,
2079 .prcm = {
2080 .omap4 = {
2081 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2082 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2083 .modulemode = MODULEMODE_SWCTRL,
2084 },
2085 },
2086};
2087
Ambresh K33acc9f2014-10-21 11:17:51 -0500[diff] [blame]2088/* uart7 */
2089static struct omap_hwmod dra7xx_uart7_hwmod = {
2090 .name = "uart7",
2091 .class = &dra7xx_uart_hwmod_class,
2092 .clkdm_name = "l4per2_clkdm",
2093 .main_clk = "uart7_gfclk_mux",
2094 .flags = HWMOD_SWSUP_SIDLE_ACT,
2095 .prcm = {
2096 .omap4 = {
2097 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2098 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2099 .modulemode = MODULEMODE_SWCTRL,
2100 },
2101 },
2102};
2103
2104/* uart8 */
2105static struct omap_hwmod dra7xx_uart8_hwmod = {
2106 .name = "uart8",
2107 .class = &dra7xx_uart_hwmod_class,
2108 .clkdm_name = "l4per2_clkdm",
2109 .main_clk = "uart8_gfclk_mux",
2110 .flags = HWMOD_SWSUP_SIDLE_ACT,
2111 .prcm = {
2112 .omap4 = {
2113 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2114 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2115 .modulemode = MODULEMODE_SWCTRL,
2116 },
2117 },
2118};
2119
2120/* uart9 */
2121static struct omap_hwmod dra7xx_uart9_hwmod = {
2122 .name = "uart9",
2123 .class = &dra7xx_uart_hwmod_class,
2124 .clkdm_name = "l4per2_clkdm",
2125 .main_clk = "uart9_gfclk_mux",
2126 .flags = HWMOD_SWSUP_SIDLE_ACT,
2127 .prcm = {
2128 .omap4 = {
2129 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2130 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2131 .modulemode = MODULEMODE_SWCTRL,
2132 },
2133 },
2134};
2135
2136/* uart10 */
2137static struct omap_hwmod dra7xx_uart10_hwmod = {
2138 .name = "uart10",
2139 .class = &dra7xx_uart_hwmod_class,
2140 .clkdm_name = "wkupaon_clkdm",
2141 .main_clk = "uart10_gfclk_mux",
2142 .flags = HWMOD_SWSUP_SIDLE_ACT,
2143 .prcm = {
2144 .omap4 = {
2145 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2146 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2147 .modulemode = MODULEMODE_SWCTRL,
2148 },
2149 },
2150};
2151
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2152/*
2153 * 'usb_otg_ss' class
2154 *
2155 */
2156
Roger Quadrosd904b382014-07-06 15:51:24 -0600[diff] [blame]2157static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2158 .rev_offs = 0x0000,
2159 .sysc_offs = 0x0010,
2160 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2161 SYSC_HAS_SIDLEMODE),
2162 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2163 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2164 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2165 .sysc_fields = &omap_hwmod_sysc_type2,
2166};
2167
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2168static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2169 .name = "usb_otg_ss",
Roger Quadrosd904b382014-07-06 15:51:24 -0600[diff] [blame]2170 .sysc = &dra7xx_usb_otg_ss_sysc,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2171};
2172
2173/* usb_otg_ss1 */
2174static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2175 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2176};
2177
2178static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2179 .name = "usb_otg_ss1",
2180 .class = &dra7xx_usb_otg_ss_hwmod_class,
2181 .clkdm_name = "l3init_clkdm",
2182 .main_clk = "dpll_core_h13x2_ck",
2183 .prcm = {
2184 .omap4 = {
2185 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2186 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2187 .modulemode = MODULEMODE_HWCTRL,
2188 },
2189 },
2190 .opt_clks = usb_otg_ss1_opt_clks,
2191 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2192};
2193
2194/* usb_otg_ss2 */
2195static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2196 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2197};
2198
2199static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2200 .name = "usb_otg_ss2",
2201 .class = &dra7xx_usb_otg_ss_hwmod_class,
2202 .clkdm_name = "l3init_clkdm",
2203 .main_clk = "dpll_core_h13x2_ck",
2204 .prcm = {
2205 .omap4 = {
2206 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2207 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2208 .modulemode = MODULEMODE_HWCTRL,
2209 },
2210 },
2211 .opt_clks = usb_otg_ss2_opt_clks,
2212 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2213};
2214
2215/* usb_otg_ss3 */
2216static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2217 .name = "usb_otg_ss3",
2218 .class = &dra7xx_usb_otg_ss_hwmod_class,
2219 .clkdm_name = "l3init_clkdm",
2220 .main_clk = "dpll_core_h13x2_ck",
2221 .prcm = {
2222 .omap4 = {
2223 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2224 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2225 .modulemode = MODULEMODE_HWCTRL,
2226 },
2227 },
2228};
2229
2230/* usb_otg_ss4 */
2231static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2232 .name = "usb_otg_ss4",
2233 .class = &dra7xx_usb_otg_ss_hwmod_class,
2234 .clkdm_name = "l3init_clkdm",
2235 .main_clk = "dpll_core_h13x2_ck",
2236 .prcm = {
2237 .omap4 = {
2238 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2239 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2240 .modulemode = MODULEMODE_HWCTRL,
2241 },
2242 },
2243};
2244
2245/*
2246 * 'vcp' class
2247 *
2248 */
2249
2250static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2251 .name = "vcp",
2252};
2253
2254/* vcp1 */
2255static struct omap_hwmod dra7xx_vcp1_hwmod = {
2256 .name = "vcp1",
2257 .class = &dra7xx_vcp_hwmod_class,
2258 .clkdm_name = "l3main1_clkdm",
2259 .main_clk = "l3_iclk_div",
2260 .prcm = {
2261 .omap4 = {
2262 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2263 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2264 },
2265 },
2266};
2267
2268/* vcp2 */
2269static struct omap_hwmod dra7xx_vcp2_hwmod = {
2270 .name = "vcp2",
2271 .class = &dra7xx_vcp_hwmod_class,
2272 .clkdm_name = "l3main1_clkdm",
2273 .main_clk = "l3_iclk_div",
2274 .prcm = {
2275 .omap4 = {
2276 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2277 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2278 },
2279 },
2280};
2281
2282/*
2283 * 'wd_timer' class
2284 *
2285 */
2286
2287static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2288 .rev_offs = 0x0000,
2289 .sysc_offs = 0x0010,
2290 .syss_offs = 0x0014,
2291 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2292 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2293 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2294 SIDLE_SMART_WKUP),
2295 .sysc_fields = &omap_hwmod_sysc_type1,
2296};
2297
2298static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2299 .name = "wd_timer",
2300 .sysc = &dra7xx_wd_timer_sysc,
2301 .pre_shutdown = &omap2_wd_timer_disable,
2302 .reset = &omap2_wd_timer_reset,
2303};
2304
2305/* wd_timer2 */
2306static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2307 .name = "wd_timer2",
2308 .class = &dra7xx_wd_timer_hwmod_class,
2309 .clkdm_name = "wkupaon_clkdm",
2310 .main_clk = "sys_32k_ck",
2311 .prcm = {
2312 .omap4 = {
2313 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2314 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2315 .modulemode = MODULEMODE_SWCTRL,
2316 },
2317 },
2318};
2319
2320
2321/*
2322 * Interfaces
2323 */
2324
2325/* l3_main_2 -> l3_instr */
2326static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2327 .master = &dra7xx_l3_main_2_hwmod,
2328 .slave = &dra7xx_l3_instr_hwmod,
2329 .clk = "l3_iclk_div",
2330 .user = OCP_USER_MPU | OCP_USER_SDMA,
2331};
2332
2333/* l4_cfg -> l3_main_1 */
2334static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2335 .master = &dra7xx_l4_cfg_hwmod,
2336 .slave = &dra7xx_l3_main_1_hwmod,
2337 .clk = "l3_iclk_div",
2338 .user = OCP_USER_MPU | OCP_USER_SDMA,
2339};
2340
2341/* mpu -> l3_main_1 */
2342static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2343 .master = &dra7xx_mpu_hwmod,
2344 .slave = &dra7xx_l3_main_1_hwmod,
2345 .clk = "l3_iclk_div",
2346 .user = OCP_USER_MPU,
2347};
2348
2349/* l3_main_1 -> l3_main_2 */
2350static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2351 .master = &dra7xx_l3_main_1_hwmod,
2352 .slave = &dra7xx_l3_main_2_hwmod,
2353 .clk = "l3_iclk_div",
2354 .user = OCP_USER_MPU,
2355};
2356
2357/* l4_cfg -> l3_main_2 */
2358static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2359 .master = &dra7xx_l4_cfg_hwmod,
2360 .slave = &dra7xx_l3_main_2_hwmod,
2361 .clk = "l3_iclk_div",
2362 .user = OCP_USER_MPU | OCP_USER_SDMA,
2363};
2364
2365/* l3_main_1 -> l4_cfg */
2366static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2367 .master = &dra7xx_l3_main_1_hwmod,
2368 .slave = &dra7xx_l4_cfg_hwmod,
2369 .clk = "l3_iclk_div",
2370 .user = OCP_USER_MPU | OCP_USER_SDMA,
2371};
2372
2373/* l3_main_1 -> l4_per1 */
2374static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2375 .master = &dra7xx_l3_main_1_hwmod,
2376 .slave = &dra7xx_l4_per1_hwmod,
2377 .clk = "l3_iclk_div",
2378 .user = OCP_USER_MPU | OCP_USER_SDMA,
2379};
2380
2381/* l3_main_1 -> l4_per2 */
2382static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2383 .master = &dra7xx_l3_main_1_hwmod,
2384 .slave = &dra7xx_l4_per2_hwmod,
2385 .clk = "l3_iclk_div",
2386 .user = OCP_USER_MPU | OCP_USER_SDMA,
2387};
2388
2389/* l3_main_1 -> l4_per3 */
2390static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2391 .master = &dra7xx_l3_main_1_hwmod,
2392 .slave = &dra7xx_l4_per3_hwmod,
2393 .clk = "l3_iclk_div",
2394 .user = OCP_USER_MPU | OCP_USER_SDMA,
2395};
2396
2397/* l3_main_1 -> l4_wkup */
2398static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2399 .master = &dra7xx_l3_main_1_hwmod,
2400 .slave = &dra7xx_l4_wkup_hwmod,
2401 .clk = "wkupaon_iclk_mux",
2402 .user = OCP_USER_MPU | OCP_USER_SDMA,
2403};
2404
2405/* l4_per2 -> atl */
2406static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2407 .master = &dra7xx_l4_per2_hwmod,
2408 .slave = &dra7xx_atl_hwmod,
2409 .clk = "l3_iclk_div",
2410 .user = OCP_USER_MPU | OCP_USER_SDMA,
2411};
2412
2413/* l3_main_1 -> bb2d */
2414static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2415 .master = &dra7xx_l3_main_1_hwmod,
2416 .slave = &dra7xx_bb2d_hwmod,
2417 .clk = "l3_iclk_div",
2418 .user = OCP_USER_MPU | OCP_USER_SDMA,
2419};
2420
2421/* l4_wkup -> counter_32k */
2422static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2423 .master = &dra7xx_l4_wkup_hwmod,
2424 .slave = &dra7xx_counter_32k_hwmod,
2425 .clk = "wkupaon_iclk_mux",
2426 .user = OCP_USER_MPU | OCP_USER_SDMA,
2427};
2428
2429/* l4_wkup -> ctrl_module_wkup */
2430static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2431 .master = &dra7xx_l4_wkup_hwmod,
2432 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2433 .clk = "wkupaon_iclk_mux",
2434 .user = OCP_USER_MPU | OCP_USER_SDMA,
2435};
2436
Mugunthan V N077c42f2014-07-08 18:46:39 +0530[diff] [blame]2437static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2438 .master = &dra7xx_l4_per2_hwmod,
2439 .slave = &dra7xx_gmac_hwmod,
2440 .clk = "dpll_gmac_ck",
2441 .user = OCP_USER_MPU,
2442};
2443
2444static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2445 .master = &dra7xx_gmac_hwmod,
2446 .slave = &dra7xx_mdio_hwmod,
2447 .user = OCP_USER_MPU,
2448};
2449
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2450/* l4_wkup -> dcan1 */
2451static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2452 .master = &dra7xx_l4_wkup_hwmod,
2453 .slave = &dra7xx_dcan1_hwmod,
2454 .clk = "wkupaon_iclk_mux",
2455 .user = OCP_USER_MPU | OCP_USER_SDMA,
2456};
2457
2458/* l4_per2 -> dcan2 */
2459static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2460 .master = &dra7xx_l4_per2_hwmod,
2461 .slave = &dra7xx_dcan2_hwmod,
2462 .clk = "l3_iclk_div",
2463 .user = OCP_USER_MPU | OCP_USER_SDMA,
2464};
2465
2466static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2467 {
2468 .pa_start = 0x4a056000,
2469 .pa_end = 0x4a056fff,
2470 .flags = ADDR_TYPE_RT
2471 },
2472 { }
2473};
2474
2475/* l4_cfg -> dma_system */
2476static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2477 .master = &dra7xx_l4_cfg_hwmod,
2478 .slave = &dra7xx_dma_system_hwmod,
2479 .clk = "l3_iclk_div",
2480 .addr = dra7xx_dma_system_addrs,
2481 .user = OCP_USER_MPU | OCP_USER_SDMA,
2482};
2483
2484static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2485 {
2486 .name = "family",
2487 .pa_start = 0x58000000,
2488 .pa_end = 0x5800007f,
2489 .flags = ADDR_TYPE_RT
2490 },
2491};
2492
2493/* l3_main_1 -> dss */
2494static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2495 .master = &dra7xx_l3_main_1_hwmod,
2496 .slave = &dra7xx_dss_hwmod,
2497 .clk = "l3_iclk_div",
2498 .addr = dra7xx_dss_addrs,
2499 .user = OCP_USER_MPU | OCP_USER_SDMA,
2500};
2501
2502static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2503 {
2504 .name = "dispc",
2505 .pa_start = 0x58001000,
2506 .pa_end = 0x58001fff,
2507 .flags = ADDR_TYPE_RT
2508 },
2509};
2510
2511/* l3_main_1 -> dispc */
2512static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2513 .master = &dra7xx_l3_main_1_hwmod,
2514 .slave = &dra7xx_dss_dispc_hwmod,
2515 .clk = "l3_iclk_div",
2516 .addr = dra7xx_dss_dispc_addrs,
2517 .user = OCP_USER_MPU | OCP_USER_SDMA,
2518};
2519
2520static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2521 {
2522 .name = "hdmi_wp",
2523 .pa_start = 0x58040000,
2524 .pa_end = 0x580400ff,
2525 .flags = ADDR_TYPE_RT
2526 },
2527 { }
2528};
2529
2530/* l3_main_1 -> dispc */
2531static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2532 .master = &dra7xx_l3_main_1_hwmod,
2533 .slave = &dra7xx_dss_hdmi_hwmod,
2534 .clk = "l3_iclk_div",
2535 .addr = dra7xx_dss_hdmi_addrs,
2536 .user = OCP_USER_MPU | OCP_USER_SDMA,
2537};
2538
2539static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2540 {
2541 .pa_start = 0x48078000,
2542 .pa_end = 0x48078fff,
2543 .flags = ADDR_TYPE_RT
2544 },
2545 { }
2546};
2547
2548/* l4_per1 -> elm */
2549static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2550 .master = &dra7xx_l4_per1_hwmod,
2551 .slave = &dra7xx_elm_hwmod,
2552 .clk = "l3_iclk_div",
2553 .addr = dra7xx_elm_addrs,
2554 .user = OCP_USER_MPU | OCP_USER_SDMA,
2555};
2556
2557/* l4_wkup -> gpio1 */
2558static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2559 .master = &dra7xx_l4_wkup_hwmod,
2560 .slave = &dra7xx_gpio1_hwmod,
2561 .clk = "wkupaon_iclk_mux",
2562 .user = OCP_USER_MPU | OCP_USER_SDMA,
2563};
2564
2565/* l4_per1 -> gpio2 */
2566static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2567 .master = &dra7xx_l4_per1_hwmod,
2568 .slave = &dra7xx_gpio2_hwmod,
2569 .clk = "l3_iclk_div",
2570 .user = OCP_USER_MPU | OCP_USER_SDMA,
2571};
2572
2573/* l4_per1 -> gpio3 */
2574static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2575 .master = &dra7xx_l4_per1_hwmod,
2576 .slave = &dra7xx_gpio3_hwmod,
2577 .clk = "l3_iclk_div",
2578 .user = OCP_USER_MPU | OCP_USER_SDMA,
2579};
2580
2581/* l4_per1 -> gpio4 */
2582static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2583 .master = &dra7xx_l4_per1_hwmod,
2584 .slave = &dra7xx_gpio4_hwmod,
2585 .clk = "l3_iclk_div",
2586 .user = OCP_USER_MPU | OCP_USER_SDMA,
2587};
2588
2589/* l4_per1 -> gpio5 */
2590static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2591 .master = &dra7xx_l4_per1_hwmod,
2592 .slave = &dra7xx_gpio5_hwmod,
2593 .clk = "l3_iclk_div",
2594 .user = OCP_USER_MPU | OCP_USER_SDMA,
2595};
2596
2597/* l4_per1 -> gpio6 */
2598static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2599 .master = &dra7xx_l4_per1_hwmod,
2600 .slave = &dra7xx_gpio6_hwmod,
2601 .clk = "l3_iclk_div",
2602 .user = OCP_USER_MPU | OCP_USER_SDMA,
2603};
2604
2605/* l4_per1 -> gpio7 */
2606static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2607 .master = &dra7xx_l4_per1_hwmod,
2608 .slave = &dra7xx_gpio7_hwmod,
2609 .clk = "l3_iclk_div",
2610 .user = OCP_USER_MPU | OCP_USER_SDMA,
2611};
2612
2613/* l4_per1 -> gpio8 */
2614static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2615 .master = &dra7xx_l4_per1_hwmod,
2616 .slave = &dra7xx_gpio8_hwmod,
2617 .clk = "l3_iclk_div",
2618 .user = OCP_USER_MPU | OCP_USER_SDMA,
2619};
2620
2621static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2622 {
2623 .pa_start = 0x50000000,
2624 .pa_end = 0x500003ff,
2625 .flags = ADDR_TYPE_RT
2626 },
2627 { }
2628};
2629
2630/* l3_main_1 -> gpmc */
2631static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2632 .master = &dra7xx_l3_main_1_hwmod,
2633 .slave = &dra7xx_gpmc_hwmod,
2634 .clk = "l3_iclk_div",
2635 .addr = dra7xx_gpmc_addrs,
2636 .user = OCP_USER_MPU | OCP_USER_SDMA,
2637};
2638
2639static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2640 {
2641 .pa_start = 0x480b2000,
2642 .pa_end = 0x480b201f,
2643 .flags = ADDR_TYPE_RT
2644 },
2645 { }
2646};
2647
2648/* l4_per1 -> hdq1w */
2649static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2650 .master = &dra7xx_l4_per1_hwmod,
2651 .slave = &dra7xx_hdq1w_hwmod,
2652 .clk = "l3_iclk_div",
2653 .addr = dra7xx_hdq1w_addrs,
2654 .user = OCP_USER_MPU | OCP_USER_SDMA,
2655};
2656
2657/* l4_per1 -> i2c1 */
2658static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2659 .master = &dra7xx_l4_per1_hwmod,
2660 .slave = &dra7xx_i2c1_hwmod,
2661 .clk = "l3_iclk_div",
2662 .user = OCP_USER_MPU | OCP_USER_SDMA,
2663};
2664
2665/* l4_per1 -> i2c2 */
2666static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2667 .master = &dra7xx_l4_per1_hwmod,
2668 .slave = &dra7xx_i2c2_hwmod,
2669 .clk = "l3_iclk_div",
2670 .user = OCP_USER_MPU | OCP_USER_SDMA,
2671};
2672
2673/* l4_per1 -> i2c3 */
2674static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2675 .master = &dra7xx_l4_per1_hwmod,
2676 .slave = &dra7xx_i2c3_hwmod,
2677 .clk = "l3_iclk_div",
2678 .user = OCP_USER_MPU | OCP_USER_SDMA,
2679};
2680
2681/* l4_per1 -> i2c4 */
2682static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2683 .master = &dra7xx_l4_per1_hwmod,
2684 .slave = &dra7xx_i2c4_hwmod,
2685 .clk = "l3_iclk_div",
2686 .user = OCP_USER_MPU | OCP_USER_SDMA,
2687};
2688
2689/* l4_per1 -> i2c5 */
2690static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2691 .master = &dra7xx_l4_per1_hwmod,
2692 .slave = &dra7xx_i2c5_hwmod,
2693 .clk = "l3_iclk_div",
2694 .user = OCP_USER_MPU | OCP_USER_SDMA,
2695};
2696
Suman Anna067395d2014-07-11 16:44:39 -0500[diff] [blame]2697/* l4_cfg -> mailbox1 */
2698static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2699 .master = &dra7xx_l4_cfg_hwmod,
2700 .slave = &dra7xx_mailbox1_hwmod,
2701 .clk = "l3_iclk_div",
2702 .user = OCP_USER_MPU | OCP_USER_SDMA,
2703};
2704
2705/* l4_per3 -> mailbox2 */
2706static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2707 .master = &dra7xx_l4_per3_hwmod,
2708 .slave = &dra7xx_mailbox2_hwmod,
2709 .clk = "l3_iclk_div",
2710 .user = OCP_USER_MPU | OCP_USER_SDMA,
2711};
2712
2713/* l4_per3 -> mailbox3 */
2714static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2715 .master = &dra7xx_l4_per3_hwmod,
2716 .slave = &dra7xx_mailbox3_hwmod,
2717 .clk = "l3_iclk_div",
2718 .user = OCP_USER_MPU | OCP_USER_SDMA,
2719};
2720
2721/* l4_per3 -> mailbox4 */
2722static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2723 .master = &dra7xx_l4_per3_hwmod,
2724 .slave = &dra7xx_mailbox4_hwmod,
2725 .clk = "l3_iclk_div",
2726 .user = OCP_USER_MPU | OCP_USER_SDMA,
2727};
2728
2729/* l4_per3 -> mailbox5 */
2730static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2731 .master = &dra7xx_l4_per3_hwmod,
2732 .slave = &dra7xx_mailbox5_hwmod,
2733 .clk = "l3_iclk_div",
2734 .user = OCP_USER_MPU | OCP_USER_SDMA,
2735};
2736
2737/* l4_per3 -> mailbox6 */
2738static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2739 .master = &dra7xx_l4_per3_hwmod,
2740 .slave = &dra7xx_mailbox6_hwmod,
2741 .clk = "l3_iclk_div",
2742 .user = OCP_USER_MPU | OCP_USER_SDMA,
2743};
2744
2745/* l4_per3 -> mailbox7 */
2746static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2747 .master = &dra7xx_l4_per3_hwmod,
2748 .slave = &dra7xx_mailbox7_hwmod,
2749 .clk = "l3_iclk_div",
2750 .user = OCP_USER_MPU | OCP_USER_SDMA,
2751};
2752
2753/* l4_per3 -> mailbox8 */
2754static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2755 .master = &dra7xx_l4_per3_hwmod,
2756 .slave = &dra7xx_mailbox8_hwmod,
2757 .clk = "l3_iclk_div",
2758 .user = OCP_USER_MPU | OCP_USER_SDMA,
2759};
2760
2761/* l4_per3 -> mailbox9 */
2762static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2763 .master = &dra7xx_l4_per3_hwmod,
2764 .slave = &dra7xx_mailbox9_hwmod,
2765 .clk = "l3_iclk_div",
2766 .user = OCP_USER_MPU | OCP_USER_SDMA,
2767};
2768
2769/* l4_per3 -> mailbox10 */
2770static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2771 .master = &dra7xx_l4_per3_hwmod,
2772 .slave = &dra7xx_mailbox10_hwmod,
2773 .clk = "l3_iclk_div",
2774 .user = OCP_USER_MPU | OCP_USER_SDMA,
2775};
2776
2777/* l4_per3 -> mailbox11 */
2778static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2779 .master = &dra7xx_l4_per3_hwmod,
2780 .slave = &dra7xx_mailbox11_hwmod,
2781 .clk = "l3_iclk_div",
2782 .user = OCP_USER_MPU | OCP_USER_SDMA,
2783};
2784
2785/* l4_per3 -> mailbox12 */
2786static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2787 .master = &dra7xx_l4_per3_hwmod,
2788 .slave = &dra7xx_mailbox12_hwmod,
2789 .clk = "l3_iclk_div",
2790 .user = OCP_USER_MPU | OCP_USER_SDMA,
2791};
2792
2793/* l4_per3 -> mailbox13 */
2794static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2795 .master = &dra7xx_l4_per3_hwmod,
2796 .slave = &dra7xx_mailbox13_hwmod,
2797 .clk = "l3_iclk_div",
2798 .user = OCP_USER_MPU | OCP_USER_SDMA,
2799};
2800
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2801/* l4_per1 -> mcspi1 */
2802static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2803 .master = &dra7xx_l4_per1_hwmod,
2804 .slave = &dra7xx_mcspi1_hwmod,
2805 .clk = "l3_iclk_div",
2806 .user = OCP_USER_MPU | OCP_USER_SDMA,
2807};
2808
2809/* l4_per1 -> mcspi2 */
2810static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2811 .master = &dra7xx_l4_per1_hwmod,
2812 .slave = &dra7xx_mcspi2_hwmod,
2813 .clk = "l3_iclk_div",
2814 .user = OCP_USER_MPU | OCP_USER_SDMA,
2815};
2816
2817/* l4_per1 -> mcspi3 */
2818static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2819 .master = &dra7xx_l4_per1_hwmod,
2820 .slave = &dra7xx_mcspi3_hwmod,
2821 .clk = "l3_iclk_div",
2822 .user = OCP_USER_MPU | OCP_USER_SDMA,
2823};
2824
2825/* l4_per1 -> mcspi4 */
2826static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2827 .master = &dra7xx_l4_per1_hwmod,
2828 .slave = &dra7xx_mcspi4_hwmod,
2829 .clk = "l3_iclk_div",
2830 .user = OCP_USER_MPU | OCP_USER_SDMA,
2831};
2832
2833/* l4_per1 -> mmc1 */
2834static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2835 .master = &dra7xx_l4_per1_hwmod,
2836 .slave = &dra7xx_mmc1_hwmod,
2837 .clk = "l3_iclk_div",
2838 .user = OCP_USER_MPU | OCP_USER_SDMA,
2839};
2840
2841/* l4_per1 -> mmc2 */
2842static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2843 .master = &dra7xx_l4_per1_hwmod,
2844 .slave = &dra7xx_mmc2_hwmod,
2845 .clk = "l3_iclk_div",
2846 .user = OCP_USER_MPU | OCP_USER_SDMA,
2847};
2848
2849/* l4_per1 -> mmc3 */
2850static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2851 .master = &dra7xx_l4_per1_hwmod,
2852 .slave = &dra7xx_mmc3_hwmod,
2853 .clk = "l3_iclk_div",
2854 .user = OCP_USER_MPU | OCP_USER_SDMA,
2855};
2856
2857/* l4_per1 -> mmc4 */
2858static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2859 .master = &dra7xx_l4_per1_hwmod,
2860 .slave = &dra7xx_mmc4_hwmod,
2861 .clk = "l3_iclk_div",
2862 .user = OCP_USER_MPU | OCP_USER_SDMA,
2863};
2864
2865/* l4_cfg -> mpu */
2866static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2867 .master = &dra7xx_l4_cfg_hwmod,
2868 .slave = &dra7xx_mpu_hwmod,
2869 .clk = "l3_iclk_div",
2870 .user = OCP_USER_MPU | OCP_USER_SDMA,
2871};
2872
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2873/* l4_cfg -> ocp2scp1 */
2874static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2875 .master = &dra7xx_l4_cfg_hwmod,
2876 .slave = &dra7xx_ocp2scp1_hwmod,
2877 .clk = "l4_root_clk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2878 .user = OCP_USER_MPU | OCP_USER_SDMA,
2879};
2880
Roger Quadrosdf0d0f12014-07-05 17:44:58 -0600[diff] [blame]2881/* l4_cfg -> ocp2scp3 */
2882static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2883 .master = &dra7xx_l4_cfg_hwmod,
2884 .slave = &dra7xx_ocp2scp3_hwmod,
2885 .clk = "l4_root_clk_div",
2886 .user = OCP_USER_MPU | OCP_USER_SDMA,
2887};
2888
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]2889/* l3_main_1 -> pciess1 */
2890static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]2891 .master = &dra7xx_l3_main_1_hwmod,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]2892 .slave = &dra7xx_pciess1_hwmod,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]2893 .clk = "l3_iclk_div",
2894 .user = OCP_USER_MPU | OCP_USER_SDMA,
2895};
2896
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]2897/* l4_cfg -> pciess1 */
2898static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]2899 .master = &dra7xx_l4_cfg_hwmod,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]2900 .slave = &dra7xx_pciess1_hwmod,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]2901 .clk = "l4_root_clk_div",
2902 .user = OCP_USER_MPU | OCP_USER_SDMA,
2903};
2904
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]2905/* l3_main_1 -> pciess2 */
2906static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]2907 .master = &dra7xx_l3_main_1_hwmod,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]2908 .slave = &dra7xx_pciess2_hwmod,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]2909 .clk = "l3_iclk_div",
2910 .user = OCP_USER_MPU | OCP_USER_SDMA,
2911};
2912
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]2913/* l4_cfg -> pciess2 */
2914static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]2915 .master = &dra7xx_l4_cfg_hwmod,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]2916 .slave = &dra7xx_pciess2_hwmod,
Kishon Vijay Abraham I70c18ef72014-06-25 23:32:45 +0530[diff] [blame]2917 .clk = "l4_root_clk_div",
2918 .user = OCP_USER_MPU | OCP_USER_SDMA,
2919};
2920
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2921static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2922 {
2923 .pa_start = 0x4b300000,
2924 .pa_end = 0x4b30007f,
2925 .flags = ADDR_TYPE_RT
2926 },
2927 { }
2928};
2929
2930/* l3_main_1 -> qspi */
2931static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2932 .master = &dra7xx_l3_main_1_hwmod,
2933 .slave = &dra7xx_qspi_hwmod,
2934 .clk = "l3_iclk_div",
2935 .addr = dra7xx_qspi_addrs,
2936 .user = OCP_USER_MPU | OCP_USER_SDMA,
2937};
2938
Lokesh Vutlac913c8a2014-07-22 13:15:57 -0600[diff] [blame]2939/* l4_per3 -> rtcss */
2940static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2941 .master = &dra7xx_l4_per3_hwmod,
2942 .slave = &dra7xx_rtcss_hwmod,
2943 .clk = "l4_root_clk_div",
2944 .user = OCP_USER_MPU | OCP_USER_SDMA,
2945};
2946
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2947static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2948 {
2949 .name = "sysc",
2950 .pa_start = 0x4a141100,
2951 .pa_end = 0x4a141107,
2952 .flags = ADDR_TYPE_RT
2953 },
2954 { }
2955};
2956
2957/* l4_cfg -> sata */
2958static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2959 .master = &dra7xx_l4_cfg_hwmod,
2960 .slave = &dra7xx_sata_hwmod,
2961 .clk = "l3_iclk_div",
2962 .addr = dra7xx_sata_addrs,
2963 .user = OCP_USER_MPU | OCP_USER_SDMA,
2964};
2965
2966static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2967 {
2968 .pa_start = 0x4a0dd000,
2969 .pa_end = 0x4a0dd07f,
2970 .flags = ADDR_TYPE_RT
2971 },
2972 { }
2973};
2974
2975/* l4_cfg -> smartreflex_core */
2976static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2977 .master = &dra7xx_l4_cfg_hwmod,
2978 .slave = &dra7xx_smartreflex_core_hwmod,
2979 .clk = "l4_root_clk_div",
2980 .addr = dra7xx_smartreflex_core_addrs,
2981 .user = OCP_USER_MPU | OCP_USER_SDMA,
2982};
2983
2984static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2985 {
2986 .pa_start = 0x4a0d9000,
2987 .pa_end = 0x4a0d907f,
2988 .flags = ADDR_TYPE_RT
2989 },
2990 { }
2991};
2992
2993/* l4_cfg -> smartreflex_mpu */
2994static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2995 .master = &dra7xx_l4_cfg_hwmod,
2996 .slave = &dra7xx_smartreflex_mpu_hwmod,
2997 .clk = "l4_root_clk_div",
2998 .addr = dra7xx_smartreflex_mpu_addrs,
2999 .user = OCP_USER_MPU | OCP_USER_SDMA,
3000};
3001
3002static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
3003 {
3004 .pa_start = 0x4a0f6000,
3005 .pa_end = 0x4a0f6fff,
3006 .flags = ADDR_TYPE_RT
3007 },
3008 { }
3009};
3010
3011/* l4_cfg -> spinlock */
3012static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3013 .master = &dra7xx_l4_cfg_hwmod,
3014 .slave = &dra7xx_spinlock_hwmod,
3015 .clk = "l3_iclk_div",
3016 .addr = dra7xx_spinlock_addrs,
3017 .user = OCP_USER_MPU | OCP_USER_SDMA,
3018};
3019
3020/* l4_wkup -> timer1 */
3021static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3022 .master = &dra7xx_l4_wkup_hwmod,
3023 .slave = &dra7xx_timer1_hwmod,
3024 .clk = "wkupaon_iclk_mux",
3025 .user = OCP_USER_MPU | OCP_USER_SDMA,
3026};
3027
3028/* l4_per1 -> timer2 */
3029static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3030 .master = &dra7xx_l4_per1_hwmod,
3031 .slave = &dra7xx_timer2_hwmod,
3032 .clk = "l3_iclk_div",
3033 .user = OCP_USER_MPU | OCP_USER_SDMA,
3034};
3035
3036/* l4_per1 -> timer3 */
3037static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3038 .master = &dra7xx_l4_per1_hwmod,
3039 .slave = &dra7xx_timer3_hwmod,
3040 .clk = "l3_iclk_div",
3041 .user = OCP_USER_MPU | OCP_USER_SDMA,
3042};
3043
3044/* l4_per1 -> timer4 */
3045static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3046 .master = &dra7xx_l4_per1_hwmod,
3047 .slave = &dra7xx_timer4_hwmod,
3048 .clk = "l3_iclk_div",
3049 .user = OCP_USER_MPU | OCP_USER_SDMA,
3050};
3051
3052/* l4_per3 -> timer5 */
3053static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3054 .master = &dra7xx_l4_per3_hwmod,
3055 .slave = &dra7xx_timer5_hwmod,
3056 .clk = "l3_iclk_div",
3057 .user = OCP_USER_MPU | OCP_USER_SDMA,
3058};
3059
3060/* l4_per3 -> timer6 */
3061static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3062 .master = &dra7xx_l4_per3_hwmod,
3063 .slave = &dra7xx_timer6_hwmod,
3064 .clk = "l3_iclk_div",
3065 .user = OCP_USER_MPU | OCP_USER_SDMA,
3066};
3067
3068/* l4_per3 -> timer7 */
3069static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3070 .master = &dra7xx_l4_per3_hwmod,
3071 .slave = &dra7xx_timer7_hwmod,
3072 .clk = "l3_iclk_div",
3073 .user = OCP_USER_MPU | OCP_USER_SDMA,
3074};
3075
3076/* l4_per3 -> timer8 */
3077static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3078 .master = &dra7xx_l4_per3_hwmod,
3079 .slave = &dra7xx_timer8_hwmod,
3080 .clk = "l3_iclk_div",
3081 .user = OCP_USER_MPU | OCP_USER_SDMA,
3082};
3083
3084/* l4_per1 -> timer9 */
3085static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3086 .master = &dra7xx_l4_per1_hwmod,
3087 .slave = &dra7xx_timer9_hwmod,
3088 .clk = "l3_iclk_div",
3089 .user = OCP_USER_MPU | OCP_USER_SDMA,
3090};
3091
3092/* l4_per1 -> timer10 */
3093static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3094 .master = &dra7xx_l4_per1_hwmod,
3095 .slave = &dra7xx_timer10_hwmod,
3096 .clk = "l3_iclk_div",
3097 .user = OCP_USER_MPU | OCP_USER_SDMA,
3098};
3099
3100/* l4_per1 -> timer11 */
3101static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3102 .master = &dra7xx_l4_per1_hwmod,
3103 .slave = &dra7xx_timer11_hwmod,
3104 .clk = "l3_iclk_div",
3105 .user = OCP_USER_MPU | OCP_USER_SDMA,
3106};
3107
Suman Anna1ac964f2015-03-16 15:54:53 -0500[diff] [blame]3108/* l4_per3 -> timer13 */
3109static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3110 .master = &dra7xx_l4_per3_hwmod,
3111 .slave = &dra7xx_timer13_hwmod,
3112 .clk = "l3_iclk_div",
3113 .user = OCP_USER_MPU | OCP_USER_SDMA,
3114};
3115
3116/* l4_per3 -> timer14 */
3117static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3118 .master = &dra7xx_l4_per3_hwmod,
3119 .slave = &dra7xx_timer14_hwmod,
3120 .clk = "l3_iclk_div",
3121 .user = OCP_USER_MPU | OCP_USER_SDMA,
3122};
3123
3124/* l4_per3 -> timer15 */
3125static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3126 .master = &dra7xx_l4_per3_hwmod,
3127 .slave = &dra7xx_timer15_hwmod,
3128 .clk = "l3_iclk_div",
3129 .user = OCP_USER_MPU | OCP_USER_SDMA,
3130};
3131
3132/* l4_per3 -> timer16 */
3133static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3134 .master = &dra7xx_l4_per3_hwmod,
3135 .slave = &dra7xx_timer16_hwmod,
3136 .clk = "l3_iclk_div",
3137 .user = OCP_USER_MPU | OCP_USER_SDMA,
3138};
3139
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3140/* l4_per1 -> uart1 */
3141static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3142 .master = &dra7xx_l4_per1_hwmod,
3143 .slave = &dra7xx_uart1_hwmod,
3144 .clk = "l3_iclk_div",
3145 .user = OCP_USER_MPU | OCP_USER_SDMA,
3146};
3147
3148/* l4_per1 -> uart2 */
3149static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3150 .master = &dra7xx_l4_per1_hwmod,
3151 .slave = &dra7xx_uart2_hwmod,
3152 .clk = "l3_iclk_div",
3153 .user = OCP_USER_MPU | OCP_USER_SDMA,
3154};
3155
3156/* l4_per1 -> uart3 */
3157static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3158 .master = &dra7xx_l4_per1_hwmod,
3159 .slave = &dra7xx_uart3_hwmod,
3160 .clk = "l3_iclk_div",
3161 .user = OCP_USER_MPU | OCP_USER_SDMA,
3162};
3163
3164/* l4_per1 -> uart4 */
3165static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3166 .master = &dra7xx_l4_per1_hwmod,
3167 .slave = &dra7xx_uart4_hwmod,
3168 .clk = "l3_iclk_div",
3169 .user = OCP_USER_MPU | OCP_USER_SDMA,
3170};
3171
3172/* l4_per1 -> uart5 */
3173static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3174 .master = &dra7xx_l4_per1_hwmod,
3175 .slave = &dra7xx_uart5_hwmod,
3176 .clk = "l3_iclk_div",
3177 .user = OCP_USER_MPU | OCP_USER_SDMA,
3178};
3179
3180/* l4_per1 -> uart6 */
3181static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3182 .master = &dra7xx_l4_per1_hwmod,
3183 .slave = &dra7xx_uart6_hwmod,
3184 .clk = "l3_iclk_div",
3185 .user = OCP_USER_MPU | OCP_USER_SDMA,
3186};
3187
Ambresh K33acc9f2014-10-21 11:17:51 -0500[diff] [blame]3188/* l4_per2 -> uart7 */
3189static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3190 .master = &dra7xx_l4_per2_hwmod,
3191 .slave = &dra7xx_uart7_hwmod,
3192 .clk = "l3_iclk_div",
3193 .user = OCP_USER_MPU | OCP_USER_SDMA,
3194};
3195
3196/* l4_per2 -> uart8 */
3197static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3198 .master = &dra7xx_l4_per2_hwmod,
3199 .slave = &dra7xx_uart8_hwmod,
3200 .clk = "l3_iclk_div",
3201 .user = OCP_USER_MPU | OCP_USER_SDMA,
3202};
3203
3204/* l4_per2 -> uart9 */
3205static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3206 .master = &dra7xx_l4_per2_hwmod,
3207 .slave = &dra7xx_uart9_hwmod,
3208 .clk = "l3_iclk_div",
3209 .user = OCP_USER_MPU | OCP_USER_SDMA,
3210};
3211
3212/* l4_wkup -> uart10 */
3213static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3214 .master = &dra7xx_l4_wkup_hwmod,
3215 .slave = &dra7xx_uart10_hwmod,
3216 .clk = "wkupaon_iclk_mux",
3217 .user = OCP_USER_MPU | OCP_USER_SDMA,
3218};
3219
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3220/* l4_per3 -> usb_otg_ss1 */
3221static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3222 .master = &dra7xx_l4_per3_hwmod,
3223 .slave = &dra7xx_usb_otg_ss1_hwmod,
3224 .clk = "dpll_core_h13x2_ck",
3225 .user = OCP_USER_MPU | OCP_USER_SDMA,
3226};
3227
3228/* l4_per3 -> usb_otg_ss2 */
3229static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3230 .master = &dra7xx_l4_per3_hwmod,
3231 .slave = &dra7xx_usb_otg_ss2_hwmod,
3232 .clk = "dpll_core_h13x2_ck",
3233 .user = OCP_USER_MPU | OCP_USER_SDMA,
3234};
3235
3236/* l4_per3 -> usb_otg_ss3 */
3237static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3238 .master = &dra7xx_l4_per3_hwmod,
3239 .slave = &dra7xx_usb_otg_ss3_hwmod,
3240 .clk = "dpll_core_h13x2_ck",
3241 .user = OCP_USER_MPU | OCP_USER_SDMA,
3242};
3243
3244/* l4_per3 -> usb_otg_ss4 */
3245static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3246 .master = &dra7xx_l4_per3_hwmod,
3247 .slave = &dra7xx_usb_otg_ss4_hwmod,
3248 .clk = "dpll_core_h13x2_ck",
3249 .user = OCP_USER_MPU | OCP_USER_SDMA,
3250};
3251
3252/* l3_main_1 -> vcp1 */
3253static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3254 .master = &dra7xx_l3_main_1_hwmod,
3255 .slave = &dra7xx_vcp1_hwmod,
3256 .clk = "l3_iclk_div",
3257 .user = OCP_USER_MPU | OCP_USER_SDMA,
3258};
3259
3260/* l4_per2 -> vcp1 */
3261static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3262 .master = &dra7xx_l4_per2_hwmod,
3263 .slave = &dra7xx_vcp1_hwmod,
3264 .clk = "l3_iclk_div",
3265 .user = OCP_USER_MPU | OCP_USER_SDMA,
3266};
3267
3268/* l3_main_1 -> vcp2 */
3269static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3270 .master = &dra7xx_l3_main_1_hwmod,
3271 .slave = &dra7xx_vcp2_hwmod,
3272 .clk = "l3_iclk_div",
3273 .user = OCP_USER_MPU | OCP_USER_SDMA,
3274};
3275
3276/* l4_per2 -> vcp2 */
3277static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3278 .master = &dra7xx_l4_per2_hwmod,
3279 .slave = &dra7xx_vcp2_hwmod,
3280 .clk = "l3_iclk_div",
3281 .user = OCP_USER_MPU | OCP_USER_SDMA,
3282};
3283
3284/* l4_wkup -> wd_timer2 */
3285static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3286 .master = &dra7xx_l4_wkup_hwmod,
3287 .slave = &dra7xx_wd_timer2_hwmod,
3288 .clk = "wkupaon_iclk_mux",
3289 .user = OCP_USER_MPU | OCP_USER_SDMA,
3290};
3291
3292static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3293 &dra7xx_l3_main_2__l3_instr,
3294 &dra7xx_l4_cfg__l3_main_1,
3295 &dra7xx_mpu__l3_main_1,
3296 &dra7xx_l3_main_1__l3_main_2,
3297 &dra7xx_l4_cfg__l3_main_2,
3298 &dra7xx_l3_main_1__l4_cfg,
3299 &dra7xx_l3_main_1__l4_per1,
3300 &dra7xx_l3_main_1__l4_per2,
3301 &dra7xx_l3_main_1__l4_per3,
3302 &dra7xx_l3_main_1__l4_wkup,
3303 &dra7xx_l4_per2__atl,
3304 &dra7xx_l3_main_1__bb2d,
3305 &dra7xx_l4_wkup__counter_32k,
3306 &dra7xx_l4_wkup__ctrl_module_wkup,
3307 &dra7xx_l4_wkup__dcan1,
3308 &dra7xx_l4_per2__dcan2,
Mugunthan V N077c42f2014-07-08 18:46:39 +0530[diff] [blame]3309 &dra7xx_l4_per2__cpgmac0,
3310 &dra7xx_gmac__mdio,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3311 &dra7xx_l4_cfg__dma_system,
3312 &dra7xx_l3_main_1__dss,
3313 &dra7xx_l3_main_1__dispc,
3314 &dra7xx_l3_main_1__hdmi,
3315 &dra7xx_l4_per1__elm,
3316 &dra7xx_l4_wkup__gpio1,
3317 &dra7xx_l4_per1__gpio2,
3318 &dra7xx_l4_per1__gpio3,
3319 &dra7xx_l4_per1__gpio4,
3320 &dra7xx_l4_per1__gpio5,
3321 &dra7xx_l4_per1__gpio6,
3322 &dra7xx_l4_per1__gpio7,
3323 &dra7xx_l4_per1__gpio8,
3324 &dra7xx_l3_main_1__gpmc,
3325 &dra7xx_l4_per1__hdq1w,
3326 &dra7xx_l4_per1__i2c1,
3327 &dra7xx_l4_per1__i2c2,
3328 &dra7xx_l4_per1__i2c3,
3329 &dra7xx_l4_per1__i2c4,
3330 &dra7xx_l4_per1__i2c5,
Suman Anna067395d2014-07-11 16:44:39 -0500[diff] [blame]3331 &dra7xx_l4_cfg__mailbox1,
3332 &dra7xx_l4_per3__mailbox2,
3333 &dra7xx_l4_per3__mailbox3,
3334 &dra7xx_l4_per3__mailbox4,
3335 &dra7xx_l4_per3__mailbox5,
3336 &dra7xx_l4_per3__mailbox6,
3337 &dra7xx_l4_per3__mailbox7,
3338 &dra7xx_l4_per3__mailbox8,
3339 &dra7xx_l4_per3__mailbox9,
3340 &dra7xx_l4_per3__mailbox10,
3341 &dra7xx_l4_per3__mailbox11,
3342 &dra7xx_l4_per3__mailbox12,
3343 &dra7xx_l4_per3__mailbox13,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3344 &dra7xx_l4_per1__mcspi1,
3345 &dra7xx_l4_per1__mcspi2,
3346 &dra7xx_l4_per1__mcspi3,
3347 &dra7xx_l4_per1__mcspi4,
3348 &dra7xx_l4_per1__mmc1,
3349 &dra7xx_l4_per1__mmc2,
3350 &dra7xx_l4_per1__mmc3,
3351 &dra7xx_l4_per1__mmc4,
3352 &dra7xx_l4_cfg__mpu,
3353 &dra7xx_l4_cfg__ocp2scp1,
Roger Quadrosdf0d0f12014-07-05 17:44:58 -0600[diff] [blame]3354 &dra7xx_l4_cfg__ocp2scp3,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3355 &dra7xx_l3_main_1__pciess1,
3356 &dra7xx_l4_cfg__pciess1,
3357 &dra7xx_l3_main_1__pciess2,
3358 &dra7xx_l4_cfg__pciess2,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3359 &dra7xx_l3_main_1__qspi,
Lokesh Vutlac913c8a2014-07-22 13:15:57 -0600[diff] [blame]3360 &dra7xx_l4_per3__rtcss,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3361 &dra7xx_l4_cfg__sata,
3362 &dra7xx_l4_cfg__smartreflex_core,
3363 &dra7xx_l4_cfg__smartreflex_mpu,
3364 &dra7xx_l4_cfg__spinlock,
3365 &dra7xx_l4_wkup__timer1,
3366 &dra7xx_l4_per1__timer2,
3367 &dra7xx_l4_per1__timer3,
3368 &dra7xx_l4_per1__timer4,
3369 &dra7xx_l4_per3__timer5,
3370 &dra7xx_l4_per3__timer6,
3371 &dra7xx_l4_per3__timer7,
3372 &dra7xx_l4_per3__timer8,
3373 &dra7xx_l4_per1__timer9,
3374 &dra7xx_l4_per1__timer10,
3375 &dra7xx_l4_per1__timer11,
Suman Anna1ac964f2015-03-16 15:54:53 -0500[diff] [blame]3376 &dra7xx_l4_per3__timer13,
3377 &dra7xx_l4_per3__timer14,
3378 &dra7xx_l4_per3__timer15,
3379 &dra7xx_l4_per3__timer16,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3380 &dra7xx_l4_per1__uart1,
3381 &dra7xx_l4_per1__uart2,
3382 &dra7xx_l4_per1__uart3,
3383 &dra7xx_l4_per1__uart4,
3384 &dra7xx_l4_per1__uart5,
3385 &dra7xx_l4_per1__uart6,
Ambresh K33acc9f2014-10-21 11:17:51 -0500[diff] [blame]3386 &dra7xx_l4_per2__uart7,
3387 &dra7xx_l4_per2__uart8,
3388 &dra7xx_l4_per2__uart9,
3389 &dra7xx_l4_wkup__uart10,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3390 &dra7xx_l4_per3__usb_otg_ss1,
3391 &dra7xx_l4_per3__usb_otg_ss2,
3392 &dra7xx_l4_per3__usb_otg_ss3,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3393 &dra7xx_l3_main_1__vcp1,
3394 &dra7xx_l4_per2__vcp1,
3395 &dra7xx_l3_main_1__vcp2,
3396 &dra7xx_l4_per2__vcp2,
3397 &dra7xx_l4_wkup__wd_timer2,
3398 NULL,
3399};
3400
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]3401static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3402 &dra7xx_l4_per3__usb_otg_ss4,
3403 NULL,
3404};
3405
3406static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3407 NULL,
3408};
3409
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3410int __init dra7xx_hwmod_init(void)
3411{
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]3412 int ret;
3413
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3414 omap_hwmod_init();
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]3415 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3416
3417 if (!ret && soc_is_dra74x())
3418 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3419 else if (!ret && soc_is_dra72x())
3420 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3421
3422 return ret;
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3423}