Arkadiusz Hiler | 2d803c2 | 2016-11-25 18:59:35 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright © 2016 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #include "i915_drv.h" |
| 26 | #include "intel_uc.h" |
| 27 | |
| 28 | /* |
| 29 | * Read GuC command/status register (SOFT_SCRATCH_0) |
| 30 | * Return true if it contains a response rather than a command |
| 31 | */ |
| 32 | bool intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status) |
| 33 | { |
| 34 | u32 val = I915_READ(SOFT_SCRATCH(0)); |
| 35 | *status = val; |
| 36 | return INTEL_GUC_RECV_IS_RESPONSE(val); |
| 37 | } |
| 38 | |
| 39 | int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) |
| 40 | { |
| 41 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
| 42 | u32 status; |
| 43 | int i; |
| 44 | int ret; |
| 45 | |
| 46 | if (WARN_ON(len < 1 || len > 15)) |
| 47 | return -EINVAL; |
| 48 | |
| 49 | mutex_lock(&guc->send_mutex); |
| 50 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 51 | |
| 52 | dev_priv->guc.action_count += 1; |
| 53 | dev_priv->guc.action_cmd = action[0]; |
| 54 | |
| 55 | for (i = 0; i < len; i++) |
| 56 | I915_WRITE(SOFT_SCRATCH(i), action[i]); |
| 57 | |
| 58 | POSTING_READ(SOFT_SCRATCH(i - 1)); |
| 59 | |
| 60 | I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER); |
| 61 | |
| 62 | /* |
| 63 | * Fast commands should complete in less than 10us, so sample quickly |
| 64 | * up to that length of time, then switch to a slower sleep-wait loop. |
| 65 | * No inte_guc_send command should ever take longer than 10ms. |
| 66 | */ |
| 67 | ret = wait_for_us(intel_guc_recv(dev_priv, &status), 10); |
| 68 | if (ret) |
| 69 | ret = wait_for(intel_guc_recv(dev_priv, &status), 10); |
| 70 | if (status != INTEL_GUC_STATUS_SUCCESS) { |
| 71 | /* |
| 72 | * Either the GuC explicitly returned an error (which |
| 73 | * we convert to -EIO here) or no response at all was |
| 74 | * received within the timeout limit (-ETIMEDOUT) |
| 75 | */ |
| 76 | if (ret != -ETIMEDOUT) |
| 77 | ret = -EIO; |
| 78 | |
| 79 | DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;" |
| 80 | " ret=%d status=0x%08X response=0x%08X\n", |
| 81 | action[0], ret, status, I915_READ(SOFT_SCRATCH(15))); |
| 82 | |
| 83 | dev_priv->guc.action_fail += 1; |
| 84 | dev_priv->guc.action_err = ret; |
| 85 | } |
| 86 | dev_priv->guc.action_status = status; |
| 87 | |
| 88 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
| 89 | mutex_unlock(&guc->send_mutex); |
| 90 | |
| 91 | return ret; |
| 92 | } |
| 93 | |
| 94 | int intel_guc_sample_forcewake(struct intel_guc *guc) |
| 95 | { |
| 96 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
| 97 | u32 action[2]; |
| 98 | |
| 99 | action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE; |
| 100 | /* WaRsDisableCoarsePowerGating:skl,bxt */ |
| 101 | if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) |
| 102 | action[1] = 0; |
| 103 | else |
| 104 | /* bit 0 and 1 are for Render and Media domain separately */ |
| 105 | action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA; |
| 106 | |
| 107 | return intel_guc_send(guc, action, ARRAY_SIZE(action)); |
| 108 | } |
| 109 | |
| 110 | int intel_guc_log_flush_complete(struct intel_guc *guc) |
| 111 | { |
| 112 | u32 action[] = { INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE }; |
| 113 | |
| 114 | return intel_guc_send(guc, action, ARRAY_SIZE(action)); |
| 115 | } |
| 116 | |
| 117 | int intel_guc_log_flush(struct intel_guc *guc) |
| 118 | { |
| 119 | u32 action[] = { |
| 120 | INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH, |
| 121 | 0 |
| 122 | }; |
| 123 | |
| 124 | return intel_guc_send(guc, action, ARRAY_SIZE(action)); |
| 125 | } |
| 126 | |
| 127 | int intel_guc_log_control(struct intel_guc *guc, u32 control_val) |
| 128 | { |
| 129 | u32 action[] = { |
| 130 | INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING, |
| 131 | control_val |
| 132 | }; |
| 133 | |
| 134 | return intel_guc_send(guc, action, ARRAY_SIZE(action)); |
| 135 | } |