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gerrit-public.fairphone.software / kernel / msm-5.4 / 2e0d513f8e9f2d17ea3df9eb43dd4697a250b59c / . / arch / arm / boot / dts / am33xx.dtsi
blob: 6827853a0a8febc31a9b606da466695045668fda [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]15 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]16
17 aliases {
18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
23 serial5 = &uart6;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]24 d_can0 = &dcan0;
25 d_can1 = &dcan1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]26 };
27
28 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame^]29 #address-cells = <1>;
30 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]31 cpu@0 {
32 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame^]33 device_type = "cpu";
34 reg = <0>;
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]35
36 /*
37 * To consider voltage drop between PMIC and SoC,
38 * tolerance value is reduced to 2% from 4% and
39 * voltage value is increased as a precaution.
40 */
41 operating-points = <
42 /* kHz uV */
43 720000 1285000
44 600000 1225000
45 500000 1125000
46 275000 1125000
47 >;
48 voltage-tolerance = <2>; /* 2 percentage */
49 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]50 };
51 };
52
53 /*
54 * The soc node represents the soc top level view. It is uses for IPs
55 * that are not memory mapped in the MPU view or for the MPU itself.
56 */
57 soc {
58 compatible = "ti,omap-infra";
59 mpu {
60 compatible = "ti,omap3-mpu";
61 ti,hwmods = "mpu";
62 };
63 };
64
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]65 am33xx_pinmux: pinmux@44e10800 {
66 compatible = "pinctrl-single";
67 reg = <0x44e10800 0x0238>;
68 #address-cells = <1>;
69 #size-cells = <0>;
70 pinctrl-single,register-width = <32>;
71 pinctrl-single,function-mask = <0x7f>;
72 };
73
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]74 /*
75 * XXX: Use a flat representation of the AM33XX interconnect.
76 * The real AM33XX interconnect network is quite complex.Since
77 * that will not bring real advantage to represent that in DT
78 * for the moment, just use a fake OCP bus entry to represent
79 * the whole bus hierarchy.
80 */
81 ocp {
82 compatible = "simple-bus";
83 #address-cells = <1>;
84 #size-cells = <1>;
85 ranges;
86 ti,hwmods = "l3_main";
87
88 intc: interrupt-controller@48200000 {
89 compatible = "ti,omap2-intc";
90 interrupt-controller;
91 #interrupt-cells = <1>;
92 ti,intc-size = <128>;
93 reg = <0x48200000 0x1000>;
94 };
95
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]96 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]97 compatible = "ti,omap4-gpio";
98 ti,hwmods = "gpio1";
99 gpio-controller;
100 #gpio-cells = <2>;
101 interrupt-controller;
102 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]103 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]104 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]105 };
106
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]107 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]108 compatible = "ti,omap4-gpio";
109 ti,hwmods = "gpio2";
110 gpio-controller;
111 #gpio-cells = <2>;
112 interrupt-controller;
113 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]114 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]115 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]116 };
117
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]118 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]119 compatible = "ti,omap4-gpio";
120 ti,hwmods = "gpio3";
121 gpio-controller;
122 #gpio-cells = <2>;
123 interrupt-controller;
124 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]125 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]126 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]127 };
128
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]129 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]130 compatible = "ti,omap4-gpio";
131 ti,hwmods = "gpio4";
132 gpio-controller;
133 #gpio-cells = <2>;
134 interrupt-controller;
135 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]136 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]137 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]138 };
139
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]140 uart1: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]141 compatible = "ti,omap3-uart";
142 ti,hwmods = "uart1";
143 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]144 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]145 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]146 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]147 };
148
149 uart2: serial@48022000 {
150 compatible = "ti,omap3-uart";
151 ti,hwmods = "uart2";
152 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]153 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]154 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]155 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]156 };
157
158 uart3: serial@48024000 {
159 compatible = "ti,omap3-uart";
160 ti,hwmods = "uart3";
161 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]162 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]163 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]164 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]165 };
166
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]167 uart4: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]168 compatible = "ti,omap3-uart";
169 ti,hwmods = "uart4";
170 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]171 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]172 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]173 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]174 };
175
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]176 uart5: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]177 compatible = "ti,omap3-uart";
178 ti,hwmods = "uart5";
179 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]180 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]181 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]182 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]183 };
184
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]185 uart6: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]186 compatible = "ti,omap3-uart";
187 ti,hwmods = "uart6";
188 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]189 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]190 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]191 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]192 };
193
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]194 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]195 compatible = "ti,omap4-i2c";
196 #address-cells = <1>;
197 #size-cells = <0>;
198 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]199 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]200 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]201 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]202 };
203
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]204 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]205 compatible = "ti,omap4-i2c";
206 #address-cells = <1>;
207 #size-cells = <0>;
208 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]209 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]210 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]211 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]212 };
213
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]214 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]215 compatible = "ti,omap4-i2c";
216 #address-cells = <1>;
217 #size-cells = <0>;
218 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]219 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]220 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]221 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]222 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]223
224 wdt2: wdt@44e35000 {
225 compatible = "ti,omap3-wdt";
226 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]227 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]228 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]229 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]230
231 dcan0: d_can@481cc000 {
232 compatible = "bosch,d_can";
233 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]234 reg = <0x481cc000 0x2000
235 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]236 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]237 status = "disabled";
238 };
239
240 dcan1: d_can@481d0000 {
241 compatible = "bosch,d_can";
242 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]243 reg = <0x481d0000 0x2000
244 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]245 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]246 status = "disabled";
247 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]248
249 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]250 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]251 reg = <0x44e31000 0x400>;
252 interrupts = <67>;
253 ti,hwmods = "timer1";
254 ti,timer-alwon;
255 };
256
257 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]258 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]259 reg = <0x48040000 0x400>;
260 interrupts = <68>;
261 ti,hwmods = "timer2";
262 };
263
264 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]265 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]266 reg = <0x48042000 0x400>;
267 interrupts = <69>;
268 ti,hwmods = "timer3";
269 };
270
271 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]272 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]273 reg = <0x48044000 0x400>;
274 interrupts = <92>;
275 ti,hwmods = "timer4";
276 ti,timer-pwm;
277 };
278
279 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]280 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]281 reg = <0x48046000 0x400>;
282 interrupts = <93>;
283 ti,hwmods = "timer5";
284 ti,timer-pwm;
285 };
286
287 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]288 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]289 reg = <0x48048000 0x400>;
290 interrupts = <94>;
291 ti,hwmods = "timer6";
292 ti,timer-pwm;
293 };
294
295 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]296 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]297 reg = <0x4804a000 0x400>;
298 interrupts = <95>;
299 ti,hwmods = "timer7";
300 ti,timer-pwm;
301 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]302
303 rtc@44e3e000 {
304 compatible = "ti,da830-rtc";
305 reg = <0x44e3e000 0x1000>;
306 interrupts = <75
307 76>;
308 ti,hwmods = "rtc";
309 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]310
311 spi0: spi@48030000 {
312 compatible = "ti,omap4-mcspi";
313 #address-cells = <1>;
314 #size-cells = <0>;
315 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]316 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]317 ti,spi-num-cs = <2>;
318 ti,hwmods = "spi0";
319 status = "disabled";
320 };
321
322 spi1: spi@481a0000 {
323 compatible = "ti,omap4-mcspi";
324 #address-cells = <1>;
325 #size-cells = <0>;
326 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]327 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]328 ti,spi-num-cs = <2>;
329 ti,hwmods = "spi1";
330 status = "disabled";
331 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]332
333 usb@47400000 {
334 compatible = "ti,musb-am33xx";
335 reg = <0x47400000 0x1000 /* usbss */
336 0x47401000 0x800 /* musb instance 0 */
337 0x47401800 0x800>; /* musb instance 1 */
338 interrupts = <17 /* usbss */
339 18 /* musb instance 0 */
340 19>; /* musb instance 1 */
341 multipoint = <1>;
342 num-eps = <16>;
343 ram-bits = <12>;
344 port0-mode = <3>;
345 port1-mode = <3>;
346 power = <250>;
347 ti,hwmods = "usb_otg_hs";
348 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]349
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]350 mac: ethernet@4a100000 {
351 compatible = "ti,cpsw";
352 ti,hwmods = "cpgmac0";
353 cpdma_channels = <8>;
354 ale_entries = <1024>;
355 bd_ram_size = <0x2000>;
356 no_bd_ram = <0>;
357 rx_descs = <64>;
358 mac_control = <0x20>;
359 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]360 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]361 cpts_clock_mult = <0x80000000>;
362 cpts_clock_shift = <29>;
363 reg = <0x4a100000 0x800
364 0x4a101200 0x100>;
365 #address-cells = <1>;
366 #size-cells = <1>;
367 interrupt-parent = <&intc>;
368 /*
369 * c0_rx_thresh_pend
370 * c0_rx_pend
371 * c0_tx_pend
372 * c0_misc_pend
373 */
374 interrupts = <40 41 42 43>;
375 ranges;
376
377 davinci_mdio: mdio@4a101000 {
378 compatible = "ti,davinci_mdio";
379 #address-cells = <1>;
380 #size-cells = <0>;
381 ti,hwmods = "davinci_mdio";
382 bus_freq = <1000000>;
383 reg = <0x4a101000 0x100>;
384 };
385
386 cpsw_emac0: slave@4a100200 {
387 /* Filled in by U-Boot */
388 mac-address = [ 00 00 00 00 00 00 ];
389 };
390
391 cpsw_emac1: slave@4a100300 {
392 /* Filled in by U-Boot */
393 mac-address = [ 00 00 00 00 00 00 ];
394 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]395 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]396
397 ocmcram: ocmcram@40300000 {
398 compatible = "ti,am3352-ocmcram";
399 reg = <0x40300000 0x10000>;
400 ti,hwmods = "ocmcram";
401 ti,no_idle_on_suspend;
402 };
403
404 wkup_m3: wkup_m3@44d00000 {
405 compatible = "ti,am3353-wkup-m3";
406 reg = <0x44d00000 0x4000 /* M3 UMEM */
407 0x44d80000 0x2000>; /* M3 DMEM */
408 ti,hwmods = "wkup_m3";
409 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]410
411 gpmc: gpmc@50000000 {
412 compatible = "ti,am3352-gpmc";
413 ti,hwmods = "gpmc";
414 reg = <0x50000000 0x2000>;
415 interrupts = <100>;
416 num-cs = <7>;
417 num-waitpins = <2>;
418 #address-cells = <2>;
419 #size-cells = <1>;
420 status = "disabled";
421 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]422 };
423};