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gerrit-public.fairphone.software / kernel / msm-5.4 / 2fa8326b4b1e5fdc889b57b03b1313f3229cb438 / . / drivers / i2c / busses / i2c-designware-core.h
blob: ab4e655a6c615829d4b8ac579f15017be7eb6cb6 [file] [log] [blame]
Dirk Brandewie2373f6b2011-10-29 10:57:23 +0100[diff] [blame]1/*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ----------------------------------------------------------------------------
26 *
27 */
28
29/*
30 * Registers offset
31 */
32#define DW_IC_CON 0x0
33#define DW_IC_TAR 0x4
34#define DW_IC_DATA_CMD 0x10
35#define DW_IC_SS_SCL_HCNT 0x14
36#define DW_IC_SS_SCL_LCNT 0x18
37#define DW_IC_FS_SCL_HCNT 0x1c
38#define DW_IC_FS_SCL_LCNT 0x20
39#define DW_IC_INTR_STAT 0x2c
40#define DW_IC_INTR_MASK 0x30
41#define DW_IC_RAW_INTR_STAT 0x34
42#define DW_IC_RX_TL 0x38
43#define DW_IC_TX_TL 0x3c
44#define DW_IC_CLR_INTR 0x40
45#define DW_IC_CLR_RX_UNDER 0x44
46#define DW_IC_CLR_RX_OVER 0x48
47#define DW_IC_CLR_TX_OVER 0x4c
48#define DW_IC_CLR_RD_REQ 0x50
49#define DW_IC_CLR_TX_ABRT 0x54
50#define DW_IC_CLR_RX_DONE 0x58
51#define DW_IC_CLR_ACTIVITY 0x5c
52#define DW_IC_CLR_STOP_DET 0x60
53#define DW_IC_CLR_START_DET 0x64
54#define DW_IC_CLR_GEN_CALL 0x68
55#define DW_IC_ENABLE 0x6c
56#define DW_IC_STATUS 0x70
57#define DW_IC_TXFLR 0x74
58#define DW_IC_RXFLR 0x78
59#define DW_IC_TX_ABRT_SOURCE 0x80
60#define DW_IC_COMP_PARAM_1 0xf4
61#define DW_IC_COMP_TYPE 0xfc
62#define DW_IC_COMP_TYPE_VALUE 0x44570140
63
64#define DW_IC_CON_MASTER 0x1
65#define DW_IC_CON_SPEED_STD 0x2
66#define DW_IC_CON_SPEED_FAST 0x4
67#define DW_IC_CON_10BITADDR_MASTER 0x10
68#define DW_IC_CON_RESTART_EN 0x20
69#define DW_IC_CON_SLAVE_DISABLE 0x40
70
71#define DW_IC_INTR_RX_UNDER 0x001
72#define DW_IC_INTR_RX_OVER 0x002
73#define DW_IC_INTR_RX_FULL 0x004
74#define DW_IC_INTR_TX_OVER 0x008
75#define DW_IC_INTR_TX_EMPTY 0x010
76#define DW_IC_INTR_RD_REQ 0x020
77#define DW_IC_INTR_TX_ABRT 0x040
78#define DW_IC_INTR_RX_DONE 0x080
79#define DW_IC_INTR_ACTIVITY 0x100
80#define DW_IC_INTR_STOP_DET 0x200
81#define DW_IC_INTR_START_DET 0x400
82#define DW_IC_INTR_GEN_CALL 0x800
83
84#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
85 DW_IC_INTR_TX_EMPTY | \
86 DW_IC_INTR_TX_ABRT | \
87 DW_IC_INTR_STOP_DET)
88
89#define DW_IC_STATUS_ACTIVITY 0x1
90
91#define DW_IC_ERR_TX_ABRT 0x1
92
93/*
94 * status codes
95 */
96#define STATUS_IDLE 0x0
97#define STATUS_WRITE_IN_PROGRESS 0x1
98#define STATUS_READ_IN_PROGRESS 0x2
99
100#define TIMEOUT 20 /* ms */
101
102/*
103 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
104 *
105 * only expected abort codes are listed here
106 * refer to the datasheet for the full list
107 */
108#define ABRT_7B_ADDR_NOACK 0
109#define ABRT_10ADDR1_NOACK 1
110#define ABRT_10ADDR2_NOACK 2
111#define ABRT_TXDATA_NOACK 3
112#define ABRT_GCALL_NOACK 4
113#define ABRT_GCALL_READ 5
114#define ABRT_SBYTE_ACKDET 7
115#define ABRT_SBYTE_NORSTRT 9
116#define ABRT_10B_RD_NORSTRT 10
117#define ABRT_MASTER_DIS 11
118#define ARB_LOST 12
119
120#define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
121#define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
122#define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
123#define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
124#define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
125#define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
126#define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
127#define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
128#define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
129#define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
130#define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
131
132#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
133 DW_IC_TX_ABRT_10ADDR1_NOACK | \
134 DW_IC_TX_ABRT_10ADDR2_NOACK | \
135 DW_IC_TX_ABRT_TXDATA_NOACK | \
136 DW_IC_TX_ABRT_GCALL_NOACK)
137/**
138 * struct dw_i2c_dev - private i2c-designware data
139 * @dev: driver model device node
140 * @base: IO registers pointer
141 * @cmd_complete: tx completion indicator
142 * @lock: protect this struct and IO registers
143 * @clk: input reference clock
144 * @cmd_err: run time hadware error code
145 * @msgs: points to an array of messages currently being transfered
146 * @msgs_num: the number of elements in msgs
147 * @msg_write_idx: the element index of the current tx message in the msgs
148 * array
149 * @tx_buf_len: the length of the current tx buffer
150 * @tx_buf: the current tx buffer
151 * @msg_read_idx: the element index of the current rx message in the msgs
152 * array
153 * @rx_buf_len: the length of the current rx buffer
154 * @rx_buf: the current rx buffer
155 * @msg_err: error status of the current transfer
156 * @status: i2c master status, one of STATUS_*
157 * @abort_source: copy of the TX_ABRT_SOURCE register
158 * @irq: interrupt number for the i2c master
159 * @adapter: i2c subsystem adapter node
160 * @tx_fifo_depth: depth of the hardware tx fifo
161 * @rx_fifo_depth: depth of the hardware rx fifo
162 */
163struct dw_i2c_dev {
164 struct device *dev;
165 void __iomem *base;
166 struct completion cmd_complete;
167 struct mutex lock;
168 struct clk *clk;
Dirk Brandewie1d31b582011-10-06 11:26:30 -0700[diff] [blame]169 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
Dirk Brandewie2373f6b2011-10-29 10:57:23 +0100[diff] [blame]170 int cmd_err;
171 struct i2c_msg *msgs;
172 int msgs_num;
173 int msg_write_idx;
174 u32 tx_buf_len;
175 u8 *tx_buf;
176 int msg_read_idx;
177 u32 rx_buf_len;
178 u8 *rx_buf;
179 int msg_err;
180 unsigned int status;
181 u32 abort_source;
182 int irq;
183 int swab;
184 struct i2c_adapter adapter;
Dirk Brandewie2fa83262011-10-06 11:26:31 -0700[diff] [blame^]185 u32 functionality;
Dirk Brandewie2373f6b2011-10-29 10:57:23 +0100[diff] [blame]186 unsigned int tx_fifo_depth;
187 unsigned int rx_fifo_depth;
188};
189
190extern u32 dw_readl(struct dw_i2c_dev *dev, int offset);
191extern void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset);
192extern int i2c_dw_init(struct dw_i2c_dev *dev);
193extern int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
194 int num);
195extern u32 i2c_dw_func(struct i2c_adapter *adap);
196extern irqreturn_t i2c_dw_isr(int this_irq, void *dev_id);