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Jamie Iles61ab1a92011-06-27 13:32:33 +01001* UART (Universal Asynchronous Receiver/Transmitter)
2
3Required properties:
4- compatible : one of:
5 - "ns8250"
6 - "ns16450"
7 - "ns16550a"
8 - "ns16550"
9 - "ns16750"
10 - "ns16850"
Paul Walmsley193c9d22015-01-30 15:11:04 -070011 - For Tegra20, must contain "nvidia,tegra20-uart"
12 - For other Tegra, must contain '"nvidia,<chip>-uart",
13 "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
14 tegra132, or tegra210.
Roland Stiggee4305f02012-06-11 21:57:14 +020015 - "nxp,lpc3220-uart"
John Crispina7ae7f82014-10-16 22:43:27 +020016 - "ralink,rt2880-uart"
Jamie Iles61ab1a92011-06-27 13:32:33 +010017 - "ibm,qpace-nwp-serial"
Ley Foon Tane06c93c2013-03-07 10:28:37 +080018 - "altr,16550-FIFO32"
19 - "altr,16550-FIFO64"
20 - "altr,16550-FIFO128"
Jingchang Lu7d480ef2014-09-05 10:35:14 +080021 - "fsl,16550-FIFO64"
Bhupesh Sharmace4ee582015-01-25 02:42:49 +053022 - "fsl,ns16550"
Jamie Iles61ab1a92011-06-27 13:32:33 +010023 - "serial" if the port type is unknown.
24- reg : offset and length of the register set for the device.
25- interrupts : should contain uart interrupt.
Murali Karicheriab72fa52012-10-22 11:58:02 -040026- clock-frequency : the input clock frequency for the UART
27 or
28 clocks phandle to refer to the clk used as per Documentation/devicetree
29 /bindings/clock/clock-bindings.txt
Jamie Iles61ab1a92011-06-27 13:32:33 +010030
31Optional properties:
32- current-speed : the current active speed of the UART.
33- reg-offset : offset to apply to the mapbase from the start of the registers.
34- reg-shift : quantity to shift the register offsets by.
Jamie Iles74237342011-06-27 13:32:34 +010035- reg-io-width : the size (in bytes) of the IO accesses that should be
36 performed on the device. There are some systems that require 32-bit
37 accesses to the UART (e.g. TI davinci).
Jamie Iles61ab1a92011-06-27 13:32:33 +010038- used-by-rtas : set to indicate that the port is in use by the OpenFirmware
39 RTAS and should not be registered.
Gabor Juhosfde8be22012-07-17 17:08:31 +010040- no-loopback-test: set to indicate that the port does not implements loopback
41 test mode
Heikki Krogerus9f1ca062013-03-25 13:34:45 +020042- fifo-size: the fifo size of the UART.
Heikki Krogerusb0b8c842013-03-25 15:51:15 +020043- auto-flow-control: one way to enable automatic flow control support. The
44 driver is allowed to detect support for the capability even without this
45 property.
Jamie Iles61ab1a92011-06-27 13:32:33 +010046
Bhupesh Sharmace4ee582015-01-25 02:42:49 +053047Note:
48* fsl,ns16550:
49 ------------
50 Freescale DUART is very similar to the PC16552D (and to a
51 pair of NS16550A), albeit with some nonstandard behavior such as
52 erratum A-004737 (relating to incorrect BRK handling).
53
54 Represents a single port that is compatible with the DUART found
55 on many Freescale chips (examples include mpc8349, mpc8548,
56 mpc8641d, p4080 and ls2085a).
57
Jamie Iles61ab1a92011-06-27 13:32:33 +010058Example:
59
60 uart@80230000 {
61 compatible = "ns8250";
62 reg = <0x80230000 0x100>;
63 clock-frequency = <3686400>;
64 interrupts = <10>;
65 reg-shift = <2>;
66 };