Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 1 | /* |
| 2 | * TI Touch Screen driver |
| 3 | * |
| 4 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation version 2. |
| 9 | * |
| 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 11 | * kind, whether express or implied; without even the implied warranty |
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/err.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/input.h> |
| 22 | #include <linux/slab.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/clk.h> |
| 25 | #include <linux/platform_device.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/input/ti_tscadc.h> |
| 28 | #include <linux/delay.h> |
| 29 | |
| 30 | #define REG_IRQEOI 0x020 |
| 31 | #define REG_RAWIRQSTATUS 0x024 |
| 32 | #define REG_IRQSTATUS 0x028 |
| 33 | #define REG_IRQENABLE 0x02C |
| 34 | #define REG_IRQWAKEUP 0x034 |
| 35 | #define REG_CTRL 0x040 |
| 36 | #define REG_ADCFSM 0x044 |
| 37 | #define REG_CLKDIV 0x04C |
| 38 | #define REG_SE 0x054 |
| 39 | #define REG_IDLECONFIG 0x058 |
| 40 | #define REG_CHARGECONFIG 0x05C |
| 41 | #define REG_CHARGEDELAY 0x060 |
| 42 | #define REG_STEPCONFIG(n) (0x64 + ((n - 1) * 8)) |
| 43 | #define REG_STEPDELAY(n) (0x68 + ((n - 1) * 8)) |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 44 | #define REG_FIFO0CNT 0xE4 |
Patil, Rachna | 30af55f | 2012-10-16 12:55:40 +0530 | [diff] [blame^] | 45 | #define REG_FIFO0THR 0xE8 |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 46 | #define REG_FIFO1THR 0xF4 |
| 47 | #define REG_FIFO0 0x100 |
| 48 | #define REG_FIFO1 0x200 |
| 49 | |
| 50 | /* Register Bitfields */ |
| 51 | #define IRQWKUP_ENB BIT(0) |
Patil, Rachna | 33f5cc6 | 2012-10-16 12:55:38 +0530 | [diff] [blame] | 52 | |
| 53 | /* Step Enable */ |
| 54 | #define STEPENB_MASK (0x1FFFF << 0) |
| 55 | #define STEPENB(val) (val << 0) |
| 56 | #define STPENB_STEPENB STEPENB(0x7FFF) |
| 57 | |
| 58 | /* IRQ enable */ |
Patil, Rachna | 30af55f | 2012-10-16 12:55:40 +0530 | [diff] [blame^] | 59 | #define IRQENB_FIFO0THRES BIT(2) |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 60 | #define IRQENB_FIFO1THRES BIT(5) |
| 61 | #define IRQENB_PENUP BIT(9) |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 62 | |
Patil, Rachna | 33f5cc6 | 2012-10-16 12:55:38 +0530 | [diff] [blame] | 63 | /* Step Configuration */ |
| 64 | #define STEPCONFIG_MODE_MASK (3 << 0) |
| 65 | #define STEPCONFIG_MODE(val) (val << 0) |
| 66 | #define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2) |
| 67 | #define STEPCONFIG_AVG_MASK (7 << 2) |
| 68 | #define STEPCONFIG_AVG(val) (val << 2) |
| 69 | #define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4) |
| 70 | #define STEPCONFIG_XPP BIT(5) |
| 71 | #define STEPCONFIG_XNN BIT(6) |
| 72 | #define STEPCONFIG_YPP BIT(7) |
| 73 | #define STEPCONFIG_YNN BIT(8) |
| 74 | #define STEPCONFIG_XNP BIT(9) |
| 75 | #define STEPCONFIG_YPN BIT(10) |
| 76 | #define STEPCONFIG_INM_MASK (0xF << 15) |
| 77 | #define STEPCONFIG_INM(val) (val << 15) |
| 78 | #define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8) |
| 79 | #define STEPCONFIG_INP_MASK (0xF << 19) |
| 80 | #define STEPCONFIG_INP(val) (val << 19) |
| 81 | #define STEPCONFIG_INP_AN2 STEPCONFIG_INP(2) |
| 82 | #define STEPCONFIG_INP_AN3 STEPCONFIG_INP(3) |
| 83 | #define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4) |
| 84 | #define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8) |
| 85 | #define STEPCONFIG_FIFO1 BIT(26) |
| 86 | |
| 87 | /* Delay register */ |
| 88 | #define STEPDELAY_OPEN_MASK (0x3FFFF << 0) |
| 89 | #define STEPDELAY_OPEN(val) (val << 0) |
| 90 | #define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098) |
| 91 | |
| 92 | /* Charge Config */ |
| 93 | #define STEPCHARGE_RFP_MASK (7 << 12) |
| 94 | #define STEPCHARGE_RFP(val) (val << 12) |
| 95 | #define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1) |
| 96 | #define STEPCHARGE_INM_MASK (0xF << 15) |
| 97 | #define STEPCHARGE_INM(val) (val << 15) |
| 98 | #define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1) |
| 99 | #define STEPCHARGE_INP_MASK (0xF << 19) |
| 100 | #define STEPCHARGE_INP(val) (val << 19) |
| 101 | #define STEPCHARGE_INP_AN1 STEPCHARGE_INP(1) |
| 102 | #define STEPCHARGE_RFM_MASK (3 << 23) |
| 103 | #define STEPCHARGE_RFM(val) (val << 23) |
| 104 | #define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1) |
| 105 | |
| 106 | /* Charge delay */ |
| 107 | #define CHARGEDLY_OPEN_MASK (0x3FFFF << 0) |
| 108 | #define CHARGEDLY_OPEN(val) (val << 0) |
| 109 | #define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(1) |
| 110 | |
| 111 | /* Control register */ |
| 112 | #define CNTRLREG_TSCSSENB BIT(0) |
| 113 | #define CNTRLREG_STEPID BIT(1) |
| 114 | #define CNTRLREG_STEPCONFIGWRT BIT(2) |
| 115 | #define CNTRLREG_AFE_CTRL_MASK (3 << 5) |
| 116 | #define CNTRLREG_AFE_CTRL(val) (val << 5) |
| 117 | #define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1) |
| 118 | #define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2) |
| 119 | #define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3) |
| 120 | #define CNTRLREG_TSCENB BIT(7) |
| 121 | |
| 122 | #define ADCFSM_STEPID 0x10 |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 123 | #define SEQ_SETTLE 275 |
| 124 | #define ADC_CLK 3000000 |
| 125 | #define MAX_12BIT ((1 << 12) - 1) |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 126 | |
| 127 | struct tscadc { |
| 128 | struct input_dev *input; |
| 129 | struct clk *tsc_ick; |
| 130 | void __iomem *tsc_base; |
| 131 | unsigned int irq; |
| 132 | unsigned int wires; |
| 133 | unsigned int x_plate_resistance; |
| 134 | bool pen_down; |
Patil, Rachna | d1fb574 | 2012-10-16 12:55:39 +0530 | [diff] [blame] | 135 | int steps_to_configure; |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 136 | }; |
| 137 | |
| 138 | static unsigned int tscadc_readl(struct tscadc *ts, unsigned int reg) |
| 139 | { |
| 140 | return readl(ts->tsc_base + reg); |
| 141 | } |
| 142 | |
| 143 | static void tscadc_writel(struct tscadc *tsc, unsigned int reg, |
| 144 | unsigned int val) |
| 145 | { |
| 146 | writel(val, tsc->tsc_base + reg); |
| 147 | } |
| 148 | |
| 149 | static void tscadc_step_config(struct tscadc *ts_dev) |
| 150 | { |
| 151 | unsigned int config; |
Patil, Rachna | d1fb574 | 2012-10-16 12:55:39 +0530 | [diff] [blame] | 152 | int i, total_steps; |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 153 | |
| 154 | /* Configure the Step registers */ |
Patil, Rachna | d1fb574 | 2012-10-16 12:55:39 +0530 | [diff] [blame] | 155 | total_steps = 2 * ts_dev->steps_to_configure; |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 156 | |
| 157 | config = STEPCONFIG_MODE_HWSYNC | |
Patil, Rachna | 33f5cc6 | 2012-10-16 12:55:38 +0530 | [diff] [blame] | 158 | STEPCONFIG_AVG_16 | STEPCONFIG_XPP; |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 159 | switch (ts_dev->wires) { |
| 160 | case 4: |
Patil, Rachna | 33f5cc6 | 2012-10-16 12:55:38 +0530 | [diff] [blame] | 161 | config |= STEPCONFIG_INP_AN2 | STEPCONFIG_XNN; |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 162 | break; |
| 163 | case 5: |
| 164 | config |= STEPCONFIG_YNN | |
Patil, Rachna | 33f5cc6 | 2012-10-16 12:55:38 +0530 | [diff] [blame] | 165 | STEPCONFIG_INP_AN4 | STEPCONFIG_XNN | |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 166 | STEPCONFIG_YPP; |
| 167 | break; |
| 168 | case 8: |
Patil, Rachna | 33f5cc6 | 2012-10-16 12:55:38 +0530 | [diff] [blame] | 169 | config |= STEPCONFIG_INP_AN2 | STEPCONFIG_XNN; |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 170 | break; |
| 171 | } |
| 172 | |
Patil, Rachna | d1fb574 | 2012-10-16 12:55:39 +0530 | [diff] [blame] | 173 | for (i = 1; i <= ts_dev->steps_to_configure; i++) { |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 174 | tscadc_writel(ts_dev, REG_STEPCONFIG(i), config); |
| 175 | tscadc_writel(ts_dev, REG_STEPDELAY(i), STEPCONFIG_OPENDLY); |
| 176 | } |
| 177 | |
| 178 | config = 0; |
| 179 | config = STEPCONFIG_MODE_HWSYNC | |
Patil, Rachna | 33f5cc6 | 2012-10-16 12:55:38 +0530 | [diff] [blame] | 180 | STEPCONFIG_AVG_16 | STEPCONFIG_YNN | |
| 181 | STEPCONFIG_INM_ADCREFM | STEPCONFIG_FIFO1; |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 182 | switch (ts_dev->wires) { |
| 183 | case 4: |
| 184 | config |= STEPCONFIG_YPP; |
| 185 | break; |
| 186 | case 5: |
Patil, Rachna | 33f5cc6 | 2012-10-16 12:55:38 +0530 | [diff] [blame] | 187 | config |= STEPCONFIG_XPP | STEPCONFIG_INP_AN4 | |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 188 | STEPCONFIG_XNP | STEPCONFIG_YPN; |
| 189 | break; |
| 190 | case 8: |
| 191 | config |= STEPCONFIG_YPP; |
| 192 | break; |
| 193 | } |
| 194 | |
Patil, Rachna | d1fb574 | 2012-10-16 12:55:39 +0530 | [diff] [blame] | 195 | for (i = (ts_dev->steps_to_configure + 1); i <= total_steps; i++) { |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 196 | tscadc_writel(ts_dev, REG_STEPCONFIG(i), config); |
| 197 | tscadc_writel(ts_dev, REG_STEPDELAY(i), STEPCONFIG_OPENDLY); |
| 198 | } |
| 199 | |
| 200 | config = 0; |
| 201 | /* Charge step configuration */ |
| 202 | config = STEPCONFIG_XPP | STEPCONFIG_YNN | |
Patil, Rachna | 33f5cc6 | 2012-10-16 12:55:38 +0530 | [diff] [blame] | 203 | STEPCHARGE_RFP_XPUL | STEPCHARGE_RFM_XNUR | |
| 204 | STEPCHARGE_INM_AN1 | STEPCHARGE_INP_AN1; |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 205 | |
| 206 | tscadc_writel(ts_dev, REG_CHARGECONFIG, config); |
Patil, Rachna | 33f5cc6 | 2012-10-16 12:55:38 +0530 | [diff] [blame] | 207 | tscadc_writel(ts_dev, REG_CHARGEDELAY, CHARGEDLY_OPENDLY); |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 208 | |
| 209 | config = 0; |
| 210 | /* Configure to calculate pressure */ |
| 211 | config = STEPCONFIG_MODE_HWSYNC | |
Patil, Rachna | 33f5cc6 | 2012-10-16 12:55:38 +0530 | [diff] [blame] | 212 | STEPCONFIG_AVG_16 | STEPCONFIG_YPP | |
| 213 | STEPCONFIG_XNN | STEPCONFIG_INM_ADCREFM; |
Patil, Rachna | d1fb574 | 2012-10-16 12:55:39 +0530 | [diff] [blame] | 214 | tscadc_writel(ts_dev, REG_STEPCONFIG(total_steps + 1), config); |
| 215 | tscadc_writel(ts_dev, REG_STEPDELAY(total_steps + 1), |
| 216 | STEPCONFIG_OPENDLY); |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 217 | |
Patil, Rachna | 33f5cc6 | 2012-10-16 12:55:38 +0530 | [diff] [blame] | 218 | config |= STEPCONFIG_INP_AN3 | STEPCONFIG_FIFO1; |
Patil, Rachna | d1fb574 | 2012-10-16 12:55:39 +0530 | [diff] [blame] | 219 | tscadc_writel(ts_dev, REG_STEPCONFIG(total_steps + 2), config); |
| 220 | tscadc_writel(ts_dev, REG_STEPDELAY(total_steps + 2), |
| 221 | STEPCONFIG_OPENDLY); |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 222 | |
| 223 | tscadc_writel(ts_dev, REG_SE, STPENB_STEPENB); |
| 224 | } |
| 225 | |
| 226 | static void tscadc_idle_config(struct tscadc *ts_config) |
| 227 | { |
| 228 | unsigned int idleconfig; |
| 229 | |
| 230 | idleconfig = STEPCONFIG_YNN | |
Patil, Rachna | 33f5cc6 | 2012-10-16 12:55:38 +0530 | [diff] [blame] | 231 | STEPCONFIG_INM_ADCREFM | |
| 232 | STEPCONFIG_YPN | STEPCONFIG_INP_ADCREFM; |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 233 | tscadc_writel(ts_config, REG_IDLECONFIG, idleconfig); |
| 234 | } |
| 235 | |
| 236 | static void tscadc_read_coordinates(struct tscadc *ts_dev, |
| 237 | unsigned int *x, unsigned int *y) |
| 238 | { |
| 239 | unsigned int fifocount = tscadc_readl(ts_dev, REG_FIFO0CNT); |
| 240 | unsigned int prev_val_x = ~0, prev_val_y = ~0; |
| 241 | unsigned int prev_diff_x = ~0, prev_diff_y = ~0; |
| 242 | unsigned int read, diff; |
| 243 | unsigned int i; |
| 244 | |
| 245 | /* |
| 246 | * Delta filter is used to remove large variations in sampled |
| 247 | * values from ADC. The filter tries to predict where the next |
| 248 | * coordinate could be. This is done by taking a previous |
| 249 | * coordinate and subtracting it form current one. Further the |
| 250 | * algorithm compares the difference with that of a present value, |
| 251 | * if true the value is reported to the sub system. |
| 252 | */ |
| 253 | for (i = 0; i < fifocount - 1; i++) { |
| 254 | read = tscadc_readl(ts_dev, REG_FIFO0) & 0xfff; |
| 255 | diff = abs(read - prev_val_x); |
| 256 | if (diff < prev_diff_x) { |
| 257 | prev_diff_x = diff; |
| 258 | *x = read; |
| 259 | } |
| 260 | prev_val_x = read; |
| 261 | |
| 262 | read = tscadc_readl(ts_dev, REG_FIFO1) & 0xfff; |
| 263 | diff = abs(read - prev_val_y); |
| 264 | if (diff < prev_diff_y) { |
| 265 | prev_diff_y = diff; |
| 266 | *y = read; |
| 267 | } |
| 268 | prev_val_y = read; |
| 269 | } |
| 270 | } |
| 271 | |
| 272 | static irqreturn_t tscadc_irq(int irq, void *dev) |
| 273 | { |
| 274 | struct tscadc *ts_dev = dev; |
| 275 | struct input_dev *input_dev = ts_dev->input; |
| 276 | unsigned int status, irqclr = 0; |
| 277 | unsigned int x = 0, y = 0; |
| 278 | unsigned int z1, z2, z; |
| 279 | unsigned int fsm; |
| 280 | |
| 281 | status = tscadc_readl(ts_dev, REG_IRQSTATUS); |
Patil, Rachna | 30af55f | 2012-10-16 12:55:40 +0530 | [diff] [blame^] | 282 | if (status & IRQENB_FIFO0THRES) { |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 283 | tscadc_read_coordinates(ts_dev, &x, &y); |
| 284 | |
| 285 | z1 = tscadc_readl(ts_dev, REG_FIFO0) & 0xfff; |
| 286 | z2 = tscadc_readl(ts_dev, REG_FIFO1) & 0xfff; |
| 287 | |
| 288 | if (ts_dev->pen_down && z1 != 0 && z2 != 0) { |
| 289 | /* |
| 290 | * Calculate pressure using formula |
| 291 | * Resistance(touch) = x plate resistance * |
| 292 | * x postion/4096 * ((z2 / z1) - 1) |
| 293 | */ |
| 294 | z = z2 - z1; |
| 295 | z *= x; |
| 296 | z *= ts_dev->x_plate_resistance; |
| 297 | z /= z1; |
| 298 | z = (z + 2047) >> 12; |
| 299 | |
| 300 | if (z <= MAX_12BIT) { |
| 301 | input_report_abs(input_dev, ABS_X, x); |
| 302 | input_report_abs(input_dev, ABS_Y, y); |
| 303 | input_report_abs(input_dev, ABS_PRESSURE, z); |
| 304 | input_report_key(input_dev, BTN_TOUCH, 1); |
| 305 | input_sync(input_dev); |
| 306 | } |
| 307 | } |
Patil, Rachna | 30af55f | 2012-10-16 12:55:40 +0530 | [diff] [blame^] | 308 | irqclr |= IRQENB_FIFO0THRES; |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 309 | } |
| 310 | |
| 311 | /* |
| 312 | * Time for sequencer to settle, to read |
| 313 | * correct state of the sequencer. |
| 314 | */ |
| 315 | udelay(SEQ_SETTLE); |
| 316 | |
| 317 | status = tscadc_readl(ts_dev, REG_RAWIRQSTATUS); |
| 318 | if (status & IRQENB_PENUP) { |
| 319 | /* Pen up event */ |
| 320 | fsm = tscadc_readl(ts_dev, REG_ADCFSM); |
| 321 | if (fsm == ADCFSM_STEPID) { |
| 322 | ts_dev->pen_down = false; |
| 323 | input_report_key(input_dev, BTN_TOUCH, 0); |
| 324 | input_report_abs(input_dev, ABS_PRESSURE, 0); |
| 325 | input_sync(input_dev); |
| 326 | } else { |
| 327 | ts_dev->pen_down = true; |
| 328 | } |
| 329 | irqclr |= IRQENB_PENUP; |
| 330 | } |
| 331 | |
| 332 | tscadc_writel(ts_dev, REG_IRQSTATUS, irqclr); |
| 333 | /* check pending interrupts */ |
| 334 | tscadc_writel(ts_dev, REG_IRQEOI, 0x0); |
| 335 | |
| 336 | tscadc_writel(ts_dev, REG_SE, STPENB_STEPENB); |
| 337 | return IRQ_HANDLED; |
| 338 | } |
| 339 | |
| 340 | /* |
| 341 | * The functions for inserting/removing driver as a module. |
| 342 | */ |
| 343 | |
| 344 | static int __devinit tscadc_probe(struct platform_device *pdev) |
| 345 | { |
| 346 | const struct tsc_data *pdata = pdev->dev.platform_data; |
| 347 | struct resource *res; |
| 348 | struct tscadc *ts_dev; |
| 349 | struct input_dev *input_dev; |
| 350 | struct clk *clk; |
| 351 | int err; |
| 352 | int clk_value, ctrl, irq; |
| 353 | |
| 354 | if (!pdata) { |
| 355 | dev_err(&pdev->dev, "missing platform data.\n"); |
| 356 | return -EINVAL; |
| 357 | } |
| 358 | |
| 359 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 360 | if (!res) { |
| 361 | dev_err(&pdev->dev, "no memory resource defined.\n"); |
| 362 | return -EINVAL; |
| 363 | } |
| 364 | |
| 365 | irq = platform_get_irq(pdev, 0); |
| 366 | if (irq < 0) { |
| 367 | dev_err(&pdev->dev, "no irq ID is specified.\n"); |
| 368 | return -EINVAL; |
| 369 | } |
| 370 | |
| 371 | /* Allocate memory for device */ |
| 372 | ts_dev = kzalloc(sizeof(struct tscadc), GFP_KERNEL); |
| 373 | input_dev = input_allocate_device(); |
| 374 | if (!ts_dev || !input_dev) { |
| 375 | dev_err(&pdev->dev, "failed to allocate memory.\n"); |
| 376 | err = -ENOMEM; |
| 377 | goto err_free_mem; |
| 378 | } |
| 379 | |
| 380 | ts_dev->input = input_dev; |
| 381 | ts_dev->irq = irq; |
| 382 | ts_dev->wires = pdata->wires; |
| 383 | ts_dev->x_plate_resistance = pdata->x_plate_resistance; |
Patil, Rachna | d1fb574 | 2012-10-16 12:55:39 +0530 | [diff] [blame] | 384 | ts_dev->steps_to_configure = pdata->steps_to_configure; |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 385 | |
| 386 | res = request_mem_region(res->start, resource_size(res), pdev->name); |
| 387 | if (!res) { |
| 388 | dev_err(&pdev->dev, "failed to reserve registers.\n"); |
| 389 | err = -EBUSY; |
| 390 | goto err_free_mem; |
| 391 | } |
| 392 | |
| 393 | ts_dev->tsc_base = ioremap(res->start, resource_size(res)); |
| 394 | if (!ts_dev->tsc_base) { |
| 395 | dev_err(&pdev->dev, "failed to map registers.\n"); |
| 396 | err = -ENOMEM; |
| 397 | goto err_release_mem_region; |
| 398 | } |
| 399 | |
| 400 | err = request_irq(ts_dev->irq, tscadc_irq, |
| 401 | 0, pdev->dev.driver->name, ts_dev); |
| 402 | if (err) { |
| 403 | dev_err(&pdev->dev, "failed to allocate irq.\n"); |
| 404 | goto err_unmap_regs; |
| 405 | } |
| 406 | |
| 407 | ts_dev->tsc_ick = clk_get(&pdev->dev, "adc_tsc_ick"); |
| 408 | if (IS_ERR(ts_dev->tsc_ick)) { |
| 409 | dev_err(&pdev->dev, "failed to get TSC ick\n"); |
| 410 | goto err_free_irq; |
| 411 | } |
| 412 | clk_enable(ts_dev->tsc_ick); |
| 413 | |
| 414 | clk = clk_get(&pdev->dev, "adc_tsc_fck"); |
| 415 | if (IS_ERR(clk)) { |
| 416 | dev_err(&pdev->dev, "failed to get TSC fck\n"); |
| 417 | err = PTR_ERR(clk); |
| 418 | goto err_disable_clk; |
| 419 | } |
| 420 | |
| 421 | clk_value = clk_get_rate(clk) / ADC_CLK; |
| 422 | clk_put(clk); |
| 423 | |
| 424 | if (clk_value < 7) { |
| 425 | dev_err(&pdev->dev, "clock input less than min clock requirement\n"); |
| 426 | goto err_disable_clk; |
| 427 | } |
| 428 | /* CLKDIV needs to be configured to the value minus 1 */ |
| 429 | tscadc_writel(ts_dev, REG_CLKDIV, clk_value - 1); |
| 430 | |
| 431 | /* Enable wake-up of the SoC using touchscreen */ |
| 432 | tscadc_writel(ts_dev, REG_IRQWAKEUP, IRQWKUP_ENB); |
| 433 | |
| 434 | ctrl = CNTRLREG_STEPCONFIGWRT | |
| 435 | CNTRLREG_TSCENB | |
| 436 | CNTRLREG_STEPID; |
| 437 | switch (ts_dev->wires) { |
| 438 | case 4: |
| 439 | ctrl |= CNTRLREG_4WIRE; |
| 440 | break; |
| 441 | case 5: |
| 442 | ctrl |= CNTRLREG_5WIRE; |
| 443 | break; |
| 444 | case 8: |
| 445 | ctrl |= CNTRLREG_8WIRE; |
| 446 | break; |
| 447 | } |
| 448 | tscadc_writel(ts_dev, REG_CTRL, ctrl); |
| 449 | |
| 450 | tscadc_idle_config(ts_dev); |
Patil, Rachna | 30af55f | 2012-10-16 12:55:40 +0530 | [diff] [blame^] | 451 | tscadc_writel(ts_dev, REG_IRQENABLE, IRQENB_FIFO0THRES); |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 452 | tscadc_step_config(ts_dev); |
Patil, Rachna | 30af55f | 2012-10-16 12:55:40 +0530 | [diff] [blame^] | 453 | tscadc_writel(ts_dev, REG_FIFO0THR, ts_dev->steps_to_configure); |
Rachna Patil | 1b8be32 | 2012-03-04 08:11:57 -0800 | [diff] [blame] | 454 | |
| 455 | ctrl |= CNTRLREG_TSCSSENB; |
| 456 | tscadc_writel(ts_dev, REG_CTRL, ctrl); |
| 457 | |
| 458 | input_dev->name = "ti-tsc-adc"; |
| 459 | input_dev->dev.parent = &pdev->dev; |
| 460 | |
| 461 | input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); |
| 462 | input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); |
| 463 | |
| 464 | input_set_abs_params(input_dev, ABS_X, 0, MAX_12BIT, 0, 0); |
| 465 | input_set_abs_params(input_dev, ABS_Y, 0, MAX_12BIT, 0, 0); |
| 466 | input_set_abs_params(input_dev, ABS_PRESSURE, 0, MAX_12BIT, 0, 0); |
| 467 | |
| 468 | /* register to the input system */ |
| 469 | err = input_register_device(input_dev); |
| 470 | if (err) |
| 471 | goto err_disable_clk; |
| 472 | |
| 473 | platform_set_drvdata(pdev, ts_dev); |
| 474 | return 0; |
| 475 | |
| 476 | err_disable_clk: |
| 477 | clk_disable(ts_dev->tsc_ick); |
| 478 | clk_put(ts_dev->tsc_ick); |
| 479 | err_free_irq: |
| 480 | free_irq(ts_dev->irq, ts_dev); |
| 481 | err_unmap_regs: |
| 482 | iounmap(ts_dev->tsc_base); |
| 483 | err_release_mem_region: |
| 484 | release_mem_region(res->start, resource_size(res)); |
| 485 | err_free_mem: |
| 486 | input_free_device(input_dev); |
| 487 | kfree(ts_dev); |
| 488 | return err; |
| 489 | } |
| 490 | |
| 491 | static int __devexit tscadc_remove(struct platform_device *pdev) |
| 492 | { |
| 493 | struct tscadc *ts_dev = platform_get_drvdata(pdev); |
| 494 | struct resource *res; |
| 495 | |
| 496 | free_irq(ts_dev->irq, ts_dev); |
| 497 | |
| 498 | input_unregister_device(ts_dev->input); |
| 499 | |
| 500 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 501 | iounmap(ts_dev->tsc_base); |
| 502 | release_mem_region(res->start, resource_size(res)); |
| 503 | |
| 504 | clk_disable(ts_dev->tsc_ick); |
| 505 | clk_put(ts_dev->tsc_ick); |
| 506 | |
| 507 | kfree(ts_dev); |
| 508 | |
| 509 | platform_set_drvdata(pdev, NULL); |
| 510 | return 0; |
| 511 | } |
| 512 | |
| 513 | static struct platform_driver ti_tsc_driver = { |
| 514 | .probe = tscadc_probe, |
| 515 | .remove = __devexit_p(tscadc_remove), |
| 516 | .driver = { |
| 517 | .name = "tsc", |
| 518 | .owner = THIS_MODULE, |
| 519 | }, |
| 520 | }; |
| 521 | module_platform_driver(ti_tsc_driver); |
| 522 | |
| 523 | MODULE_DESCRIPTION("TI touchscreen controller driver"); |
| 524 | MODULE_AUTHOR("Rachna Patil <rachna@ti.com>"); |
| 525 | MODULE_LICENSE("GPL"); |