Philipp Zabel | 58e4a66 | 2015-02-23 18:40:11 +0100 | [diff] [blame] | 1 | Freescale i.MX General Power Controller |
| 2 | ======================================= |
| 3 | |
Lucas Stach | b7a24a7 | 2017-02-17 20:02:43 +0100 | [diff] [blame] | 4 | The i.MX6 General Power Control (GPC) block contains DVFS load tracking |
| 5 | counters and Power Gating Control (PGC). |
Philipp Zabel | 58e4a66 | 2015-02-23 18:40:11 +0100 | [diff] [blame] | 6 | |
| 7 | Required properties: |
Lucas Stach | 47905a1 | 2017-04-05 15:19:08 +0200 | [diff] [blame] | 8 | - compatible: Should be one of the following: |
| 9 | - fsl,imx6q-gpc |
| 10 | - fsl,imx6qp-gpc |
| 11 | - fsl,imx6sl-gpc |
Fabio Estevam | cfabb79 | 2017-12-15 00:24:57 -0200 | [diff] [blame] | 12 | - fsl,imx6sx-gpc |
Philipp Zabel | 58e4a66 | 2015-02-23 18:40:11 +0100 | [diff] [blame] | 13 | - reg: should be register base and length as documented in the |
| 14 | datasheet |
Lucas Stach | b7a24a7 | 2017-02-17 20:02:43 +0100 | [diff] [blame] | 15 | - interrupts: Should contain one interrupt specifier for the GPC interrupt |
| 16 | - clocks: Must contain an entry for each entry in clock-names. |
Mauro Carvalho Chehab | 34962fb | 2018-05-08 15:14:57 -0300 | [diff] [blame] | 17 | See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. |
Lucas Stach | b7a24a7 | 2017-02-17 20:02:43 +0100 | [diff] [blame] | 18 | - clock-names: Must include the following entries: |
| 19 | - ipg |
Philipp Zabel | 58e4a66 | 2015-02-23 18:40:11 +0100 | [diff] [blame] | 20 | |
Lucas Stach | b7a24a7 | 2017-02-17 20:02:43 +0100 | [diff] [blame] | 21 | The power domains are generic power domain providers as documented in |
| 22 | Documentation/devicetree/bindings/power/power_domain.txt. They are described as |
| 23 | subnodes of the power gating controller 'pgc' node of the GPC and should |
| 24 | contain the following: |
| 25 | |
| 26 | Required properties: |
Dong Aisheng | ff693a3 | 2017-03-23 12:53:24 +0800 | [diff] [blame] | 27 | - reg: Must contain the DOMAIN_INDEX of this power domain |
Lucas Stach | b7a24a7 | 2017-02-17 20:02:43 +0100 | [diff] [blame] | 28 | The following DOMAIN_INDEX values are valid for i.MX6Q: |
| 29 | ARM_DOMAIN 0 |
| 30 | PU_DOMAIN 1 |
| 31 | The following additional DOMAIN_INDEX value is valid for i.MX6SL: |
| 32 | DISPLAY_DOMAIN 2 |
Fabio Estevam | cfabb79 | 2017-12-15 00:24:57 -0200 | [diff] [blame] | 33 | The following additional DOMAIN_INDEX value is valid for i.MX6SX: |
| 34 | PCI_DOMAIN 3 |
Lucas Stach | b7a24a7 | 2017-02-17 20:02:43 +0100 | [diff] [blame] | 35 | |
| 36 | - #power-domain-cells: Should be 0 |
| 37 | |
| 38 | Optional properties: |
| 39 | - clocks: a number of phandles to clocks that need to be enabled during domain |
| 40 | power-up sequencing to ensure reset propagation into devices located inside |
| 41 | this power domain |
| 42 | - power-supply: a phandle to the regulator powering this domain |
Philipp Zabel | 58e4a66 | 2015-02-23 18:40:11 +0100 | [diff] [blame] | 43 | |
| 44 | Example: |
| 45 | |
Marco Franchi | 48c926c | 2017-11-08 14:27:48 -0200 | [diff] [blame] | 46 | gpc: gpc@20dc000 { |
Philipp Zabel | 58e4a66 | 2015-02-23 18:40:11 +0100 | [diff] [blame] | 47 | compatible = "fsl,imx6q-gpc"; |
| 48 | reg = <0x020dc000 0x4000>; |
| 49 | interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, |
| 50 | <0 90 IRQ_TYPE_LEVEL_HIGH>; |
Lucas Stach | b7a24a7 | 2017-02-17 20:02:43 +0100 | [diff] [blame] | 51 | clocks = <&clks IMX6QDL_CLK_IPG>; |
| 52 | clock-names = "ipg"; |
| 53 | |
| 54 | pgc { |
| 55 | #address-cells = <1>; |
| 56 | #size-cells = <0>; |
| 57 | |
| 58 | power-domain@0 { |
| 59 | reg = <0>; |
| 60 | #power-domain-cells = <0>; |
| 61 | }; |
Dong Aisheng | ff693a3 | 2017-03-23 12:53:24 +0800 | [diff] [blame] | 62 | |
Lucas Stach | b7a24a7 | 2017-02-17 20:02:43 +0100 | [diff] [blame] | 63 | pd_pu: power-domain@1 { |
| 64 | reg = <1>; |
| 65 | #power-domain-cells = <0>; |
| 66 | power-supply = <®_pu>; |
| 67 | clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, |
| 68 | <&clks IMX6QDL_CLK_GPU3D_SHADER>, |
| 69 | <&clks IMX6QDL_CLK_GPU2D_CORE>, |
| 70 | <&clks IMX6QDL_CLK_GPU2D_AXI>, |
| 71 | <&clks IMX6QDL_CLK_OPENVG_AXI>, |
| 72 | <&clks IMX6QDL_CLK_VPU_AXI>; |
| 73 | }; |
| 74 | }; |
Philipp Zabel | 58e4a66 | 2015-02-23 18:40:11 +0100 | [diff] [blame] | 75 | }; |
| 76 | |
| 77 | |
| 78 | Specifying power domain for IP modules |
| 79 | ====================================== |
| 80 | |
| 81 | IP cores belonging to a power domain should contain a 'power-domains' property |
Lucas Stach | b7a24a7 | 2017-02-17 20:02:43 +0100 | [diff] [blame] | 82 | that is a phandle pointing to the power domain the device belongs to. |
Philipp Zabel | 58e4a66 | 2015-02-23 18:40:11 +0100 | [diff] [blame] | 83 | |
| 84 | Example of a device that is part of the PU power domain: |
| 85 | |
Marco Franchi | 48c926c | 2017-11-08 14:27:48 -0200 | [diff] [blame] | 86 | vpu: vpu@2040000 { |
Philipp Zabel | 58e4a66 | 2015-02-23 18:40:11 +0100 | [diff] [blame] | 87 | reg = <0x02040000 0x3c000>; |
| 88 | /* ... */ |
Lucas Stach | b7a24a7 | 2017-02-17 20:02:43 +0100 | [diff] [blame] | 89 | power-domains = <&pd_pu>; |
Philipp Zabel | 58e4a66 | 2015-02-23 18:40:11 +0100 | [diff] [blame] | 90 | /* ... */ |
| 91 | }; |