blob: 45daa0be5ff90074e606c8ce96e2297727afa8be [file] [log] [blame]
Dan Williams62232e452015-06-08 14:27:06 -04001/*
2 * Copyright (c) 2014-2015, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU Lesser General Public License,
6 * version 2.1, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT ANY
9 * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
10 * FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for
11 * more details.
12 */
13#ifndef __NDCTL_H__
14#define __NDCTL_H__
15
16#include <linux/types.h>
17
18struct nd_cmd_smart {
19 __u32 status;
20 __u8 data[128];
21} __packed;
22
23struct nd_cmd_smart_threshold {
24 __u32 status;
25 __u8 data[8];
26} __packed;
27
28struct nd_cmd_dimm_flags {
29 __u32 status;
30 __u32 flags;
31} __packed;
32
33struct nd_cmd_get_config_size {
34 __u32 status;
35 __u32 config_size;
36 __u32 max_xfer;
37} __packed;
38
39struct nd_cmd_get_config_data_hdr {
40 __u32 in_offset;
41 __u32 in_length;
42 __u32 status;
43 __u8 out_buf[0];
44} __packed;
45
46struct nd_cmd_set_config_hdr {
47 __u32 in_offset;
48 __u32 in_length;
49 __u8 in_buf[0];
50} __packed;
51
52struct nd_cmd_vendor_hdr {
53 __u32 opcode;
54 __u32 in_length;
55 __u8 in_buf[0];
56} __packed;
57
58struct nd_cmd_vendor_tail {
59 __u32 status;
60 __u32 out_length;
61 __u8 out_buf[0];
62} __packed;
63
64struct nd_cmd_ars_cap {
65 __u64 address;
66 __u64 length;
67 __u32 status;
68 __u32 max_ars_out;
Dan Williams4577b062016-02-17 13:08:58 -080069 __u32 clear_err_unit;
70 __u32 reserved;
Dan Williams62232e452015-06-08 14:27:06 -040071} __packed;
72
73struct nd_cmd_ars_start {
74 __u64 address;
75 __u64 length;
76 __u16 type;
Dan Williams4577b062016-02-17 13:08:58 -080077 __u8 flags;
78 __u8 reserved[5];
Dan Williams62232e452015-06-08 14:27:06 -040079 __u32 status;
Dan Williams4577b062016-02-17 13:08:58 -080080 __u32 scrub_time;
Dan Williams62232e452015-06-08 14:27:06 -040081} __packed;
82
83struct nd_cmd_ars_status {
84 __u32 status;
85 __u32 out_length;
86 __u64 address;
87 __u64 length;
Dan Williams4577b062016-02-17 13:08:58 -080088 __u64 restart_address;
89 __u64 restart_length;
Dan Williams62232e452015-06-08 14:27:06 -040090 __u16 type;
Dan Williams4577b062016-02-17 13:08:58 -080091 __u16 flags;
Dan Williams62232e452015-06-08 14:27:06 -040092 __u32 num_records;
93 struct nd_ars_record {
94 __u32 handle;
Dan Williams4577b062016-02-17 13:08:58 -080095 __u32 reserved;
Dan Williams62232e452015-06-08 14:27:06 -040096 __u64 err_address;
Vishal Vermaec927772015-07-09 13:25:35 -060097 __u64 length;
Dan Williams62232e452015-06-08 14:27:06 -040098 } __packed records[0];
99} __packed;
100
Dan Williamsd4f32362016-03-03 16:08:54 -0800101struct nd_cmd_clear_error {
102 __u64 address;
103 __u64 length;
104 __u32 status;
105 __u8 reserved[4];
106 __u64 cleared;
107} __packed;
108
Dan Williams62232e452015-06-08 14:27:06 -0400109enum {
110 ND_CMD_IMPLEMENTED = 0,
111
112 /* bus commands */
113 ND_CMD_ARS_CAP = 1,
114 ND_CMD_ARS_START = 2,
115 ND_CMD_ARS_STATUS = 3,
Dan Williamsd4f32362016-03-03 16:08:54 -0800116 ND_CMD_CLEAR_ERROR = 4,
Dan Williams62232e452015-06-08 14:27:06 -0400117
118 /* per-dimm commands */
119 ND_CMD_SMART = 1,
120 ND_CMD_SMART_THRESHOLD = 2,
121 ND_CMD_DIMM_FLAGS = 3,
122 ND_CMD_GET_CONFIG_SIZE = 4,
123 ND_CMD_GET_CONFIG_DATA = 5,
124 ND_CMD_SET_CONFIG_DATA = 6,
125 ND_CMD_VENDOR_EFFECT_LOG_SIZE = 7,
126 ND_CMD_VENDOR_EFFECT_LOG = 8,
127 ND_CMD_VENDOR = 9,
Dan Williams31eca762016-04-28 16:23:43 -0700128 ND_CMD_CALL = 10,
Dan Williams62232e452015-06-08 14:27:06 -0400129};
130
Vishal Verma39c686b2015-07-09 13:25:36 -0600131enum {
132 ND_ARS_VOLATILE = 1,
133 ND_ARS_PERSISTENT = 2,
134};
135
Dan Williams62232e452015-06-08 14:27:06 -0400136static inline const char *nvdimm_bus_cmd_name(unsigned cmd)
137{
138 static const char * const names[] = {
139 [ND_CMD_ARS_CAP] = "ars_cap",
140 [ND_CMD_ARS_START] = "ars_start",
141 [ND_CMD_ARS_STATUS] = "ars_status",
Dan Williamsd4f32362016-03-03 16:08:54 -0800142 [ND_CMD_CLEAR_ERROR] = "clear_error",
Dan Williams62232e452015-06-08 14:27:06 -0400143 };
144
145 if (cmd < ARRAY_SIZE(names) && names[cmd])
146 return names[cmd];
147 return "unknown";
148}
149
150static inline const char *nvdimm_cmd_name(unsigned cmd)
151{
152 static const char * const names[] = {
153 [ND_CMD_SMART] = "smart",
154 [ND_CMD_SMART_THRESHOLD] = "smart_thresh",
155 [ND_CMD_DIMM_FLAGS] = "flags",
156 [ND_CMD_GET_CONFIG_SIZE] = "get_size",
157 [ND_CMD_GET_CONFIG_DATA] = "get_data",
158 [ND_CMD_SET_CONFIG_DATA] = "set_data",
159 [ND_CMD_VENDOR_EFFECT_LOG_SIZE] = "effect_size",
160 [ND_CMD_VENDOR_EFFECT_LOG] = "effect_log",
161 [ND_CMD_VENDOR] = "vendor",
Dan Williams31eca762016-04-28 16:23:43 -0700162 [ND_CMD_CALL] = "cmd_call",
Dan Williams62232e452015-06-08 14:27:06 -0400163 };
164
165 if (cmd < ARRAY_SIZE(names) && names[cmd])
166 return names[cmd];
167 return "unknown";
168}
169
170#define ND_IOCTL 'N'
171
172#define ND_IOCTL_SMART _IOWR(ND_IOCTL, ND_CMD_SMART,\
173 struct nd_cmd_smart)
174
175#define ND_IOCTL_SMART_THRESHOLD _IOWR(ND_IOCTL, ND_CMD_SMART_THRESHOLD,\
176 struct nd_cmd_smart_threshold)
177
178#define ND_IOCTL_DIMM_FLAGS _IOWR(ND_IOCTL, ND_CMD_DIMM_FLAGS,\
179 struct nd_cmd_dimm_flags)
180
181#define ND_IOCTL_GET_CONFIG_SIZE _IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_SIZE,\
182 struct nd_cmd_get_config_size)
183
184#define ND_IOCTL_GET_CONFIG_DATA _IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_DATA,\
185 struct nd_cmd_get_config_data_hdr)
186
187#define ND_IOCTL_SET_CONFIG_DATA _IOWR(ND_IOCTL, ND_CMD_SET_CONFIG_DATA,\
188 struct nd_cmd_set_config_hdr)
189
190#define ND_IOCTL_VENDOR _IOWR(ND_IOCTL, ND_CMD_VENDOR,\
191 struct nd_cmd_vendor_hdr)
192
193#define ND_IOCTL_ARS_CAP _IOWR(ND_IOCTL, ND_CMD_ARS_CAP,\
194 struct nd_cmd_ars_cap)
195
196#define ND_IOCTL_ARS_START _IOWR(ND_IOCTL, ND_CMD_ARS_START,\
197 struct nd_cmd_ars_start)
198
199#define ND_IOCTL_ARS_STATUS _IOWR(ND_IOCTL, ND_CMD_ARS_STATUS,\
200 struct nd_cmd_ars_status)
201
Dan Williamsd4f32362016-03-03 16:08:54 -0800202#define ND_IOCTL_CLEAR_ERROR _IOWR(ND_IOCTL, ND_CMD_CLEAR_ERROR,\
203 struct nd_cmd_clear_error)
204
Dan Williams4d88a972015-05-31 14:41:48 -0400205#define ND_DEVICE_DIMM 1 /* nd_dimm: container for "config data" */
Dan Williams3d880022015-05-31 15:02:11 -0400206#define ND_DEVICE_REGION_PMEM 2 /* nd_region: (parent of PMEM namespaces) */
207#define ND_DEVICE_REGION_BLK 3 /* nd_region: (parent of BLK namespaces) */
208#define ND_DEVICE_NAMESPACE_IO 4 /* legacy persistent memory */
209#define ND_DEVICE_NAMESPACE_PMEM 5 /* PMEM namespace (may alias with BLK) */
210#define ND_DEVICE_NAMESPACE_BLK 6 /* BLK namespace (may alias with PMEM) */
Dan Williams4d88a972015-05-31 14:41:48 -0400211
212enum nd_driver_flags {
213 ND_DRIVER_DIMM = 1 << ND_DEVICE_DIMM,
Dan Williams3d880022015-05-31 15:02:11 -0400214 ND_DRIVER_REGION_PMEM = 1 << ND_DEVICE_REGION_PMEM,
215 ND_DRIVER_REGION_BLK = 1 << ND_DEVICE_REGION_BLK,
216 ND_DRIVER_NAMESPACE_IO = 1 << ND_DEVICE_NAMESPACE_IO,
217 ND_DRIVER_NAMESPACE_PMEM = 1 << ND_DEVICE_NAMESPACE_PMEM,
218 ND_DRIVER_NAMESPACE_BLK = 1 << ND_DEVICE_NAMESPACE_BLK,
Dan Williams4d88a972015-05-31 14:41:48 -0400219};
Dan Williamsbf9bccc2015-06-17 17:14:46 -0400220
221enum {
222 ND_MIN_NAMESPACE_SIZE = 0x00400000,
223};
Vishal Verma39c686b2015-07-09 13:25:36 -0600224
225enum ars_masks {
226 ARS_STATUS_MASK = 0x0000FFFF,
227 ARS_EXT_STATUS_SHIFT = 16,
228};
Dan Williams31eca762016-04-28 16:23:43 -0700229
230/*
231 * struct nd_cmd_pkg
232 *
233 * is a wrapper to a quasi pass thru interface for invoking firmware
234 * associated with nvdimms.
235 *
236 * INPUT PARAMETERS
237 *
238 * nd_family corresponds to the firmware (e.g. DSM) interface.
239 *
240 * nd_command are the function index advertised by the firmware.
241 *
242 * nd_size_in is the size of the input parameters being passed to firmware
243 *
244 * OUTPUT PARAMETERS
245 *
246 * nd_fw_size is the size of the data firmware wants to return for
247 * the call. If nd_fw_size is greater than size of nd_size_out, only
248 * the first nd_size_out bytes are returned.
249 */
250
251struct nd_cmd_pkg {
252 __u64 nd_family; /* family of commands */
253 __u64 nd_command;
254 __u32 nd_size_in; /* INPUT: size of input args */
255 __u32 nd_size_out; /* INPUT: size of payload */
256 __u32 nd_reserved2[9]; /* reserved must be zero */
257 __u32 nd_fw_size; /* OUTPUT: size fw wants to return */
258 unsigned char nd_payload[]; /* Contents of call */
259};
260
261/* These NVDIMM families represent pre-standardization command sets */
262#define NVDIMM_FAMILY_INTEL 0
263#define NVDIMM_FAMILY_HPE1 1
264#define NVDIMM_FAMILY_HPE2 2
265
266#define ND_IOCTL_CALL _IOWR(ND_IOCTL, ND_CMD_CALL,\
267 struct nd_cmd_pkg)
268
Dan Williams62232e452015-06-08 14:27:06 -0400269#endif /* __NDCTL_H__ */