blob: 692846c7941b53ac8449ed69a21b2a946a89c3bf [file] [log] [blame]
Michael Turquette738f66d2016-05-23 15:44:26 -07001/*
2 * GXBB clock tree IDs
3 */
4
5#ifndef __GXBB_CLKC_H
6#define __GXBB_CLKC_H
7
8#define CLKID_CPUCLK 1
Neil Armstrong19a2a852016-08-22 14:49:37 +02009#define CLKID_HDMI_PLL 2
Kevin Hilman33608dc2016-08-02 14:40:11 -070010#define CLKID_FCLK_DIV2 4
Neil Armstrong19a2a852016-08-22 14:49:37 +020011#define CLKID_FCLK_DIV3 5
12#define CLKID_FCLK_DIV4 6
Michael Turquette738f66d2016-05-23 15:44:26 -070013#define CLKID_CLK81 12
Martin Blumenstingled6f4b52016-09-06 23:38:44 +020014#define CLKID_MPLL2 15
Jerome Brunetf2120a82016-09-07 17:13:39 +020015#define CLKID_SPI 34
Jerome Brunetdfdd7d42016-09-14 12:06:05 +020016#define CLKID_I2C 22
Martin Blumenstingl33d0fcdf2017-01-19 15:58:20 +010017#define CLKID_SAR_ADC 23
Michael Turquette738f66d2016-05-23 15:44:26 -070018#define CLKID_ETH 36
Martin Blumenstingl5dbe7892016-09-04 23:31:46 +020019#define CLKID_USB0 50
20#define CLKID_USB1 51
21#define CLKID_USB 55
Neil Armstrong5a582cf2017-01-17 13:08:48 +010022#define CLKID_HDMI_PCLK 63
Martin Blumenstingl5dbe7892016-09-04 23:31:46 +020023#define CLKID_USB1_DDR_BRIDGE 64
24#define CLKID_USB0_DDR_BRIDGE 65
Martin Blumenstingl33d0fcdf2017-01-19 15:58:20 +010025#define CLKID_SANA 69
Neil Armstrong5a582cf2017-01-17 13:08:48 +010026#define CLKID_GCLK_VENCI_INT0 77
Jerome Brunetdfdd7d42016-09-14 12:06:05 +020027#define CLKID_AO_I2C 93
Kevin Hilman33608dc2016-08-02 14:40:11 -070028#define CLKID_SD_EMMC_A 94
29#define CLKID_SD_EMMC_B 95
30#define CLKID_SD_EMMC_C 96
Martin Blumenstingl33d0fcdf2017-01-19 15:58:20 +010031#define CLKID_SAR_ADC_CLK 97
32#define CLKID_SAR_ADC_SEL 98
Michael Turquette738f66d2016-05-23 15:44:26 -070033
34#endif /* __GXBB_CLKC_H */