blob: 58ce6af8452db9ca8b4d3c380a06e448919f6a8d [file] [log] [blame]
Simon Arlott75fabc32012-09-10 23:26:15 -06001/*
Eric Anholt41691b82015-10-08 18:37:24 -07002 * Copyright (C) 2010,2015 Broadcom
Simon Arlott75fabc32012-09-10 23:26:15 -06003 * Copyright (C) 2012 Stephen Warren
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
Simon Arlott75fabc32012-09-10 23:26:15 -060015 */
16
Eric Anholt41691b82015-10-08 18:37:24 -070017/**
18 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
19 *
20 * The clock tree on the 2835 has several levels. There's a root
21 * oscillator running at 19.2Mhz. After the oscillator there are 5
22 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
23 * and "HDMI displays". Those 5 PLLs each can divide their output to
24 * produce up to 4 channels. Finally, there is the level of clocks to
25 * be consumed by other hardware components (like "H264" or "HDMI
26 * state machine"), which divide off of some subset of the PLL
27 * channels.
28 *
29 * All of the clocks in the tree are exposed in the DT, because the DT
30 * may want to make assignments of the final layer of clocks to the
31 * PLL channels, and some components of the hardware will actually
32 * skip layers of the tree (for example, the pixel clock comes
33 * directly from the PLLH PIX channel without using a CM_*CTL clock
34 * generator).
35 */
36
Simon Arlott75fabc32012-09-10 23:26:15 -060037#include <linux/clk-provider.h>
38#include <linux/clkdev.h>
Eric Anholt9e400c52016-06-01 12:05:35 -070039#include <linux/clk.h>
Simon Arlott75fabc32012-09-10 23:26:15 -060040#include <linux/clk/bcm2835.h>
Martin Sperl96bf9c62016-02-29 14:20:15 +000041#include <linux/debugfs.h>
Eric Anholt3f919582017-01-18 07:31:57 +110042#include <linux/delay.h>
Eric Anholt41691b82015-10-08 18:37:24 -070043#include <linux/module.h>
Stephen Warren526d2392012-12-24 21:55:01 -070044#include <linux/of.h>
Eric Anholt41691b82015-10-08 18:37:24 -070045#include <linux/platform_device.h>
46#include <linux/slab.h>
47#include <dt-bindings/clock/bcm2835.h>
48
49#define CM_PASSWORD 0x5a000000
50
51#define CM_GNRICCTL 0x000
52#define CM_GNRICDIV 0x004
53# define CM_DIV_FRAC_BITS 12
Martin Sperl959ca922016-02-29 11:39:21 +000054# define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
Eric Anholt41691b82015-10-08 18:37:24 -070055
56#define CM_VPUCTL 0x008
57#define CM_VPUDIV 0x00c
58#define CM_SYSCTL 0x010
59#define CM_SYSDIV 0x014
60#define CM_PERIACTL 0x018
61#define CM_PERIADIV 0x01c
62#define CM_PERIICTL 0x020
63#define CM_PERIIDIV 0x024
64#define CM_H264CTL 0x028
65#define CM_H264DIV 0x02c
66#define CM_ISPCTL 0x030
67#define CM_ISPDIV 0x034
68#define CM_V3DCTL 0x038
69#define CM_V3DDIV 0x03c
70#define CM_CAM0CTL 0x040
71#define CM_CAM0DIV 0x044
72#define CM_CAM1CTL 0x048
73#define CM_CAM1DIV 0x04c
74#define CM_CCP2CTL 0x050
75#define CM_CCP2DIV 0x054
76#define CM_DSI0ECTL 0x058
77#define CM_DSI0EDIV 0x05c
78#define CM_DSI0PCTL 0x060
79#define CM_DSI0PDIV 0x064
80#define CM_DPICTL 0x068
81#define CM_DPIDIV 0x06c
82#define CM_GP0CTL 0x070
83#define CM_GP0DIV 0x074
84#define CM_GP1CTL 0x078
85#define CM_GP1DIV 0x07c
86#define CM_GP2CTL 0x080
87#define CM_GP2DIV 0x084
88#define CM_HSMCTL 0x088
89#define CM_HSMDIV 0x08c
90#define CM_OTPCTL 0x090
91#define CM_OTPDIV 0x094
Martin Sperl2103a212015-12-22 20:13:08 +000092#define CM_PCMCTL 0x098
93#define CM_PCMDIV 0x09c
Eric Anholt41691b82015-10-08 18:37:24 -070094#define CM_PWMCTL 0x0a0
95#define CM_PWMDIV 0x0a4
Martin Sperl2103a212015-12-22 20:13:08 +000096#define CM_SLIMCTL 0x0a8
97#define CM_SLIMDIV 0x0ac
Eric Anholt41691b82015-10-08 18:37:24 -070098#define CM_SMICTL 0x0b0
99#define CM_SMIDIV 0x0b4
Martin Sperl2103a212015-12-22 20:13:08 +0000100/* no definition for 0x0b8 and 0x0bc */
101#define CM_TCNTCTL 0x0c0
Eric Anholt3f919582017-01-18 07:31:57 +1100102# define CM_TCNT_SRC1_SHIFT 12
103#define CM_TCNTCNT 0x0c4
Martin Sperl2103a212015-12-22 20:13:08 +0000104#define CM_TECCTL 0x0c8
105#define CM_TECDIV 0x0cc
106#define CM_TD0CTL 0x0d0
107#define CM_TD0DIV 0x0d4
108#define CM_TD1CTL 0x0d8
109#define CM_TD1DIV 0x0dc
Eric Anholt41691b82015-10-08 18:37:24 -0700110#define CM_TSENSCTL 0x0e0
111#define CM_TSENSDIV 0x0e4
112#define CM_TIMERCTL 0x0e8
113#define CM_TIMERDIV 0x0ec
114#define CM_UARTCTL 0x0f0
115#define CM_UARTDIV 0x0f4
116#define CM_VECCTL 0x0f8
117#define CM_VECDIV 0x0fc
118#define CM_PULSECTL 0x190
119#define CM_PULSEDIV 0x194
120#define CM_SDCCTL 0x1a8
121#define CM_SDCDIV 0x1ac
122#define CM_ARMCTL 0x1b0
Martin Sperld3d6f152016-02-29 15:43:57 +0000123#define CM_AVEOCTL 0x1b8
124#define CM_AVEODIV 0x1bc
Eric Anholt41691b82015-10-08 18:37:24 -0700125#define CM_EMMCCTL 0x1c0
126#define CM_EMMCDIV 0x1c4
127
128/* General bits for the CM_*CTL regs */
129# define CM_ENABLE BIT(4)
130# define CM_KILL BIT(5)
131# define CM_GATE_BIT 6
132# define CM_GATE BIT(CM_GATE_BIT)
133# define CM_BUSY BIT(7)
134# define CM_BUSYD BIT(8)
Martin Sperl959ca922016-02-29 11:39:21 +0000135# define CM_FRAC BIT(9)
Eric Anholt41691b82015-10-08 18:37:24 -0700136# define CM_SRC_SHIFT 0
137# define CM_SRC_BITS 4
138# define CM_SRC_MASK 0xf
139# define CM_SRC_GND 0
140# define CM_SRC_OSC 1
141# define CM_SRC_TESTDEBUG0 2
142# define CM_SRC_TESTDEBUG1 3
143# define CM_SRC_PLLA_CORE 4
144# define CM_SRC_PLLA_PER 4
145# define CM_SRC_PLLC_CORE0 5
146# define CM_SRC_PLLC_PER 5
147# define CM_SRC_PLLC_CORE1 8
148# define CM_SRC_PLLD_CORE 6
149# define CM_SRC_PLLD_PER 6
150# define CM_SRC_PLLH_AUX 7
151# define CM_SRC_PLLC_CORE1 8
152# define CM_SRC_PLLC_CORE2 9
153
154#define CM_OSCCOUNT 0x100
155
156#define CM_PLLA 0x104
157# define CM_PLL_ANARST BIT(8)
158# define CM_PLLA_HOLDPER BIT(7)
159# define CM_PLLA_LOADPER BIT(6)
160# define CM_PLLA_HOLDCORE BIT(5)
161# define CM_PLLA_LOADCORE BIT(4)
162# define CM_PLLA_HOLDCCP2 BIT(3)
163# define CM_PLLA_LOADCCP2 BIT(2)
164# define CM_PLLA_HOLDDSI0 BIT(1)
165# define CM_PLLA_LOADDSI0 BIT(0)
166
167#define CM_PLLC 0x108
168# define CM_PLLC_HOLDPER BIT(7)
169# define CM_PLLC_LOADPER BIT(6)
170# define CM_PLLC_HOLDCORE2 BIT(5)
171# define CM_PLLC_LOADCORE2 BIT(4)
172# define CM_PLLC_HOLDCORE1 BIT(3)
173# define CM_PLLC_LOADCORE1 BIT(2)
174# define CM_PLLC_HOLDCORE0 BIT(1)
175# define CM_PLLC_LOADCORE0 BIT(0)
176
177#define CM_PLLD 0x10c
178# define CM_PLLD_HOLDPER BIT(7)
179# define CM_PLLD_LOADPER BIT(6)
180# define CM_PLLD_HOLDCORE BIT(5)
181# define CM_PLLD_LOADCORE BIT(4)
182# define CM_PLLD_HOLDDSI1 BIT(3)
183# define CM_PLLD_LOADDSI1 BIT(2)
184# define CM_PLLD_HOLDDSI0 BIT(1)
185# define CM_PLLD_LOADDSI0 BIT(0)
186
187#define CM_PLLH 0x110
188# define CM_PLLH_LOADRCAL BIT(2)
189# define CM_PLLH_LOADAUX BIT(1)
190# define CM_PLLH_LOADPIX BIT(0)
191
192#define CM_LOCK 0x114
193# define CM_LOCK_FLOCKH BIT(12)
194# define CM_LOCK_FLOCKD BIT(11)
195# define CM_LOCK_FLOCKC BIT(10)
196# define CM_LOCK_FLOCKB BIT(9)
197# define CM_LOCK_FLOCKA BIT(8)
198
199#define CM_EVENT 0x118
200#define CM_DSI1ECTL 0x158
201#define CM_DSI1EDIV 0x15c
202#define CM_DSI1PCTL 0x160
203#define CM_DSI1PDIV 0x164
204#define CM_DFTCTL 0x168
205#define CM_DFTDIV 0x16c
206
207#define CM_PLLB 0x170
208# define CM_PLLB_HOLDARM BIT(1)
209# define CM_PLLB_LOADARM BIT(0)
210
211#define A2W_PLLA_CTRL 0x1100
212#define A2W_PLLC_CTRL 0x1120
213#define A2W_PLLD_CTRL 0x1140
214#define A2W_PLLH_CTRL 0x1160
215#define A2W_PLLB_CTRL 0x11e0
216# define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
217# define A2W_PLL_CTRL_PWRDN BIT(16)
218# define A2W_PLL_CTRL_PDIV_MASK 0x000007000
219# define A2W_PLL_CTRL_PDIV_SHIFT 12
220# define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
221# define A2W_PLL_CTRL_NDIV_SHIFT 0
222
223#define A2W_PLLA_ANA0 0x1010
224#define A2W_PLLC_ANA0 0x1030
225#define A2W_PLLD_ANA0 0x1050
226#define A2W_PLLH_ANA0 0x1070
227#define A2W_PLLB_ANA0 0x10f0
228
229#define A2W_PLL_KA_SHIFT 7
230#define A2W_PLL_KA_MASK GENMASK(9, 7)
231#define A2W_PLL_KI_SHIFT 19
232#define A2W_PLL_KI_MASK GENMASK(21, 19)
233#define A2W_PLL_KP_SHIFT 15
234#define A2W_PLL_KP_MASK GENMASK(18, 15)
235
236#define A2W_PLLH_KA_SHIFT 19
237#define A2W_PLLH_KA_MASK GENMASK(21, 19)
238#define A2W_PLLH_KI_LOW_SHIFT 22
239#define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
240#define A2W_PLLH_KI_HIGH_SHIFT 0
241#define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
242#define A2W_PLLH_KP_SHIFT 1
243#define A2W_PLLH_KP_MASK GENMASK(4, 1)
244
245#define A2W_XOSC_CTRL 0x1190
246# define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
247# define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
248# define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
249# define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
250# define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
251# define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
252# define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
253# define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
254
255#define A2W_PLLA_FRAC 0x1200
256#define A2W_PLLC_FRAC 0x1220
257#define A2W_PLLD_FRAC 0x1240
258#define A2W_PLLH_FRAC 0x1260
259#define A2W_PLLB_FRAC 0x12e0
260# define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
261# define A2W_PLL_FRAC_BITS 20
262
263#define A2W_PLL_CHANNEL_DISABLE BIT(8)
264#define A2W_PLL_DIV_BITS 8
265#define A2W_PLL_DIV_SHIFT 0
266
267#define A2W_PLLA_DSI0 0x1300
268#define A2W_PLLA_CORE 0x1400
269#define A2W_PLLA_PER 0x1500
270#define A2W_PLLA_CCP2 0x1600
271
272#define A2W_PLLC_CORE2 0x1320
273#define A2W_PLLC_CORE1 0x1420
274#define A2W_PLLC_PER 0x1520
275#define A2W_PLLC_CORE0 0x1620
276
277#define A2W_PLLD_DSI0 0x1340
278#define A2W_PLLD_CORE 0x1440
279#define A2W_PLLD_PER 0x1540
280#define A2W_PLLD_DSI1 0x1640
281
282#define A2W_PLLH_AUX 0x1360
283#define A2W_PLLH_RCAL 0x1460
284#define A2W_PLLH_PIX 0x1560
285#define A2W_PLLH_STS 0x1660
286
287#define A2W_PLLH_CTRLR 0x1960
288#define A2W_PLLH_FRACR 0x1a60
289#define A2W_PLLH_AUXR 0x1b60
290#define A2W_PLLH_RCALR 0x1c60
291#define A2W_PLLH_PIXR 0x1d60
292#define A2W_PLLH_STSR 0x1e60
293
294#define A2W_PLLB_ARM 0x13e0
295#define A2W_PLLB_SP0 0x14e0
296#define A2W_PLLB_SP1 0x15e0
297#define A2W_PLLB_SP2 0x16e0
298
299#define LOCK_TIMEOUT_NS 100000000
300#define BCM2835_MAX_FB_RATE 1750000000u
301
Eric Anholt8a39e9f2017-01-18 07:31:56 +1100302/*
303 * Names of clocks used within the driver that need to be replaced
304 * with an external parent's name. This array is in the order that
305 * the clocks node in the DT references external clocks.
306 */
307static const char *const cprman_parent_names[] = {
308 "xosc",
309 "dsi0_byte",
310 "dsi0_ddr2",
311 "dsi0_ddr",
312 "dsi1_byte",
313 "dsi1_ddr2",
314 "dsi1_ddr",
315};
316
Eric Anholt41691b82015-10-08 18:37:24 -0700317struct bcm2835_cprman {
318 struct device *dev;
319 void __iomem *regs;
Martin Sperl6e1e60d2016-02-29 11:39:22 +0000320 spinlock_t regs_lock; /* spinlock for all clocks */
Eric Anholt8a39e9f2017-01-18 07:31:56 +1100321
322 /*
323 * Real names of cprman clock parents looked up through
324 * of_clk_get_parent_name(), which will be used in the
325 * parent_names[] arrays for clock registration.
326 */
327 const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)];
Eric Anholt41691b82015-10-08 18:37:24 -0700328
Stephen Boydb19f0092016-06-01 16:15:03 -0700329 /* Must be last */
330 struct clk_hw_onecell_data onecell;
Eric Anholt41691b82015-10-08 18:37:24 -0700331};
332
333static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
334{
335 writel(CM_PASSWORD | val, cprman->regs + reg);
336}
337
338static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)
339{
340 return readl(cprman->regs + reg);
341}
Stephen Warren526d2392012-12-24 21:55:01 -0700342
Eric Anholt3f919582017-01-18 07:31:57 +1100343/* Does a cycle of measuring a clock through the TCNT clock, which may
344 * source from many other clocks in the system.
345 */
346static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,
347 u32 tcnt_mux)
348{
349 u32 osccount = 19200; /* 1ms */
350 u32 count;
351 ktime_t timeout;
352
353 spin_lock(&cprman->regs_lock);
354
355 cprman_write(cprman, CM_TCNTCTL, CM_KILL);
356
357 cprman_write(cprman, CM_TCNTCTL,
358 (tcnt_mux & CM_SRC_MASK) |
359 (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT);
360
361 cprman_write(cprman, CM_OSCCOUNT, osccount);
362
363 /* do a kind delay at the start */
364 mdelay(1);
365
366 /* Finish off whatever is left of OSCCOUNT */
367 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
368 while (cprman_read(cprman, CM_OSCCOUNT)) {
369 if (ktime_after(ktime_get(), timeout)) {
370 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");
371 count = 0;
372 goto out;
373 }
374 cpu_relax();
375 }
376
377 /* Wait for BUSY to clear. */
378 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
379 while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {
380 if (ktime_after(ktime_get(), timeout)) {
381 dev_err(cprman->dev, "timeout waiting for !BUSY\n");
382 count = 0;
383 goto out;
384 }
385 cpu_relax();
386 }
387
388 count = cprman_read(cprman, CM_TCNTCNT);
389
390 cprman_write(cprman, CM_TCNTCTL, 0);
391
392out:
393 spin_unlock(&cprman->regs_lock);
394
395 return count * 1000;
396}
397
Martin Sperl96bf9c62016-02-29 14:20:15 +0000398static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
399 struct debugfs_reg32 *regs, size_t nregs,
400 struct dentry *dentry)
401{
402 struct dentry *regdump;
403 struct debugfs_regset32 *regset;
404
405 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
406 if (!regset)
407 return -ENOMEM;
408
409 regset->regs = regs;
410 regset->nregs = nregs;
411 regset->base = cprman->regs + base;
412
413 regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry,
414 regset);
415
416 return regdump ? 0 : -ENOMEM;
417}
418
Simon Arlott75fabc32012-09-10 23:26:15 -0600419/*
420 * These are fixed clocks. They're probably not all root clocks and it may
421 * be possible to turn them on and off but until this is mapped out better
422 * it's the only way they can be used.
423 */
424void __init bcm2835_init_clocks(void)
425{
Stephen Boydb19f0092016-06-01 16:15:03 -0700426 struct clk_hw *hw;
Simon Arlott75fabc32012-09-10 23:26:15 -0600427 int ret;
428
Stephen Boydb19f0092016-06-01 16:15:03 -0700429 hw = clk_hw_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 126000000);
430 if (IS_ERR(hw))
Simon Arlott75fabc32012-09-10 23:26:15 -0600431 pr_err("apb_pclk not registered\n");
432
Stephen Boydb19f0092016-06-01 16:15:03 -0700433 hw = clk_hw_register_fixed_rate(NULL, "uart0_pclk", NULL, 0, 3000000);
434 if (IS_ERR(hw))
Simon Arlott75fabc32012-09-10 23:26:15 -0600435 pr_err("uart0_pclk not registered\n");
Stephen Boydb19f0092016-06-01 16:15:03 -0700436 ret = clk_hw_register_clkdev(hw, NULL, "20201000.uart");
Simon Arlott75fabc32012-09-10 23:26:15 -0600437 if (ret)
438 pr_err("uart0_pclk alias not registered\n");
439
Stephen Boydb19f0092016-06-01 16:15:03 -0700440 hw = clk_hw_register_fixed_rate(NULL, "uart1_pclk", NULL, 0, 125000000);
441 if (IS_ERR(hw))
Simon Arlott75fabc32012-09-10 23:26:15 -0600442 pr_err("uart1_pclk not registered\n");
Stephen Boydb19f0092016-06-01 16:15:03 -0700443 ret = clk_hw_register_clkdev(hw, NULL, "20215000.uart");
Simon Arlott75fabc32012-09-10 23:26:15 -0600444 if (ret)
Domenico Andreoli686ea582012-10-20 03:35:28 +0200445 pr_err("uart1_pclk alias not registered\n");
Simon Arlott75fabc32012-09-10 23:26:15 -0600446}
Eric Anholt41691b82015-10-08 18:37:24 -0700447
448struct bcm2835_pll_data {
449 const char *name;
450 u32 cm_ctrl_reg;
451 u32 a2w_ctrl_reg;
452 u32 frac_reg;
453 u32 ana_reg_base;
454 u32 reference_enable_mask;
455 /* Bit in CM_LOCK to indicate when the PLL has locked. */
456 u32 lock_mask;
457
458 const struct bcm2835_pll_ana_bits *ana;
459
460 unsigned long min_rate;
461 unsigned long max_rate;
462 /*
463 * Highest rate for the VCO before we have to use the
464 * pre-divide-by-2.
465 */
466 unsigned long max_fb_rate;
467};
468
469struct bcm2835_pll_ana_bits {
470 u32 mask0;
471 u32 set0;
472 u32 mask1;
473 u32 set1;
474 u32 mask3;
475 u32 set3;
476 u32 fb_prediv_mask;
477};
478
479static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {
480 .mask0 = 0,
481 .set0 = 0,
Eric Anholt286259e2016-04-13 13:05:02 -0700482 .mask1 = (u32)~(A2W_PLL_KI_MASK | A2W_PLL_KP_MASK),
Eric Anholt41691b82015-10-08 18:37:24 -0700483 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),
Eric Anholt286259e2016-04-13 13:05:02 -0700484 .mask3 = (u32)~A2W_PLL_KA_MASK,
Eric Anholt41691b82015-10-08 18:37:24 -0700485 .set3 = (2 << A2W_PLL_KA_SHIFT),
486 .fb_prediv_mask = BIT(14),
487};
488
489static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
Eric Anholt286259e2016-04-13 13:05:02 -0700490 .mask0 = (u32)~(A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK),
Eric Anholt41691b82015-10-08 18:37:24 -0700491 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),
Eric Anholt286259e2016-04-13 13:05:02 -0700492 .mask1 = (u32)~(A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK),
Eric Anholt41691b82015-10-08 18:37:24 -0700493 .set1 = (6 << A2W_PLLH_KP_SHIFT),
494 .mask3 = 0,
495 .set3 = 0,
496 .fb_prediv_mask = BIT(11),
497};
498
Eric Anholt41691b82015-10-08 18:37:24 -0700499struct bcm2835_pll_divider_data {
500 const char *name;
Martin Sperl3b15afe2016-02-29 12:51:42 +0000501 const char *source_pll;
502
Eric Anholt41691b82015-10-08 18:37:24 -0700503 u32 cm_reg;
504 u32 a2w_reg;
505
506 u32 load_mask;
507 u32 hold_mask;
508 u32 fixed_divider;
Eric Anholt55486092017-01-18 07:31:55 +1100509 u32 flags;
Eric Anholt41691b82015-10-08 18:37:24 -0700510};
511
Eric Anholt41691b82015-10-08 18:37:24 -0700512struct bcm2835_clock_data {
513 const char *name;
514
515 const char *const *parents;
516 int num_mux_parents;
517
Boris Brezillon155e8b32016-12-01 22:00:19 +0100518 /* Bitmap encoding which parents accept rate change propagation. */
519 unsigned int set_rate_parent;
520
Eric Anholt41691b82015-10-08 18:37:24 -0700521 u32 ctl_reg;
522 u32 div_reg;
523
524 /* Number of integer bits in the divider */
525 u32 int_bits;
526 /* Number of fractional bits in the divider */
527 u32 frac_bits;
528
Eric Anholte69fdcc2016-06-01 12:05:33 -0700529 u32 flags;
530
Eric Anholt41691b82015-10-08 18:37:24 -0700531 bool is_vpu_clock;
Martin Sperl959ca922016-02-29 11:39:21 +0000532 bool is_mash_clock;
Phil Elwell35429762017-06-01 15:14:22 +0100533 bool low_jitter;
Eric Anholt3f919582017-01-18 07:31:57 +1100534
535 u32 tcnt_mux;
Eric Anholt41691b82015-10-08 18:37:24 -0700536};
537
Martin Sperl56eb3a22016-02-29 12:51:41 +0000538struct bcm2835_gate_data {
539 const char *name;
540 const char *parent;
541
542 u32 ctl_reg;
543};
544
Eric Anholt41691b82015-10-08 18:37:24 -0700545struct bcm2835_pll {
546 struct clk_hw hw;
547 struct bcm2835_cprman *cprman;
548 const struct bcm2835_pll_data *data;
549};
550
551static int bcm2835_pll_is_on(struct clk_hw *hw)
552{
553 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
554 struct bcm2835_cprman *cprman = pll->cprman;
555 const struct bcm2835_pll_data *data = pll->data;
556
557 return cprman_read(cprman, data->a2w_ctrl_reg) &
558 A2W_PLL_CTRL_PRST_DISABLE;
559}
560
561static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
562 unsigned long parent_rate,
563 u32 *ndiv, u32 *fdiv)
564{
565 u64 div;
566
567 div = (u64)rate << A2W_PLL_FRAC_BITS;
568 do_div(div, parent_rate);
569
570 *ndiv = div >> A2W_PLL_FRAC_BITS;
571 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
572}
573
574static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
575 u32 ndiv, u32 fdiv, u32 pdiv)
576{
577 u64 rate;
578
579 if (pdiv == 0)
580 return 0;
581
582 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);
583 do_div(rate, pdiv);
584 return rate >> A2W_PLL_FRAC_BITS;
585}
586
587static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
588 unsigned long *parent_rate)
589{
Eric Anholtc4e634c2016-09-30 10:07:27 -0700590 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
591 const struct bcm2835_pll_data *data = pll->data;
Eric Anholt41691b82015-10-08 18:37:24 -0700592 u32 ndiv, fdiv;
593
Eric Anholtc4e634c2016-09-30 10:07:27 -0700594 rate = clamp(rate, data->min_rate, data->max_rate);
595
Eric Anholt41691b82015-10-08 18:37:24 -0700596 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
597
598 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
599}
600
601static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
602 unsigned long parent_rate)
603{
604 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
605 struct bcm2835_cprman *cprman = pll->cprman;
606 const struct bcm2835_pll_data *data = pll->data;
607 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
608 u32 ndiv, pdiv, fdiv;
609 bool using_prediv;
610
611 if (parent_rate == 0)
612 return 0;
613
614 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
615 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;
616 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;
617 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
618 data->ana->fb_prediv_mask;
619
Phil Elwelle45098d2017-05-15 10:35:04 -0700620 if (using_prediv) {
Eric Anholt41691b82015-10-08 18:37:24 -0700621 ndiv *= 2;
Phil Elwelle45098d2017-05-15 10:35:04 -0700622 fdiv *= 2;
623 }
Eric Anholt41691b82015-10-08 18:37:24 -0700624
625 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
626}
627
628static void bcm2835_pll_off(struct clk_hw *hw)
629{
630 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
631 struct bcm2835_cprman *cprman = pll->cprman;
632 const struct bcm2835_pll_data *data = pll->data;
633
Martin Sperl6727f082016-02-29 11:39:17 +0000634 spin_lock(&cprman->regs_lock);
635 cprman_write(cprman, data->cm_ctrl_reg,
636 cprman_read(cprman, data->cm_ctrl_reg) |
637 CM_PLL_ANARST);
638 cprman_write(cprman, data->a2w_ctrl_reg,
639 cprman_read(cprman, data->a2w_ctrl_reg) |
640 A2W_PLL_CTRL_PWRDN);
641 spin_unlock(&cprman->regs_lock);
Eric Anholt41691b82015-10-08 18:37:24 -0700642}
643
644static int bcm2835_pll_on(struct clk_hw *hw)
645{
646 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
647 struct bcm2835_cprman *cprman = pll->cprman;
648 const struct bcm2835_pll_data *data = pll->data;
649 ktime_t timeout;
650
Eric Anholte708b382016-04-13 13:05:03 -0700651 cprman_write(cprman, data->a2w_ctrl_reg,
652 cprman_read(cprman, data->a2w_ctrl_reg) &
653 ~A2W_PLL_CTRL_PWRDN);
654
Eric Anholt41691b82015-10-08 18:37:24 -0700655 /* Take the PLL out of reset. */
656 cprman_write(cprman, data->cm_ctrl_reg,
657 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
658
659 /* Wait for the PLL to lock. */
660 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
661 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
662 if (ktime_after(ktime_get(), timeout)) {
663 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
664 clk_hw_get_name(hw));
665 return -ETIMEDOUT;
666 }
667
668 cpu_relax();
669 }
670
671 return 0;
672}
673
674static void
675bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)
676{
677 int i;
678
679 /*
680 * ANA register setup is done as a series of writes to
681 * ANA3-ANA0, in that order. This lets us write all 4
682 * registers as a single cycle of the serdes interface (taking
683 * 100 xosc clocks), whereas if we were to update ana0, 1, and
684 * 3 individually through their partial-write registers, each
685 * would be their own serdes cycle.
686 */
687 for (i = 3; i >= 0; i--)
688 cprman_write(cprman, ana_reg_base + i * 4, ana[i]);
689}
690
691static int bcm2835_pll_set_rate(struct clk_hw *hw,
692 unsigned long rate, unsigned long parent_rate)
693{
694 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
695 struct bcm2835_cprman *cprman = pll->cprman;
696 const struct bcm2835_pll_data *data = pll->data;
697 bool was_using_prediv, use_fb_prediv, do_ana_setup_first;
698 u32 ndiv, fdiv, a2w_ctl;
699 u32 ana[4];
700 int i;
701
Eric Anholt41691b82015-10-08 18:37:24 -0700702 if (rate > data->max_fb_rate) {
703 use_fb_prediv = true;
704 rate /= 2;
705 } else {
706 use_fb_prediv = false;
707 }
708
709 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);
710
711 for (i = 3; i >= 0; i--)
712 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
713
714 was_using_prediv = ana[1] & data->ana->fb_prediv_mask;
715
716 ana[0] &= ~data->ana->mask0;
717 ana[0] |= data->ana->set0;
718 ana[1] &= ~data->ana->mask1;
719 ana[1] |= data->ana->set1;
720 ana[3] &= ~data->ana->mask3;
721 ana[3] |= data->ana->set3;
722
723 if (was_using_prediv && !use_fb_prediv) {
724 ana[1] &= ~data->ana->fb_prediv_mask;
725 do_ana_setup_first = true;
726 } else if (!was_using_prediv && use_fb_prediv) {
727 ana[1] |= data->ana->fb_prediv_mask;
728 do_ana_setup_first = false;
729 } else {
730 do_ana_setup_first = true;
731 }
732
733 /* Unmask the reference clock from the oscillator. */
734 cprman_write(cprman, A2W_XOSC_CTRL,
735 cprman_read(cprman, A2W_XOSC_CTRL) |
736 data->reference_enable_mask);
737
738 if (do_ana_setup_first)
739 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
740
741 /* Set the PLL multiplier from the oscillator. */
742 cprman_write(cprman, data->frac_reg, fdiv);
743
744 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
745 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK;
746 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT;
747 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK;
748 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT;
749 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);
750
751 if (!do_ana_setup_first)
752 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
753
754 return 0;
755}
756
Martin Sperl96bf9c62016-02-29 14:20:15 +0000757static int bcm2835_pll_debug_init(struct clk_hw *hw,
758 struct dentry *dentry)
759{
760 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
761 struct bcm2835_cprman *cprman = pll->cprman;
762 const struct bcm2835_pll_data *data = pll->data;
763 struct debugfs_reg32 *regs;
764
765 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
766 if (!regs)
767 return -ENOMEM;
768
769 regs[0].name = "cm_ctrl";
770 regs[0].offset = data->cm_ctrl_reg;
771 regs[1].name = "a2w_ctrl";
772 regs[1].offset = data->a2w_ctrl_reg;
773 regs[2].name = "frac";
774 regs[2].offset = data->frac_reg;
775 regs[3].name = "ana0";
776 regs[3].offset = data->ana_reg_base + 0 * 4;
777 regs[4].name = "ana1";
778 regs[4].offset = data->ana_reg_base + 1 * 4;
779 regs[5].name = "ana2";
780 regs[5].offset = data->ana_reg_base + 2 * 4;
781 regs[6].name = "ana3";
782 regs[6].offset = data->ana_reg_base + 3 * 4;
783
784 return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
785}
786
Eric Anholt41691b82015-10-08 18:37:24 -0700787static const struct clk_ops bcm2835_pll_clk_ops = {
788 .is_prepared = bcm2835_pll_is_on,
789 .prepare = bcm2835_pll_on,
790 .unprepare = bcm2835_pll_off,
791 .recalc_rate = bcm2835_pll_get_rate,
792 .set_rate = bcm2835_pll_set_rate,
793 .round_rate = bcm2835_pll_round_rate,
Martin Sperl96bf9c62016-02-29 14:20:15 +0000794 .debug_init = bcm2835_pll_debug_init,
Eric Anholt41691b82015-10-08 18:37:24 -0700795};
796
797struct bcm2835_pll_divider {
798 struct clk_divider div;
799 struct bcm2835_cprman *cprman;
800 const struct bcm2835_pll_divider_data *data;
801};
802
803static struct bcm2835_pll_divider *
804bcm2835_pll_divider_from_hw(struct clk_hw *hw)
805{
806 return container_of(hw, struct bcm2835_pll_divider, div.hw);
807}
808
809static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
810{
811 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
812 struct bcm2835_cprman *cprman = divider->cprman;
813 const struct bcm2835_pll_divider_data *data = divider->data;
814
815 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
816}
817
818static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
819 unsigned long rate,
820 unsigned long *parent_rate)
821{
822 return clk_divider_ops.round_rate(hw, rate, parent_rate);
823}
824
825static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
826 unsigned long parent_rate)
827{
Eric Anholt79c1e2f2016-02-15 19:03:58 -0800828 return clk_divider_ops.recalc_rate(hw, parent_rate);
Eric Anholt41691b82015-10-08 18:37:24 -0700829}
830
831static void bcm2835_pll_divider_off(struct clk_hw *hw)
832{
833 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
834 struct bcm2835_cprman *cprman = divider->cprman;
835 const struct bcm2835_pll_divider_data *data = divider->data;
836
Martin Sperlec36a5c2016-02-29 11:39:18 +0000837 spin_lock(&cprman->regs_lock);
Eric Anholt41691b82015-10-08 18:37:24 -0700838 cprman_write(cprman, data->cm_reg,
839 (cprman_read(cprman, data->cm_reg) &
840 ~data->load_mask) | data->hold_mask);
Boris Brezillon68af4fa2016-12-01 20:27:21 +0100841 cprman_write(cprman, data->a2w_reg,
842 cprman_read(cprman, data->a2w_reg) |
843 A2W_PLL_CHANNEL_DISABLE);
Martin Sperlec36a5c2016-02-29 11:39:18 +0000844 spin_unlock(&cprman->regs_lock);
Eric Anholt41691b82015-10-08 18:37:24 -0700845}
846
847static int bcm2835_pll_divider_on(struct clk_hw *hw)
848{
849 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
850 struct bcm2835_cprman *cprman = divider->cprman;
851 const struct bcm2835_pll_divider_data *data = divider->data;
852
Martin Sperlec36a5c2016-02-29 11:39:18 +0000853 spin_lock(&cprman->regs_lock);
Eric Anholt41691b82015-10-08 18:37:24 -0700854 cprman_write(cprman, data->a2w_reg,
855 cprman_read(cprman, data->a2w_reg) &
856 ~A2W_PLL_CHANNEL_DISABLE);
857
858 cprman_write(cprman, data->cm_reg,
859 cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
Martin Sperlec36a5c2016-02-29 11:39:18 +0000860 spin_unlock(&cprman->regs_lock);
Eric Anholt41691b82015-10-08 18:37:24 -0700861
862 return 0;
863}
864
865static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
866 unsigned long rate,
867 unsigned long parent_rate)
868{
869 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
870 struct bcm2835_cprman *cprman = divider->cprman;
871 const struct bcm2835_pll_divider_data *data = divider->data;
Eric Anholt773b3962016-02-15 19:03:57 -0800872 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
Eric Anholt41691b82015-10-08 18:37:24 -0700873
Eric Anholt773b3962016-02-15 19:03:57 -0800874 div = DIV_ROUND_UP_ULL(parent_rate, rate);
Eric Anholt41691b82015-10-08 18:37:24 -0700875
Eric Anholt773b3962016-02-15 19:03:57 -0800876 div = min(div, max_div);
877 if (div == max_div)
878 div = 0;
879
880 cprman_write(cprman, data->a2w_reg, div);
Eric Anholt41691b82015-10-08 18:37:24 -0700881 cm = cprman_read(cprman, data->cm_reg);
882 cprman_write(cprman, data->cm_reg, cm | data->load_mask);
883 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
884
885 return 0;
886}
887
Martin Sperl96bf9c62016-02-29 14:20:15 +0000888static int bcm2835_pll_divider_debug_init(struct clk_hw *hw,
889 struct dentry *dentry)
890{
891 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
892 struct bcm2835_cprman *cprman = divider->cprman;
893 const struct bcm2835_pll_divider_data *data = divider->data;
894 struct debugfs_reg32 *regs;
895
896 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
897 if (!regs)
898 return -ENOMEM;
899
900 regs[0].name = "cm";
901 regs[0].offset = data->cm_reg;
902 regs[1].name = "a2w";
903 regs[1].offset = data->a2w_reg;
904
905 return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
906}
907
Eric Anholt41691b82015-10-08 18:37:24 -0700908static const struct clk_ops bcm2835_pll_divider_clk_ops = {
909 .is_prepared = bcm2835_pll_divider_is_on,
910 .prepare = bcm2835_pll_divider_on,
911 .unprepare = bcm2835_pll_divider_off,
912 .recalc_rate = bcm2835_pll_divider_get_rate,
913 .set_rate = bcm2835_pll_divider_set_rate,
914 .round_rate = bcm2835_pll_divider_round_rate,
Martin Sperl96bf9c62016-02-29 14:20:15 +0000915 .debug_init = bcm2835_pll_divider_debug_init,
Eric Anholt41691b82015-10-08 18:37:24 -0700916};
917
918/*
919 * The CM dividers do fixed-point division, so we can't use the
920 * generic integer divider code like the PLL dividers do (and we can't
921 * fake it by having some fixed shifts preceding it in the clock tree,
922 * because we'd run out of bits in a 32-bit unsigned long).
923 */
924struct bcm2835_clock {
925 struct clk_hw hw;
926 struct bcm2835_cprman *cprman;
927 const struct bcm2835_clock_data *data;
928};
929
930static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)
931{
932 return container_of(hw, struct bcm2835_clock, hw);
933}
934
935static int bcm2835_clock_is_on(struct clk_hw *hw)
936{
937 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
938 struct bcm2835_cprman *cprman = clock->cprman;
939 const struct bcm2835_clock_data *data = clock->data;
940
941 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;
942}
943
944static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
945 unsigned long rate,
Remi Pommarel9c95b322015-12-06 17:22:46 +0100946 unsigned long parent_rate,
947 bool round_up)
Eric Anholt41691b82015-10-08 18:37:24 -0700948{
949 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
950 const struct bcm2835_clock_data *data = clock->data;
Remi Pommarel9c95b322015-12-06 17:22:46 +0100951 u32 unused_frac_mask =
952 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
Eric Anholt41691b82015-10-08 18:37:24 -0700953 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
Remi Pommarel9c95b322015-12-06 17:22:46 +0100954 u64 rem;
Martin Sperl959ca922016-02-29 11:39:21 +0000955 u32 div, mindiv, maxdiv;
Eric Anholt41691b82015-10-08 18:37:24 -0700956
Remi Pommarel9c95b322015-12-06 17:22:46 +0100957 rem = do_div(temp, rate);
Eric Anholt41691b82015-10-08 18:37:24 -0700958 div = temp;
959
Remi Pommarel9c95b322015-12-06 17:22:46 +0100960 /* Round up and mask off the unused bits */
961 if (round_up && ((div & unused_frac_mask) != 0 || rem != 0))
962 div += unused_frac_mask + 1;
963 div &= ~unused_frac_mask;
Eric Anholt41691b82015-10-08 18:37:24 -0700964
Martin Sperl959ca922016-02-29 11:39:21 +0000965 /* different clamping limits apply for a mash clock */
966 if (data->is_mash_clock) {
967 /* clamp to min divider of 2 */
968 mindiv = 2 << CM_DIV_FRAC_BITS;
969 /* clamp to the highest possible integer divider */
970 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
971 } else {
972 /* clamp to min divider of 1 */
973 mindiv = 1 << CM_DIV_FRAC_BITS;
974 /* clamp to the highest possible fractional divider */
975 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
976 CM_DIV_FRAC_BITS - data->frac_bits);
977 }
978
979 /* apply the clamping limits */
980 div = max_t(u32, div, mindiv);
981 div = min_t(u32, div, maxdiv);
Eric Anholt41691b82015-10-08 18:37:24 -0700982
983 return div;
984}
985
986static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
987 unsigned long parent_rate,
988 u32 div)
989{
990 const struct bcm2835_clock_data *data = clock->data;
991 u64 temp;
992
Eric Anholt8a39e9f2017-01-18 07:31:56 +1100993 if (data->int_bits == 0 && data->frac_bits == 0)
994 return parent_rate;
995
Eric Anholt41691b82015-10-08 18:37:24 -0700996 /*
997 * The divisor is a 12.12 fixed point field, but only some of
998 * the bits are populated in any given clock.
999 */
1000 div >>= CM_DIV_FRAC_BITS - data->frac_bits;
1001 div &= (1 << (data->int_bits + data->frac_bits)) - 1;
1002
1003 if (div == 0)
1004 return 0;
1005
1006 temp = (u64)parent_rate << data->frac_bits;
1007
1008 do_div(temp, div);
1009
1010 return temp;
1011}
1012
Eric Anholt41691b82015-10-08 18:37:24 -07001013static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
1014 unsigned long parent_rate)
1015{
1016 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1017 struct bcm2835_cprman *cprman = clock->cprman;
1018 const struct bcm2835_clock_data *data = clock->data;
Eric Anholt8a39e9f2017-01-18 07:31:56 +11001019 u32 div;
1020
1021 if (data->int_bits == 0 && data->frac_bits == 0)
1022 return parent_rate;
1023
1024 div = cprman_read(cprman, data->div_reg);
Eric Anholt41691b82015-10-08 18:37:24 -07001025
1026 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
1027}
1028
1029static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
1030{
1031 struct bcm2835_cprman *cprman = clock->cprman;
1032 const struct bcm2835_clock_data *data = clock->data;
1033 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
1034
1035 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
1036 if (ktime_after(ktime_get(), timeout)) {
1037 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
1038 clk_hw_get_name(&clock->hw));
1039 return;
1040 }
1041 cpu_relax();
1042 }
1043}
1044
1045static void bcm2835_clock_off(struct clk_hw *hw)
1046{
1047 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1048 struct bcm2835_cprman *cprman = clock->cprman;
1049 const struct bcm2835_clock_data *data = clock->data;
1050
1051 spin_lock(&cprman->regs_lock);
1052 cprman_write(cprman, data->ctl_reg,
1053 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
1054 spin_unlock(&cprman->regs_lock);
1055
1056 /* BUSY will remain high until the divider completes its cycle. */
1057 bcm2835_clock_wait_busy(clock);
1058}
1059
1060static int bcm2835_clock_on(struct clk_hw *hw)
1061{
1062 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1063 struct bcm2835_cprman *cprman = clock->cprman;
1064 const struct bcm2835_clock_data *data = clock->data;
1065
1066 spin_lock(&cprman->regs_lock);
1067 cprman_write(cprman, data->ctl_reg,
1068 cprman_read(cprman, data->ctl_reg) |
1069 CM_ENABLE |
1070 CM_GATE);
1071 spin_unlock(&cprman->regs_lock);
1072
Eric Anholt3f919582017-01-18 07:31:57 +11001073 /* Debug code to measure the clock once it's turned on to see
1074 * if it's ticking at the rate we expect.
1075 */
1076 if (data->tcnt_mux && false) {
1077 dev_info(cprman->dev,
1078 "clk %s: rate %ld, measure %ld\n",
1079 data->name,
1080 clk_hw_get_rate(hw),
1081 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));
1082 }
1083
Eric Anholt41691b82015-10-08 18:37:24 -07001084 return 0;
1085}
1086
1087static int bcm2835_clock_set_rate(struct clk_hw *hw,
1088 unsigned long rate, unsigned long parent_rate)
1089{
1090 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1091 struct bcm2835_cprman *cprman = clock->cprman;
1092 const struct bcm2835_clock_data *data = clock->data;
Remi Pommarel9c95b322015-12-06 17:22:46 +01001093 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false);
Martin Sperl959ca922016-02-29 11:39:21 +00001094 u32 ctl;
1095
1096 spin_lock(&cprman->regs_lock);
1097
1098 /*
1099 * Setting up frac support
1100 *
1101 * In principle it is recommended to stop/start the clock first,
1102 * but as we set CLK_SET_RATE_GATE during registration of the
1103 * clock this requirement should be take care of by the
1104 * clk-framework.
1105 */
1106 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
1107 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
1108 cprman_write(cprman, data->ctl_reg, ctl);
Eric Anholt41691b82015-10-08 18:37:24 -07001109
1110 cprman_write(cprman, data->div_reg, div);
1111
Martin Sperl959ca922016-02-29 11:39:21 +00001112 spin_unlock(&cprman->regs_lock);
1113
Eric Anholt41691b82015-10-08 18:37:24 -07001114 return 0;
1115}
1116
Eric Anholt67615c52016-06-01 12:05:36 -07001117static bool
1118bcm2835_clk_is_pllc(struct clk_hw *hw)
1119{
1120 if (!hw)
1121 return false;
1122
1123 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;
1124}
1125
Boris Brezillon155e8b32016-12-01 22:00:19 +01001126static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
1127 int parent_idx,
1128 unsigned long rate,
1129 u32 *div,
Phil Elwell35429762017-06-01 15:14:22 +01001130 unsigned long *prate,
1131 unsigned long *avgrate)
Boris Brezillon155e8b32016-12-01 22:00:19 +01001132{
1133 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1134 struct bcm2835_cprman *cprman = clock->cprman;
1135 const struct bcm2835_clock_data *data = clock->data;
Boris Brezillon2aab7a22016-12-12 09:00:53 +01001136 unsigned long best_rate = 0;
Boris Brezillon155e8b32016-12-01 22:00:19 +01001137 u32 curdiv, mindiv, maxdiv;
1138 struct clk_hw *parent;
1139
1140 parent = clk_hw_get_parent_by_index(hw, parent_idx);
1141
1142 if (!(BIT(parent_idx) & data->set_rate_parent)) {
1143 *prate = clk_hw_get_rate(parent);
1144 *div = bcm2835_clock_choose_div(hw, rate, *prate, true);
1145
Phil Elwell35429762017-06-01 15:14:22 +01001146 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
1147
1148 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {
1149 unsigned long high, low;
1150 u32 int_div = *div & ~CM_DIV_FRAC_MASK;
1151
1152 high = bcm2835_clock_rate_from_divisor(clock, *prate,
1153 int_div);
1154 int_div += CM_DIV_FRAC_MASK + 1;
1155 low = bcm2835_clock_rate_from_divisor(clock, *prate,
1156 int_div);
1157
1158 /*
1159 * Return a value which is the maximum deviation
1160 * below the ideal rate, for use as a metric.
1161 */
1162 return *avgrate - max(*avgrate - low, high - *avgrate);
1163 }
1164 return *avgrate;
Boris Brezillon155e8b32016-12-01 22:00:19 +01001165 }
1166
1167 if (data->frac_bits)
1168 dev_warn(cprman->dev,
1169 "frac bits are not used when propagating rate change");
1170
1171 /* clamp to min divider of 2 if we're dealing with a mash clock */
1172 mindiv = data->is_mash_clock ? 2 : 1;
1173 maxdiv = BIT(data->int_bits) - 1;
1174
1175 /* TODO: Be smart, and only test a subset of the available divisors. */
1176 for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) {
1177 unsigned long tmp_rate;
1178
1179 tmp_rate = clk_hw_round_rate(parent, rate * curdiv);
1180 tmp_rate /= curdiv;
1181 if (curdiv == mindiv ||
1182 (tmp_rate > best_rate && tmp_rate <= rate))
1183 best_rate = tmp_rate;
1184
1185 if (best_rate == rate)
1186 break;
1187 }
1188
1189 *div = curdiv << CM_DIV_FRAC_BITS;
1190 *prate = curdiv * best_rate;
Phil Elwell35429762017-06-01 15:14:22 +01001191 *avgrate = best_rate;
Boris Brezillon155e8b32016-12-01 22:00:19 +01001192
1193 return best_rate;
1194}
1195
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001196static int bcm2835_clock_determine_rate(struct clk_hw *hw,
Martin Sperl6e1e60d2016-02-29 11:39:22 +00001197 struct clk_rate_request *req)
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001198{
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001199 struct clk_hw *parent, *best_parent = NULL;
Eric Anholt67615c52016-06-01 12:05:36 -07001200 bool current_parent_is_pllc;
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001201 unsigned long rate, best_rate = 0;
1202 unsigned long prate, best_prate = 0;
Phil Elwell35429762017-06-01 15:14:22 +01001203 unsigned long avgrate, best_avgrate = 0;
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001204 size_t i;
1205 u32 div;
1206
Eric Anholt67615c52016-06-01 12:05:36 -07001207 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw));
1208
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001209 /*
1210 * Select parent clock that results in the closest but lower rate
1211 */
1212 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
1213 parent = clk_hw_get_parent_by_index(hw, i);
1214 if (!parent)
1215 continue;
Eric Anholt67615c52016-06-01 12:05:36 -07001216
1217 /*
1218 * Don't choose a PLLC-derived clock as our parent
1219 * unless it had been manually set that way. PLLC's
1220 * frequency gets adjusted by the firmware due to
1221 * over-temp or under-voltage conditions, without
1222 * prior notification to our clock consumer.
1223 */
1224 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)
1225 continue;
1226
Boris Brezillon155e8b32016-12-01 22:00:19 +01001227 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
Phil Elwell35429762017-06-01 15:14:22 +01001228 &div, &prate,
1229 &avgrate);
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001230 if (rate > best_rate && rate <= req->rate) {
1231 best_parent = parent;
1232 best_prate = prate;
1233 best_rate = rate;
Phil Elwell35429762017-06-01 15:14:22 +01001234 best_avgrate = avgrate;
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001235 }
1236 }
1237
1238 if (!best_parent)
1239 return -EINVAL;
1240
1241 req->best_parent_hw = best_parent;
1242 req->best_parent_rate = best_prate;
1243
Phil Elwell35429762017-06-01 15:14:22 +01001244 req->rate = best_avgrate;
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001245
1246 return 0;
1247}
1248
1249static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
1250{
1251 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1252 struct bcm2835_cprman *cprman = clock->cprman;
1253 const struct bcm2835_clock_data *data = clock->data;
1254 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
1255
1256 cprman_write(cprman, data->ctl_reg, src);
1257 return 0;
1258}
1259
1260static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
1261{
1262 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1263 struct bcm2835_cprman *cprman = clock->cprman;
1264 const struct bcm2835_clock_data *data = clock->data;
1265 u32 src = cprman_read(cprman, data->ctl_reg);
1266
1267 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
1268}
1269
Martin Sperl96bf9c62016-02-29 14:20:15 +00001270static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
1271 {
1272 .name = "ctl",
1273 .offset = 0,
1274 },
1275 {
1276 .name = "div",
1277 .offset = 4,
1278 },
1279};
1280
1281static int bcm2835_clock_debug_init(struct clk_hw *hw,
1282 struct dentry *dentry)
1283{
1284 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1285 struct bcm2835_cprman *cprman = clock->cprman;
1286 const struct bcm2835_clock_data *data = clock->data;
1287
1288 return bcm2835_debugfs_regset(
1289 cprman, data->ctl_reg,
1290 bcm2835_debugfs_clock_reg32,
1291 ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
1292 dentry);
1293}
1294
Eric Anholt41691b82015-10-08 18:37:24 -07001295static const struct clk_ops bcm2835_clock_clk_ops = {
1296 .is_prepared = bcm2835_clock_is_on,
1297 .prepare = bcm2835_clock_on,
1298 .unprepare = bcm2835_clock_off,
1299 .recalc_rate = bcm2835_clock_get_rate,
1300 .set_rate = bcm2835_clock_set_rate,
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001301 .determine_rate = bcm2835_clock_determine_rate,
1302 .set_parent = bcm2835_clock_set_parent,
1303 .get_parent = bcm2835_clock_get_parent,
Martin Sperl96bf9c62016-02-29 14:20:15 +00001304 .debug_init = bcm2835_clock_debug_init,
Eric Anholt41691b82015-10-08 18:37:24 -07001305};
1306
1307static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
1308{
1309 return true;
1310}
1311
1312/*
1313 * The VPU clock can never be disabled (it doesn't have an ENABLE
1314 * bit), so it gets its own set of clock ops.
1315 */
1316static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
1317 .is_prepared = bcm2835_vpu_clock_is_on,
1318 .recalc_rate = bcm2835_clock_get_rate,
1319 .set_rate = bcm2835_clock_set_rate,
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001320 .determine_rate = bcm2835_clock_determine_rate,
1321 .set_parent = bcm2835_clock_set_parent,
1322 .get_parent = bcm2835_clock_get_parent,
Martin Sperl96bf9c62016-02-29 14:20:15 +00001323 .debug_init = bcm2835_clock_debug_init,
Eric Anholt41691b82015-10-08 18:37:24 -07001324};
1325
Stephen Boydb19f0092016-06-01 16:15:03 -07001326static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
1327 const struct bcm2835_pll_data *data)
Eric Anholt41691b82015-10-08 18:37:24 -07001328{
1329 struct bcm2835_pll *pll;
1330 struct clk_init_data init;
Stephen Boydb19f0092016-06-01 16:15:03 -07001331 int ret;
Eric Anholt41691b82015-10-08 18:37:24 -07001332
1333 memset(&init, 0, sizeof(init));
1334
1335 /* All of the PLLs derive from the external oscillator. */
Eric Anholt8a39e9f2017-01-18 07:31:56 +11001336 init.parent_names = &cprman->real_parent_names[0];
Eric Anholt41691b82015-10-08 18:37:24 -07001337 init.num_parents = 1;
1338 init.name = data->name;
1339 init.ops = &bcm2835_pll_clk_ops;
1340 init.flags = CLK_IGNORE_UNUSED;
1341
1342 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1343 if (!pll)
1344 return NULL;
1345
1346 pll->cprman = cprman;
1347 pll->data = data;
1348 pll->hw.init = &init;
1349
Stephen Boydb19f0092016-06-01 16:15:03 -07001350 ret = devm_clk_hw_register(cprman->dev, &pll->hw);
1351 if (ret)
1352 return NULL;
1353 return &pll->hw;
Eric Anholt41691b82015-10-08 18:37:24 -07001354}
1355
Stephen Boydb19f0092016-06-01 16:15:03 -07001356static struct clk_hw *
Eric Anholt41691b82015-10-08 18:37:24 -07001357bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
1358 const struct bcm2835_pll_divider_data *data)
1359{
1360 struct bcm2835_pll_divider *divider;
1361 struct clk_init_data init;
Eric Anholt41691b82015-10-08 18:37:24 -07001362 const char *divider_name;
Stephen Boydb19f0092016-06-01 16:15:03 -07001363 int ret;
Eric Anholt41691b82015-10-08 18:37:24 -07001364
1365 if (data->fixed_divider != 1) {
1366 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
1367 "%s_prediv", data->name);
1368 if (!divider_name)
1369 return NULL;
1370 } else {
1371 divider_name = data->name;
1372 }
1373
1374 memset(&init, 0, sizeof(init));
1375
Martin Sperl3b15afe2016-02-29 12:51:42 +00001376 init.parent_names = &data->source_pll;
Eric Anholt41691b82015-10-08 18:37:24 -07001377 init.num_parents = 1;
1378 init.name = divider_name;
1379 init.ops = &bcm2835_pll_divider_clk_ops;
Eric Anholt55486092017-01-18 07:31:55 +11001380 init.flags = data->flags | CLK_IGNORE_UNUSED;
Eric Anholt41691b82015-10-08 18:37:24 -07001381
1382 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
1383 if (!divider)
1384 return NULL;
1385
1386 divider->div.reg = cprman->regs + data->a2w_reg;
1387 divider->div.shift = A2W_PLL_DIV_SHIFT;
1388 divider->div.width = A2W_PLL_DIV_BITS;
Eric Anholt79c1e2f2016-02-15 19:03:58 -08001389 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
Eric Anholt41691b82015-10-08 18:37:24 -07001390 divider->div.lock = &cprman->regs_lock;
1391 divider->div.hw.init = &init;
1392 divider->div.table = NULL;
1393
1394 divider->cprman = cprman;
1395 divider->data = data;
1396
Stephen Boydb19f0092016-06-01 16:15:03 -07001397 ret = devm_clk_hw_register(cprman->dev, &divider->div.hw);
1398 if (ret)
1399 return ERR_PTR(ret);
Eric Anholt41691b82015-10-08 18:37:24 -07001400
1401 /*
1402 * PLLH's channels have a fixed divide by 10 afterwards, which
1403 * is what our consumers are actually using.
1404 */
1405 if (data->fixed_divider != 1) {
Stephen Boydb19f0092016-06-01 16:15:03 -07001406 return clk_hw_register_fixed_factor(cprman->dev, data->name,
1407 divider_name,
1408 CLK_SET_RATE_PARENT,
1409 1,
1410 data->fixed_divider);
Eric Anholt41691b82015-10-08 18:37:24 -07001411 }
1412
Stephen Boydb19f0092016-06-01 16:15:03 -07001413 return &divider->div.hw;
Eric Anholt41691b82015-10-08 18:37:24 -07001414}
1415
Stephen Boydb19f0092016-06-01 16:15:03 -07001416static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
Eric Anholt41691b82015-10-08 18:37:24 -07001417 const struct bcm2835_clock_data *data)
1418{
1419 struct bcm2835_clock *clock;
1420 struct clk_init_data init;
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001421 const char *parents[1 << CM_SRC_BITS];
Eric Anholt8a39e9f2017-01-18 07:31:56 +11001422 size_t i, j;
Stephen Boydb19f0092016-06-01 16:15:03 -07001423 int ret;
Eric Anholt41691b82015-10-08 18:37:24 -07001424
1425 /*
Eric Anholt8a39e9f2017-01-18 07:31:56 +11001426 * Replace our strings referencing parent clocks with the
1427 * actual clock-output-name of the parent.
Eric Anholt41691b82015-10-08 18:37:24 -07001428 */
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001429 for (i = 0; i < data->num_mux_parents; i++) {
Eric Anholt8a39e9f2017-01-18 07:31:56 +11001430 parents[i] = data->parents[i];
1431
1432 for (j = 0; j < ARRAY_SIZE(cprman_parent_names); j++) {
1433 if (strcmp(parents[i], cprman_parent_names[j]) == 0) {
1434 parents[i] = cprman->real_parent_names[j];
1435 break;
1436 }
1437 }
Eric Anholt41691b82015-10-08 18:37:24 -07001438 }
1439
1440 memset(&init, 0, sizeof(init));
Remi Pommarel6d18b8a2015-12-06 17:22:47 +01001441 init.parent_names = parents;
1442 init.num_parents = data->num_mux_parents;
Eric Anholt41691b82015-10-08 18:37:24 -07001443 init.name = data->name;
Eric Anholte69fdcc2016-06-01 12:05:33 -07001444 init.flags = data->flags | CLK_IGNORE_UNUSED;
Eric Anholt41691b82015-10-08 18:37:24 -07001445
Boris Brezillon155e8b32016-12-01 22:00:19 +01001446 /*
1447 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
1448 * rate changes on at least of the parents.
1449 */
1450 if (data->set_rate_parent)
1451 init.flags |= CLK_SET_RATE_PARENT;
1452
Eric Anholt41691b82015-10-08 18:37:24 -07001453 if (data->is_vpu_clock) {
1454 init.ops = &bcm2835_vpu_clock_clk_ops;
1455 } else {
1456 init.ops = &bcm2835_clock_clk_ops;
1457 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
Eric Anholteddcbe832016-06-01 12:05:34 -07001458
1459 /* If the clock wasn't actually enabled at boot, it's not
1460 * critical.
1461 */
1462 if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE))
1463 init.flags &= ~CLK_IS_CRITICAL;
Eric Anholt41691b82015-10-08 18:37:24 -07001464 }
1465
1466 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1467 if (!clock)
1468 return NULL;
1469
1470 clock->cprman = cprman;
1471 clock->data = data;
1472 clock->hw.init = &init;
1473
Stephen Boydb19f0092016-06-01 16:15:03 -07001474 ret = devm_clk_hw_register(cprman->dev, &clock->hw);
1475 if (ret)
1476 return ERR_PTR(ret);
1477 return &clock->hw;
Eric Anholt41691b82015-10-08 18:37:24 -07001478}
1479
Martin Sperl56eb3a22016-02-29 12:51:41 +00001480static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman,
1481 const struct bcm2835_gate_data *data)
1482{
1483 return clk_register_gate(cprman->dev, data->name, data->parent,
1484 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1485 cprman->regs + data->ctl_reg,
1486 CM_GATE_BIT, 0, &cprman->regs_lock);
1487}
1488
Stephen Boydb19f0092016-06-01 16:15:03 -07001489typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
1490 const void *data);
Martin Sperl56eb3a22016-02-29 12:51:41 +00001491struct bcm2835_clk_desc {
1492 bcm2835_clk_register clk_register;
1493 const void *data;
1494};
1495
Martin Sperl3b15afe2016-02-29 12:51:42 +00001496/* assignment helper macros for different clock types */
1497#define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
1498 .data = __VA_ARGS__ }
1499#define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \
1500 &(struct bcm2835_pll_data) \
1501 {__VA_ARGS__})
1502#define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \
1503 &(struct bcm2835_pll_divider_data) \
1504 {__VA_ARGS__})
1505#define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \
1506 &(struct bcm2835_clock_data) \
1507 {__VA_ARGS__})
1508#define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \
1509 &(struct bcm2835_gate_data) \
1510 {__VA_ARGS__})
Martin Sperl56eb3a22016-02-29 12:51:41 +00001511
Martin Sperl3b15afe2016-02-29 12:51:42 +00001512/* parent mux arrays plus helper macros */
1513
1514/* main oscillator parent mux */
1515static const char *const bcm2835_clock_osc_parents[] = {
1516 "gnd",
1517 "xosc",
1518 "testdebug0",
1519 "testdebug1"
1520};
1521
1522#define REGISTER_OSC_CLK(...) REGISTER_CLK( \
1523 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1524 .parents = bcm2835_clock_osc_parents, \
1525 __VA_ARGS__)
1526
1527/* main peripherial parent mux */
1528static const char *const bcm2835_clock_per_parents[] = {
1529 "gnd",
1530 "xosc",
1531 "testdebug0",
1532 "testdebug1",
1533 "plla_per",
1534 "pllc_per",
1535 "plld_per",
1536 "pllh_aux",
1537};
1538
1539#define REGISTER_PER_CLK(...) REGISTER_CLK( \
1540 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1541 .parents = bcm2835_clock_per_parents, \
1542 __VA_ARGS__)
1543
Phil Elwell8c0de582017-06-01 15:14:16 +01001544/*
1545 * Restrict clock sources for the PCM peripheral to the oscillator and
1546 * PLLD_PER because other source may have varying rates or be switched
1547 * off.
1548 *
1549 * Prevent other sources from being selected by replacing their names in
1550 * the list of potential parents with dummy entries (entry index is
1551 * significant).
1552 */
1553static const char *const bcm2835_pcm_per_parents[] = {
1554 "-",
1555 "xosc",
1556 "-",
1557 "-",
1558 "-",
1559 "-",
1560 "plld_per",
1561 "-",
1562};
1563
1564#define REGISTER_PCM_CLK(...) REGISTER_CLK( \
1565 .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \
1566 .parents = bcm2835_pcm_per_parents, \
1567 __VA_ARGS__)
1568
Martin Sperl3b15afe2016-02-29 12:51:42 +00001569/* main vpu parent mux */
1570static const char *const bcm2835_clock_vpu_parents[] = {
1571 "gnd",
1572 "xosc",
1573 "testdebug0",
1574 "testdebug1",
1575 "plla_core",
1576 "pllc_core0",
1577 "plld_core",
1578 "pllh_aux",
1579 "pllc_core1",
1580 "pllc_core2",
1581};
1582
1583#define REGISTER_VPU_CLK(...) REGISTER_CLK( \
1584 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1585 .parents = bcm2835_clock_vpu_parents, \
1586 __VA_ARGS__)
1587
1588/*
Eric Anholt8a39e9f2017-01-18 07:31:56 +11001589 * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI
1590 * analog PHY. The _inv variants are generated internally to cprman,
1591 * but we don't use them so they aren't hooked up.
1592 */
1593static const char *const bcm2835_clock_dsi0_parents[] = {
1594 "gnd",
1595 "xosc",
1596 "testdebug0",
1597 "testdebug1",
1598 "dsi0_ddr",
1599 "dsi0_ddr_inv",
1600 "dsi0_ddr2",
1601 "dsi0_ddr2_inv",
1602 "dsi0_byte",
1603 "dsi0_byte_inv",
1604};
1605
1606static const char *const bcm2835_clock_dsi1_parents[] = {
1607 "gnd",
1608 "xosc",
1609 "testdebug0",
1610 "testdebug1",
1611 "dsi1_ddr",
1612 "dsi1_ddr_inv",
1613 "dsi1_ddr2",
1614 "dsi1_ddr2_inv",
1615 "dsi1_byte",
1616 "dsi1_byte_inv",
1617};
1618
1619#define REGISTER_DSI0_CLK(...) REGISTER_CLK( \
1620 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \
1621 .parents = bcm2835_clock_dsi0_parents, \
1622 __VA_ARGS__)
1623
1624#define REGISTER_DSI1_CLK(...) REGISTER_CLK( \
1625 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
1626 .parents = bcm2835_clock_dsi1_parents, \
1627 __VA_ARGS__)
1628
1629/*
Martin Sperl3b15afe2016-02-29 12:51:42 +00001630 * the real definition of all the pll, pll_dividers and clocks
1631 * these make use of the above REGISTER_* macros
1632 */
Martin Sperl56eb3a22016-02-29 12:51:41 +00001633static const struct bcm2835_clk_desc clk_desc_array[] = {
Martin Sperl3b15afe2016-02-29 12:51:42 +00001634 /* the PLL + PLL dividers */
1635
1636 /*
1637 * PLLA is the auxiliary PLL, used to drive the CCP2
1638 * (Compact Camera Port 2) transmitter clock.
1639 *
1640 * It is in the PX LDO power domain, which is on when the
1641 * AUDIO domain is on.
1642 */
1643 [BCM2835_PLLA] = REGISTER_PLL(
1644 .name = "plla",
1645 .cm_ctrl_reg = CM_PLLA,
1646 .a2w_ctrl_reg = A2W_PLLA_CTRL,
1647 .frac_reg = A2W_PLLA_FRAC,
1648 .ana_reg_base = A2W_PLLA_ANA0,
1649 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
1650 .lock_mask = CM_LOCK_FLOCKA,
1651
1652 .ana = &bcm2835_ana_default,
1653
1654 .min_rate = 600000000u,
1655 .max_rate = 2400000000u,
1656 .max_fb_rate = BCM2835_MAX_FB_RATE),
1657 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
1658 .name = "plla_core",
1659 .source_pll = "plla",
1660 .cm_reg = CM_PLLA,
1661 .a2w_reg = A2W_PLLA_CORE,
1662 .load_mask = CM_PLLA_LOADCORE,
1663 .hold_mask = CM_PLLA_HOLDCORE,
Eric Anholt55486092017-01-18 07:31:55 +11001664 .fixed_divider = 1,
1665 .flags = CLK_SET_RATE_PARENT),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001666 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
1667 .name = "plla_per",
1668 .source_pll = "plla",
1669 .cm_reg = CM_PLLA,
1670 .a2w_reg = A2W_PLLA_PER,
1671 .load_mask = CM_PLLA_LOADPER,
1672 .hold_mask = CM_PLLA_HOLDPER,
Eric Anholt55486092017-01-18 07:31:55 +11001673 .fixed_divider = 1,
1674 .flags = CLK_SET_RATE_PARENT),
Martin Sperl72843692016-02-29 15:43:56 +00001675 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
1676 .name = "plla_dsi0",
1677 .source_pll = "plla",
1678 .cm_reg = CM_PLLA,
1679 .a2w_reg = A2W_PLLA_DSI0,
1680 .load_mask = CM_PLLA_LOADDSI0,
1681 .hold_mask = CM_PLLA_HOLDDSI0,
1682 .fixed_divider = 1),
1683 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
1684 .name = "plla_ccp2",
1685 .source_pll = "plla",
1686 .cm_reg = CM_PLLA,
1687 .a2w_reg = A2W_PLLA_CCP2,
1688 .load_mask = CM_PLLA_LOADCCP2,
1689 .hold_mask = CM_PLLA_HOLDCCP2,
Eric Anholt55486092017-01-18 07:31:55 +11001690 .fixed_divider = 1,
1691 .flags = CLK_SET_RATE_PARENT),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001692
1693 /* PLLB is used for the ARM's clock. */
1694 [BCM2835_PLLB] = REGISTER_PLL(
1695 .name = "pllb",
1696 .cm_ctrl_reg = CM_PLLB,
1697 .a2w_ctrl_reg = A2W_PLLB_CTRL,
1698 .frac_reg = A2W_PLLB_FRAC,
1699 .ana_reg_base = A2W_PLLB_ANA0,
1700 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
1701 .lock_mask = CM_LOCK_FLOCKB,
1702
1703 .ana = &bcm2835_ana_default,
1704
1705 .min_rate = 600000000u,
1706 .max_rate = 3000000000u,
1707 .max_fb_rate = BCM2835_MAX_FB_RATE),
1708 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
1709 .name = "pllb_arm",
1710 .source_pll = "pllb",
1711 .cm_reg = CM_PLLB,
1712 .a2w_reg = A2W_PLLB_ARM,
1713 .load_mask = CM_PLLB_LOADARM,
1714 .hold_mask = CM_PLLB_HOLDARM,
Eric Anholt55486092017-01-18 07:31:55 +11001715 .fixed_divider = 1,
1716 .flags = CLK_SET_RATE_PARENT),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001717
1718 /*
1719 * PLLC is the core PLL, used to drive the core VPU clock.
1720 *
1721 * It is in the PX LDO power domain, which is on when the
1722 * AUDIO domain is on.
1723 */
1724 [BCM2835_PLLC] = REGISTER_PLL(
1725 .name = "pllc",
1726 .cm_ctrl_reg = CM_PLLC,
1727 .a2w_ctrl_reg = A2W_PLLC_CTRL,
1728 .frac_reg = A2W_PLLC_FRAC,
1729 .ana_reg_base = A2W_PLLC_ANA0,
1730 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1731 .lock_mask = CM_LOCK_FLOCKC,
1732
1733 .ana = &bcm2835_ana_default,
1734
1735 .min_rate = 600000000u,
1736 .max_rate = 3000000000u,
1737 .max_fb_rate = BCM2835_MAX_FB_RATE),
1738 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
1739 .name = "pllc_core0",
1740 .source_pll = "pllc",
1741 .cm_reg = CM_PLLC,
1742 .a2w_reg = A2W_PLLC_CORE0,
1743 .load_mask = CM_PLLC_LOADCORE0,
1744 .hold_mask = CM_PLLC_HOLDCORE0,
Eric Anholt55486092017-01-18 07:31:55 +11001745 .fixed_divider = 1,
1746 .flags = CLK_SET_RATE_PARENT),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001747 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
1748 .name = "pllc_core1",
1749 .source_pll = "pllc",
1750 .cm_reg = CM_PLLC,
1751 .a2w_reg = A2W_PLLC_CORE1,
1752 .load_mask = CM_PLLC_LOADCORE1,
1753 .hold_mask = CM_PLLC_HOLDCORE1,
Eric Anholt55486092017-01-18 07:31:55 +11001754 .fixed_divider = 1,
1755 .flags = CLK_SET_RATE_PARENT),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001756 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
1757 .name = "pllc_core2",
1758 .source_pll = "pllc",
1759 .cm_reg = CM_PLLC,
1760 .a2w_reg = A2W_PLLC_CORE2,
1761 .load_mask = CM_PLLC_LOADCORE2,
1762 .hold_mask = CM_PLLC_HOLDCORE2,
Eric Anholt55486092017-01-18 07:31:55 +11001763 .fixed_divider = 1,
1764 .flags = CLK_SET_RATE_PARENT),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001765 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
1766 .name = "pllc_per",
1767 .source_pll = "pllc",
1768 .cm_reg = CM_PLLC,
1769 .a2w_reg = A2W_PLLC_PER,
1770 .load_mask = CM_PLLC_LOADPER,
1771 .hold_mask = CM_PLLC_HOLDPER,
Eric Anholt55486092017-01-18 07:31:55 +11001772 .fixed_divider = 1,
1773 .flags = CLK_SET_RATE_PARENT),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001774
1775 /*
1776 * PLLD is the display PLL, used to drive DSI display panels.
1777 *
1778 * It is in the PX LDO power domain, which is on when the
1779 * AUDIO domain is on.
1780 */
1781 [BCM2835_PLLD] = REGISTER_PLL(
1782 .name = "plld",
1783 .cm_ctrl_reg = CM_PLLD,
1784 .a2w_ctrl_reg = A2W_PLLD_CTRL,
1785 .frac_reg = A2W_PLLD_FRAC,
1786 .ana_reg_base = A2W_PLLD_ANA0,
1787 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
1788 .lock_mask = CM_LOCK_FLOCKD,
1789
1790 .ana = &bcm2835_ana_default,
1791
1792 .min_rate = 600000000u,
1793 .max_rate = 2400000000u,
1794 .max_fb_rate = BCM2835_MAX_FB_RATE),
1795 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
1796 .name = "plld_core",
1797 .source_pll = "plld",
1798 .cm_reg = CM_PLLD,
1799 .a2w_reg = A2W_PLLD_CORE,
1800 .load_mask = CM_PLLD_LOADCORE,
1801 .hold_mask = CM_PLLD_HOLDCORE,
Eric Anholt55486092017-01-18 07:31:55 +11001802 .fixed_divider = 1,
1803 .flags = CLK_SET_RATE_PARENT),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001804 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
1805 .name = "plld_per",
1806 .source_pll = "plld",
1807 .cm_reg = CM_PLLD,
1808 .a2w_reg = A2W_PLLD_PER,
1809 .load_mask = CM_PLLD_LOADPER,
1810 .hold_mask = CM_PLLD_HOLDPER,
Eric Anholt55486092017-01-18 07:31:55 +11001811 .fixed_divider = 1,
1812 .flags = CLK_SET_RATE_PARENT),
Martin Sperl72843692016-02-29 15:43:56 +00001813 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
1814 .name = "plld_dsi0",
1815 .source_pll = "plld",
1816 .cm_reg = CM_PLLD,
1817 .a2w_reg = A2W_PLLD_DSI0,
1818 .load_mask = CM_PLLD_LOADDSI0,
1819 .hold_mask = CM_PLLD_HOLDDSI0,
1820 .fixed_divider = 1),
1821 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
1822 .name = "plld_dsi1",
1823 .source_pll = "plld",
1824 .cm_reg = CM_PLLD,
1825 .a2w_reg = A2W_PLLD_DSI1,
1826 .load_mask = CM_PLLD_LOADDSI1,
1827 .hold_mask = CM_PLLD_HOLDDSI1,
1828 .fixed_divider = 1),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001829
1830 /*
1831 * PLLH is used to supply the pixel clock or the AUX clock for the
1832 * TV encoder.
1833 *
1834 * It is in the HDMI power domain.
1835 */
1836 [BCM2835_PLLH] = REGISTER_PLL(
1837 "pllh",
1838 .cm_ctrl_reg = CM_PLLH,
1839 .a2w_ctrl_reg = A2W_PLLH_CTRL,
1840 .frac_reg = A2W_PLLH_FRAC,
1841 .ana_reg_base = A2W_PLLH_ANA0,
1842 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1843 .lock_mask = CM_LOCK_FLOCKH,
1844
1845 .ana = &bcm2835_ana_pllh,
1846
1847 .min_rate = 600000000u,
1848 .max_rate = 3000000000u,
1849 .max_fb_rate = BCM2835_MAX_FB_RATE),
1850 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
1851 .name = "pllh_rcal",
1852 .source_pll = "pllh",
1853 .cm_reg = CM_PLLH,
1854 .a2w_reg = A2W_PLLH_RCAL,
1855 .load_mask = CM_PLLH_LOADRCAL,
1856 .hold_mask = 0,
Eric Anholt55486092017-01-18 07:31:55 +11001857 .fixed_divider = 10,
1858 .flags = CLK_SET_RATE_PARENT),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001859 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
1860 .name = "pllh_aux",
1861 .source_pll = "pllh",
1862 .cm_reg = CM_PLLH,
1863 .a2w_reg = A2W_PLLH_AUX,
1864 .load_mask = CM_PLLH_LOADAUX,
1865 .hold_mask = 0,
Eric Anholt55486092017-01-18 07:31:55 +11001866 .fixed_divider = 1,
1867 .flags = CLK_SET_RATE_PARENT),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001868 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
1869 .name = "pllh_pix",
1870 .source_pll = "pllh",
1871 .cm_reg = CM_PLLH,
1872 .a2w_reg = A2W_PLLH_PIX,
1873 .load_mask = CM_PLLH_LOADPIX,
1874 .hold_mask = 0,
Eric Anholt55486092017-01-18 07:31:55 +11001875 .fixed_divider = 10,
1876 .flags = CLK_SET_RATE_PARENT),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001877
Martin Sperl56eb3a22016-02-29 12:51:41 +00001878 /* the clocks */
Martin Sperl3b15afe2016-02-29 12:51:42 +00001879
1880 /* clocks with oscillator parent mux */
1881
1882 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1883 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
1884 .name = "otp",
1885 .ctl_reg = CM_OTPCTL,
1886 .div_reg = CM_OTPDIV,
1887 .int_bits = 4,
Eric Anholt3f919582017-01-18 07:31:57 +11001888 .frac_bits = 0,
1889 .tcnt_mux = 6),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001890 /*
1891 * Used for a 1Mhz clock for the system clocksource, and also used
1892 * bythe watchdog timer and the camera pulse generator.
1893 */
1894 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
1895 .name = "timer",
1896 .ctl_reg = CM_TIMERCTL,
1897 .div_reg = CM_TIMERDIV,
1898 .int_bits = 6,
1899 .frac_bits = 12),
1900 /*
1901 * Clock for the temperature sensor.
1902 * Generally run at 2Mhz, max 5Mhz.
1903 */
1904 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
1905 .name = "tsens",
1906 .ctl_reg = CM_TSENSCTL,
1907 .div_reg = CM_TSENSDIV,
1908 .int_bits = 5,
1909 .frac_bits = 0),
Martin Sperld3d6f152016-02-29 15:43:57 +00001910 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
1911 .name = "tec",
1912 .ctl_reg = CM_TECCTL,
1913 .div_reg = CM_TECDIV,
1914 .int_bits = 6,
1915 .frac_bits = 0),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001916
1917 /* clocks with vpu parent mux */
1918 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
1919 .name = "h264",
1920 .ctl_reg = CM_H264CTL,
1921 .div_reg = CM_H264DIV,
1922 .int_bits = 4,
Eric Anholt3f919582017-01-18 07:31:57 +11001923 .frac_bits = 8,
1924 .tcnt_mux = 1),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001925 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
1926 .name = "isp",
1927 .ctl_reg = CM_ISPCTL,
1928 .div_reg = CM_ISPDIV,
1929 .int_bits = 4,
Eric Anholt3f919582017-01-18 07:31:57 +11001930 .frac_bits = 8,
1931 .tcnt_mux = 2),
Martin Sperld3d6f152016-02-29 15:43:57 +00001932
Martin Sperl3b15afe2016-02-29 12:51:42 +00001933 /*
1934 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1935 * in the SDRAM controller can't be used.
1936 */
1937 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
1938 .name = "sdram",
1939 .ctl_reg = CM_SDCCTL,
1940 .div_reg = CM_SDCDIV,
1941 .int_bits = 6,
Eric Anholt3f919582017-01-18 07:31:57 +11001942 .frac_bits = 0,
1943 .tcnt_mux = 3),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001944 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
1945 .name = "v3d",
1946 .ctl_reg = CM_V3DCTL,
1947 .div_reg = CM_V3DDIV,
1948 .int_bits = 4,
Eric Anholt3f919582017-01-18 07:31:57 +11001949 .frac_bits = 8,
1950 .tcnt_mux = 4),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001951 /*
1952 * VPU clock. This doesn't have an enable bit, since it drives
1953 * the bus for everything else, and is special so it doesn't need
1954 * to be gated for rate changes. It is also known as "clk_audio"
1955 * in various hardware documentation.
1956 */
1957 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
1958 .name = "vpu",
1959 .ctl_reg = CM_VPUCTL,
1960 .div_reg = CM_VPUDIV,
1961 .int_bits = 12,
1962 .frac_bits = 8,
Eric Anholte69fdcc2016-06-01 12:05:33 -07001963 .flags = CLK_IS_CRITICAL,
Eric Anholt3f919582017-01-18 07:31:57 +11001964 .is_vpu_clock = true,
1965 .tcnt_mux = 5),
Martin Sperl3b15afe2016-02-29 12:51:42 +00001966
1967 /* clocks with per parent mux */
Martin Sperld3d6f152016-02-29 15:43:57 +00001968 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
1969 .name = "aveo",
1970 .ctl_reg = CM_AVEOCTL,
1971 .div_reg = CM_AVEODIV,
1972 .int_bits = 4,
Eric Anholt3f919582017-01-18 07:31:57 +11001973 .frac_bits = 0,
1974 .tcnt_mux = 38),
Martin Sperld3d6f152016-02-29 15:43:57 +00001975 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
1976 .name = "cam0",
1977 .ctl_reg = CM_CAM0CTL,
1978 .div_reg = CM_CAM0DIV,
1979 .int_bits = 4,
Eric Anholt3f919582017-01-18 07:31:57 +11001980 .frac_bits = 8,
1981 .tcnt_mux = 14),
Martin Sperld3d6f152016-02-29 15:43:57 +00001982 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
1983 .name = "cam1",
1984 .ctl_reg = CM_CAM1CTL,
1985 .div_reg = CM_CAM1DIV,
1986 .int_bits = 4,
Eric Anholt3f919582017-01-18 07:31:57 +11001987 .frac_bits = 8,
1988 .tcnt_mux = 15),
Martin Sperld3d6f152016-02-29 15:43:57 +00001989 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
1990 .name = "dft",
1991 .ctl_reg = CM_DFTCTL,
1992 .div_reg = CM_DFTDIV,
1993 .int_bits = 5,
1994 .frac_bits = 0),
1995 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
1996 .name = "dpi",
1997 .ctl_reg = CM_DPICTL,
1998 .div_reg = CM_DPIDIV,
1999 .int_bits = 4,
Eric Anholt3f919582017-01-18 07:31:57 +11002000 .frac_bits = 8,
2001 .tcnt_mux = 17),
Martin Sperl3b15afe2016-02-29 12:51:42 +00002002
2003 /* Arasan EMMC clock */
2004 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
2005 .name = "emmc",
2006 .ctl_reg = CM_EMMCCTL,
2007 .div_reg = CM_EMMCDIV,
2008 .int_bits = 4,
Eric Anholt3f919582017-01-18 07:31:57 +11002009 .frac_bits = 8,
2010 .tcnt_mux = 39),
Martin Sperld3d6f152016-02-29 15:43:57 +00002011
2012 /* General purpose (GPIO) clocks */
2013 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
2014 .name = "gp0",
2015 .ctl_reg = CM_GP0CTL,
2016 .div_reg = CM_GP0DIV,
2017 .int_bits = 12,
2018 .frac_bits = 12,
Eric Anholt3f919582017-01-18 07:31:57 +11002019 .is_mash_clock = true,
2020 .tcnt_mux = 20),
Martin Sperld3d6f152016-02-29 15:43:57 +00002021 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
2022 .name = "gp1",
2023 .ctl_reg = CM_GP1CTL,
2024 .div_reg = CM_GP1DIV,
2025 .int_bits = 12,
2026 .frac_bits = 12,
Eric Anholteddcbe832016-06-01 12:05:34 -07002027 .flags = CLK_IS_CRITICAL,
Eric Anholt3f919582017-01-18 07:31:57 +11002028 .is_mash_clock = true,
2029 .tcnt_mux = 21),
Martin Sperld3d6f152016-02-29 15:43:57 +00002030 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
2031 .name = "gp2",
2032 .ctl_reg = CM_GP2CTL,
2033 .div_reg = CM_GP2DIV,
2034 .int_bits = 12,
Eric Anholteddcbe832016-06-01 12:05:34 -07002035 .frac_bits = 12,
2036 .flags = CLK_IS_CRITICAL),
Martin Sperld3d6f152016-02-29 15:43:57 +00002037
Martin Sperl3b15afe2016-02-29 12:51:42 +00002038 /* HDMI state machine */
2039 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
2040 .name = "hsm",
2041 .ctl_reg = CM_HSMCTL,
2042 .div_reg = CM_HSMDIV,
2043 .int_bits = 4,
Eric Anholt3f919582017-01-18 07:31:57 +11002044 .frac_bits = 8,
2045 .tcnt_mux = 22),
Phil Elwell8c0de582017-06-01 15:14:16 +01002046 [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK(
Martin Sperl33b68962016-02-29 12:51:43 +00002047 .name = "pcm",
2048 .ctl_reg = CM_PCMCTL,
2049 .div_reg = CM_PCMDIV,
2050 .int_bits = 12,
2051 .frac_bits = 12,
Eric Anholt3f919582017-01-18 07:31:57 +11002052 .is_mash_clock = true,
Phil Elwell35429762017-06-01 15:14:22 +01002053 .low_jitter = true,
Eric Anholt3f919582017-01-18 07:31:57 +11002054 .tcnt_mux = 23),
Martin Sperl3b15afe2016-02-29 12:51:42 +00002055 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
2056 .name = "pwm",
2057 .ctl_reg = CM_PWMCTL,
2058 .div_reg = CM_PWMDIV,
2059 .int_bits = 12,
2060 .frac_bits = 12,
Eric Anholt3f919582017-01-18 07:31:57 +11002061 .is_mash_clock = true,
2062 .tcnt_mux = 24),
Martin Sperld3d6f152016-02-29 15:43:57 +00002063 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
2064 .name = "slim",
2065 .ctl_reg = CM_SLIMCTL,
2066 .div_reg = CM_SLIMDIV,
2067 .int_bits = 12,
2068 .frac_bits = 12,
Eric Anholt3f919582017-01-18 07:31:57 +11002069 .is_mash_clock = true,
2070 .tcnt_mux = 25),
Martin Sperld3d6f152016-02-29 15:43:57 +00002071 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
2072 .name = "smi",
2073 .ctl_reg = CM_SMICTL,
2074 .div_reg = CM_SMIDIV,
2075 .int_bits = 4,
Eric Anholt3f919582017-01-18 07:31:57 +11002076 .frac_bits = 8,
2077 .tcnt_mux = 27),
Martin Sperl3b15afe2016-02-29 12:51:42 +00002078 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
2079 .name = "uart",
2080 .ctl_reg = CM_UARTCTL,
2081 .div_reg = CM_UARTDIV,
2082 .int_bits = 10,
Eric Anholt3f919582017-01-18 07:31:57 +11002083 .frac_bits = 12,
2084 .tcnt_mux = 28),
Martin Sperld3d6f152016-02-29 15:43:57 +00002085
Martin Sperl3b15afe2016-02-29 12:51:42 +00002086 /* TV encoder clock. Only operating frequency is 108Mhz. */
2087 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
2088 .name = "vec",
2089 .ctl_reg = CM_VECCTL,
2090 .div_reg = CM_VECDIV,
2091 .int_bits = 4,
Boris Brezillond86d46a2016-12-01 22:00:20 +01002092 .frac_bits = 0,
2093 /*
2094 * Allow rate change propagation only on PLLH_AUX which is
2095 * assigned index 7 in the parent array.
2096 */
Eric Anholt3f919582017-01-18 07:31:57 +11002097 .set_rate_parent = BIT(7),
2098 .tcnt_mux = 29),
Martin Sperl3b15afe2016-02-29 12:51:42 +00002099
Martin Sperld3d6f152016-02-29 15:43:57 +00002100 /* dsi clocks */
2101 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
2102 .name = "dsi0e",
2103 .ctl_reg = CM_DSI0ECTL,
2104 .div_reg = CM_DSI0EDIV,
2105 .int_bits = 4,
Eric Anholt3f919582017-01-18 07:31:57 +11002106 .frac_bits = 8,
2107 .tcnt_mux = 18),
Martin Sperld3d6f152016-02-29 15:43:57 +00002108 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
2109 .name = "dsi1e",
2110 .ctl_reg = CM_DSI1ECTL,
2111 .div_reg = CM_DSI1EDIV,
2112 .int_bits = 4,
Eric Anholt3f919582017-01-18 07:31:57 +11002113 .frac_bits = 8,
2114 .tcnt_mux = 19),
Eric Anholt8a39e9f2017-01-18 07:31:56 +11002115 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
2116 .name = "dsi0p",
2117 .ctl_reg = CM_DSI0PCTL,
2118 .div_reg = CM_DSI0PDIV,
2119 .int_bits = 0,
Eric Anholt3f919582017-01-18 07:31:57 +11002120 .frac_bits = 0,
2121 .tcnt_mux = 12),
Eric Anholt8a39e9f2017-01-18 07:31:56 +11002122 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
2123 .name = "dsi1p",
2124 .ctl_reg = CM_DSI1PCTL,
2125 .div_reg = CM_DSI1PDIV,
2126 .int_bits = 0,
Eric Anholt3f919582017-01-18 07:31:57 +11002127 .frac_bits = 0,
2128 .tcnt_mux = 13),
Martin Sperld3d6f152016-02-29 15:43:57 +00002129
Martin Sperl56eb3a22016-02-29 12:51:41 +00002130 /* the gates */
Martin Sperl3b15afe2016-02-29 12:51:42 +00002131
2132 /*
2133 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
2134 * you have the debug bit set in the power manager, which we
2135 * don't bother exposing) are individual gates off of the
2136 * non-stop vpu clock.
2137 */
Martin Sperl56eb3a22016-02-29 12:51:41 +00002138 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
Martin Sperl3b15afe2016-02-29 12:51:42 +00002139 .name = "peri_image",
2140 .parent = "vpu",
2141 .ctl_reg = CM_PERIICTL),
Martin Sperl56eb3a22016-02-29 12:51:41 +00002142};
2143
Eric Anholt9e400c52016-06-01 12:05:35 -07002144/*
2145 * Permanently take a reference on the parent of the SDRAM clock.
2146 *
2147 * While the SDRAM is being driven by its dedicated PLL most of the
2148 * time, there is a little loop running in the firmware that
2149 * periodically switches the SDRAM to using our CM clock to do PVT
2150 * recalibration, with the assumption that the previously configured
2151 * SDRAM parent is still enabled and running.
2152 */
2153static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)
2154{
2155 struct clk *parent = clk_get_parent(sdc);
2156
2157 if (IS_ERR(parent))
2158 return PTR_ERR(parent);
2159
2160 return clk_prepare_enable(parent);
2161}
2162
Eric Anholt41691b82015-10-08 18:37:24 -07002163static int bcm2835_clk_probe(struct platform_device *pdev)
2164{
2165 struct device *dev = &pdev->dev;
Stephen Boydb19f0092016-06-01 16:15:03 -07002166 struct clk_hw **hws;
Eric Anholt41691b82015-10-08 18:37:24 -07002167 struct bcm2835_cprman *cprman;
2168 struct resource *res;
Martin Sperl56eb3a22016-02-29 12:51:41 +00002169 const struct bcm2835_clk_desc *desc;
2170 const size_t asize = ARRAY_SIZE(clk_desc_array);
2171 size_t i;
Eric Anholt9e400c52016-06-01 12:05:35 -07002172 int ret;
Eric Anholt41691b82015-10-08 18:37:24 -07002173
Stephen Boydb19f0092016-06-01 16:15:03 -07002174 cprman = devm_kzalloc(dev, sizeof(*cprman) +
2175 sizeof(*cprman->onecell.hws) * asize,
Martin Sperl56eb3a22016-02-29 12:51:41 +00002176 GFP_KERNEL);
Eric Anholt41691b82015-10-08 18:37:24 -07002177 if (!cprman)
2178 return -ENOMEM;
2179
2180 spin_lock_init(&cprman->regs_lock);
2181 cprman->dev = dev;
2182 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2183 cprman->regs = devm_ioremap_resource(dev, res);
2184 if (IS_ERR(cprman->regs))
2185 return PTR_ERR(cprman->regs);
2186
Eric Anholt8a39e9f2017-01-18 07:31:56 +11002187 memcpy(cprman->real_parent_names, cprman_parent_names,
2188 sizeof(cprman_parent_names));
2189 of_clk_parent_fill(dev->of_node, cprman->real_parent_names,
2190 ARRAY_SIZE(cprman_parent_names));
2191
2192 /*
2193 * Make sure the external oscillator has been registered.
2194 *
2195 * The other (DSI) clocks are not present on older device
2196 * trees, which we still need to support for backwards
2197 * compatibility.
2198 */
2199 if (!cprman->real_parent_names[0])
Eric Anholt41691b82015-10-08 18:37:24 -07002200 return -ENODEV;
2201
2202 platform_set_drvdata(pdev, cprman);
2203
Stephen Boydb19f0092016-06-01 16:15:03 -07002204 cprman->onecell.num = asize;
2205 hws = cprman->onecell.hws;
Eric Anholt41691b82015-10-08 18:37:24 -07002206
Martin Sperl56eb3a22016-02-29 12:51:41 +00002207 for (i = 0; i < asize; i++) {
2208 desc = &clk_desc_array[i];
2209 if (desc->clk_register && desc->data)
Stephen Boydb19f0092016-06-01 16:15:03 -07002210 hws[i] = desc->clk_register(cprman, desc->data);
Martin Sperl56eb3a22016-02-29 12:51:41 +00002211 }
Remi Pommarelcfbab8f2015-12-06 17:22:48 +01002212
Stephen Boydb19f0092016-06-01 16:15:03 -07002213 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
Eric Anholt9e400c52016-06-01 12:05:35 -07002214 if (ret)
2215 return ret;
2216
Stephen Boydb19f0092016-06-01 16:15:03 -07002217 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
2218 &cprman->onecell);
Eric Anholt41691b82015-10-08 18:37:24 -07002219}
2220
2221static const struct of_device_id bcm2835_clk_of_match[] = {
2222 { .compatible = "brcm,bcm2835-cprman", },
2223 {}
2224};
2225MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
2226
2227static struct platform_driver bcm2835_clk_driver = {
2228 .driver = {
2229 .name = "bcm2835-clk",
2230 .of_match_table = bcm2835_clk_of_match,
2231 },
2232 .probe = bcm2835_clk_probe,
2233};
2234
2235builtin_platform_driver(bcm2835_clk_driver);
2236
2237MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
2238MODULE_DESCRIPTION("BCM2835 clock driver");
2239MODULE_LICENSE("GPL v2");