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gerrit-public.fairphone.software / kernel / msm-5.4 / 358965d7bab9c70c11b64931da02667b161cb03a / . / arch / arm / mach-omap2 / clock34xx_data.c
blob: 60c6140b86afef7c1fc9d68aaaa04581a72e1c15 [file] [log] [blame]
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1/*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2009 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13/*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
17 */
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/clk.h>
22
23#include <plat/control.h>
24#include <plat/clkdev_omap.h>
25
26#include "clock.h"
27#include "clock34xx.h"
28#include "cm.h"
29#include "cm-regbits-34xx.h"
30#include "prm.h"
31#include "prm-regbits-34xx.h"
32
33/*
34 * clocks
35 */
36
37#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
38
39/* Maximum DPLL multiplier, divider values for OMAP3 */
40#define OMAP3_MAX_DPLL_MULT 2048
Richard Woodruff358965d2010-02-22 22:09:08 -0700[diff] [blame^]41#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]42#define OMAP3_MAX_DPLL_DIV 128
43
44/*
45 * DPLL1 supplies clock to the MPU.
46 * DPLL2 supplies clock to the IVA2.
47 * DPLL3 supplies CORE domain clocks.
48 * DPLL4 supplies peripheral clocks.
49 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
50 */
51
52/* Forward declarations for DPLL bypass clocks */
53static struct clk dpll1_fck;
54static struct clk dpll2_fck;
55
56/* PRM CLOCKS */
57
58/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
59static struct clk omap_32k_fck = {
60 .name = "omap_32k_fck",
61 .ops = &clkops_null,
62 .rate = 32768,
63 .flags = RATE_FIXED,
64};
65
66static struct clk secure_32k_fck = {
67 .name = "secure_32k_fck",
68 .ops = &clkops_null,
69 .rate = 32768,
70 .flags = RATE_FIXED,
71};
72
73/* Virtual source clocks for osc_sys_ck */
74static struct clk virt_12m_ck = {
75 .name = "virt_12m_ck",
76 .ops = &clkops_null,
77 .rate = 12000000,
78 .flags = RATE_FIXED,
79};
80
81static struct clk virt_13m_ck = {
82 .name = "virt_13m_ck",
83 .ops = &clkops_null,
84 .rate = 13000000,
85 .flags = RATE_FIXED,
86};
87
88static struct clk virt_16_8m_ck = {
89 .name = "virt_16_8m_ck",
90 .ops = &clkops_null,
91 .rate = 16800000,
92 .flags = RATE_FIXED,
93};
94
95static struct clk virt_19_2m_ck = {
96 .name = "virt_19_2m_ck",
97 .ops = &clkops_null,
98 .rate = 19200000,
99 .flags = RATE_FIXED,
100};
101
102static struct clk virt_26m_ck = {
103 .name = "virt_26m_ck",
104 .ops = &clkops_null,
105 .rate = 26000000,
106 .flags = RATE_FIXED,
107};
108
109static struct clk virt_38_4m_ck = {
110 .name = "virt_38_4m_ck",
111 .ops = &clkops_null,
112 .rate = 38400000,
113 .flags = RATE_FIXED,
114};
115
116static const struct clksel_rate osc_sys_12m_rates[] = {
117 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
118 { .div = 0 }
119};
120
121static const struct clksel_rate osc_sys_13m_rates[] = {
122 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
123 { .div = 0 }
124};
125
126static const struct clksel_rate osc_sys_16_8m_rates[] = {
127 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
128 { .div = 0 }
129};
130
131static const struct clksel_rate osc_sys_19_2m_rates[] = {
132 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
133 { .div = 0 }
134};
135
136static const struct clksel_rate osc_sys_26m_rates[] = {
137 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
138 { .div = 0 }
139};
140
141static const struct clksel_rate osc_sys_38_4m_rates[] = {
142 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
143 { .div = 0 }
144};
145
146static const struct clksel osc_sys_clksel[] = {
147 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
148 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
149 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
150 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
151 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
152 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
153 { .parent = NULL },
154};
155
156/* Oscillator clock */
157/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
158static struct clk osc_sys_ck = {
159 .name = "osc_sys_ck",
160 .ops = &clkops_null,
161 .init = &omap2_init_clksel_parent,
162 .clksel_reg = OMAP3430_PRM_CLKSEL,
163 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
164 .clksel = osc_sys_clksel,
165 /* REVISIT: deal with autoextclkmode? */
166 .flags = RATE_FIXED,
167 .recalc = &omap2_clksel_recalc,
168};
169
170static const struct clksel_rate div2_rates[] = {
171 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
172 { .div = 2, .val = 2, .flags = RATE_IN_343X },
173 { .div = 0 }
174};
175
176static const struct clksel sys_clksel[] = {
177 { .parent = &osc_sys_ck, .rates = div2_rates },
178 { .parent = NULL }
179};
180
181/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
182/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
183static struct clk sys_ck = {
184 .name = "sys_ck",
185 .ops = &clkops_null,
186 .parent = &osc_sys_ck,
187 .init = &omap2_init_clksel_parent,
188 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
189 .clksel_mask = OMAP_SYSCLKDIV_MASK,
190 .clksel = sys_clksel,
191 .recalc = &omap2_clksel_recalc,
192};
193
194static struct clk sys_altclk = {
195 .name = "sys_altclk",
196 .ops = &clkops_null,
197};
198
199/* Optional external clock input for some McBSPs */
200static struct clk mcbsp_clks = {
201 .name = "mcbsp_clks",
202 .ops = &clkops_null,
203};
204
205/* PRM EXTERNAL CLOCK OUTPUT */
206
207static struct clk sys_clkout1 = {
208 .name = "sys_clkout1",
209 .ops = &clkops_omap2_dflt,
210 .parent = &osc_sys_ck,
211 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
212 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
213 .recalc = &followparent_recalc,
214};
215
216/* DPLLS */
217
218/* CM CLOCKS */
219
220static const struct clksel_rate div16_dpll_rates[] = {
221 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
222 { .div = 2, .val = 2, .flags = RATE_IN_343X },
223 { .div = 3, .val = 3, .flags = RATE_IN_343X },
224 { .div = 4, .val = 4, .flags = RATE_IN_343X },
225 { .div = 5, .val = 5, .flags = RATE_IN_343X },
226 { .div = 6, .val = 6, .flags = RATE_IN_343X },
227 { .div = 7, .val = 7, .flags = RATE_IN_343X },
228 { .div = 8, .val = 8, .flags = RATE_IN_343X },
229 { .div = 9, .val = 9, .flags = RATE_IN_343X },
230 { .div = 10, .val = 10, .flags = RATE_IN_343X },
231 { .div = 11, .val = 11, .flags = RATE_IN_343X },
232 { .div = 12, .val = 12, .flags = RATE_IN_343X },
233 { .div = 13, .val = 13, .flags = RATE_IN_343X },
234 { .div = 14, .val = 14, .flags = RATE_IN_343X },
235 { .div = 15, .val = 15, .flags = RATE_IN_343X },
236 { .div = 16, .val = 16, .flags = RATE_IN_343X },
237 { .div = 0 }
238};
239
240/* DPLL1 */
241/* MPU clock source */
242/* Type: DPLL */
243static struct dpll_data dpll1_dd = {
244 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
245 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
246 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
247 .clk_bypass = &dpll1_fck,
248 .clk_ref = &sys_ck,
249 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
250 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
251 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
252 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
253 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
254 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
255 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
256 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
257 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
258 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
259 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
260 .max_multiplier = OMAP3_MAX_DPLL_MULT,
261 .min_divider = 1,
262 .max_divider = OMAP3_MAX_DPLL_DIV,
263 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
264};
265
266static struct clk dpll1_ck = {
267 .name = "dpll1_ck",
268 .ops = &clkops_null,
269 .parent = &sys_ck,
270 .dpll_data = &dpll1_dd,
271 .round_rate = &omap2_dpll_round_rate,
272 .set_rate = &omap3_noncore_dpll_set_rate,
273 .clkdm_name = "dpll1_clkdm",
274 .recalc = &omap3_dpll_recalc,
275};
276
277/*
278 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
279 * DPLL isn't bypassed.
280 */
281static struct clk dpll1_x2_ck = {
282 .name = "dpll1_x2_ck",
283 .ops = &clkops_null,
284 .parent = &dpll1_ck,
285 .clkdm_name = "dpll1_clkdm",
286 .recalc = &omap3_clkoutx2_recalc,
287};
288
289/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
290static const struct clksel div16_dpll1_x2m2_clksel[] = {
291 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
292 { .parent = NULL }
293};
294
295/*
296 * Does not exist in the TRM - needed to separate the M2 divider from
297 * bypass selection in mpu_ck
298 */
299static struct clk dpll1_x2m2_ck = {
300 .name = "dpll1_x2m2_ck",
301 .ops = &clkops_null,
302 .parent = &dpll1_x2_ck,
303 .init = &omap2_init_clksel_parent,
304 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
305 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
306 .clksel = div16_dpll1_x2m2_clksel,
307 .clkdm_name = "dpll1_clkdm",
308 .recalc = &omap2_clksel_recalc,
309};
310
311/* DPLL2 */
312/* IVA2 clock source */
313/* Type: DPLL */
314
315static struct dpll_data dpll2_dd = {
316 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
317 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
318 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
319 .clk_bypass = &dpll2_fck,
320 .clk_ref = &sys_ck,
321 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
322 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
323 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
324 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
325 (1 << DPLL_LOW_POWER_BYPASS),
326 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
327 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
328 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
329 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
330 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
331 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
332 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
333 .max_multiplier = OMAP3_MAX_DPLL_MULT,
334 .min_divider = 1,
335 .max_divider = OMAP3_MAX_DPLL_DIV,
336 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
337};
338
339static struct clk dpll2_ck = {
340 .name = "dpll2_ck",
Tony Lindgren47512272010-02-15 09:27:25 -0800[diff] [blame]341 .ops = &omap3_clkops_noncore_dpll_ops,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]342 .parent = &sys_ck,
343 .dpll_data = &dpll2_dd,
344 .round_rate = &omap2_dpll_round_rate,
345 .set_rate = &omap3_noncore_dpll_set_rate,
346 .clkdm_name = "dpll2_clkdm",
347 .recalc = &omap3_dpll_recalc,
348};
349
350static const struct clksel div16_dpll2_m2x2_clksel[] = {
351 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
352 { .parent = NULL }
353};
354
355/*
356 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
357 * or CLKOUTX2. CLKOUT seems most plausible.
358 */
359static struct clk dpll2_m2_ck = {
360 .name = "dpll2_m2_ck",
361 .ops = &clkops_null,
362 .parent = &dpll2_ck,
363 .init = &omap2_init_clksel_parent,
364 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
365 OMAP3430_CM_CLKSEL2_PLL),
366 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
367 .clksel = div16_dpll2_m2x2_clksel,
368 .clkdm_name = "dpll2_clkdm",
369 .recalc = &omap2_clksel_recalc,
370};
371
372/*
373 * DPLL3
374 * Source clock for all interfaces and for some device fclks
375 * REVISIT: Also supports fast relock bypass - not included below
376 */
377static struct dpll_data dpll3_dd = {
378 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
379 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
380 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
381 .clk_bypass = &sys_ck,
382 .clk_ref = &sys_ck,
383 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
384 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
385 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
386 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
387 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
388 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
389 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
390 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
391 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
392 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
393 .max_multiplier = OMAP3_MAX_DPLL_MULT,
394 .min_divider = 1,
395 .max_divider = OMAP3_MAX_DPLL_DIV,
396 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
397};
398
399static struct clk dpll3_ck = {
400 .name = "dpll3_ck",
401 .ops = &clkops_null,
402 .parent = &sys_ck,
403 .dpll_data = &dpll3_dd,
404 .round_rate = &omap2_dpll_round_rate,
405 .clkdm_name = "dpll3_clkdm",
406 .recalc = &omap3_dpll_recalc,
407};
408
409/*
410 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
411 * DPLL isn't bypassed
412 */
413static struct clk dpll3_x2_ck = {
414 .name = "dpll3_x2_ck",
415 .ops = &clkops_null,
416 .parent = &dpll3_ck,
417 .clkdm_name = "dpll3_clkdm",
418 .recalc = &omap3_clkoutx2_recalc,
419};
420
421static const struct clksel_rate div31_dpll3_rates[] = {
422 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
423 { .div = 2, .val = 2, .flags = RATE_IN_343X },
424 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
425 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
426 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
427 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
428 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
429 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
430 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
431 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
432 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
433 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
434 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
435 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
436 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
437 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
438 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
439 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
440 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
441 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
442 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
443 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
444 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
445 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
446 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
447 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
448 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
449 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
450 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
451 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
452 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
453 { .div = 0 },
454};
455
456static const struct clksel div31_dpll3m2_clksel[] = {
457 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
458 { .parent = NULL }
459};
460
461/* DPLL3 output M2 - primary control point for CORE speed */
462static struct clk dpll3_m2_ck = {
463 .name = "dpll3_m2_ck",
464 .ops = &clkops_null,
465 .parent = &dpll3_ck,
466 .init = &omap2_init_clksel_parent,
467 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
468 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
469 .clksel = div31_dpll3m2_clksel,
470 .clkdm_name = "dpll3_clkdm",
471 .round_rate = &omap2_clksel_round_rate,
472 .set_rate = &omap3_core_dpll_m2_set_rate,
473 .recalc = &omap2_clksel_recalc,
474};
475
476static struct clk core_ck = {
477 .name = "core_ck",
478 .ops = &clkops_null,
479 .parent = &dpll3_m2_ck,
480 .recalc = &followparent_recalc,
481};
482
483static struct clk dpll3_m2x2_ck = {
484 .name = "dpll3_m2x2_ck",
485 .ops = &clkops_null,
486 .parent = &dpll3_m2_ck,
487 .clkdm_name = "dpll3_clkdm",
488 .recalc = &omap3_clkoutx2_recalc,
489};
490
491/* The PWRDN bit is apparently only available on 3430ES2 and above */
492static const struct clksel div16_dpll3_clksel[] = {
493 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
494 { .parent = NULL }
495};
496
497/* This virtual clock is the source for dpll3_m3x2_ck */
498static struct clk dpll3_m3_ck = {
499 .name = "dpll3_m3_ck",
500 .ops = &clkops_null,
501 .parent = &dpll3_ck,
502 .init = &omap2_init_clksel_parent,
503 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
504 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
505 .clksel = div16_dpll3_clksel,
506 .clkdm_name = "dpll3_clkdm",
507 .recalc = &omap2_clksel_recalc,
508};
509
510/* The PWRDN bit is apparently only available on 3430ES2 and above */
511static struct clk dpll3_m3x2_ck = {
512 .name = "dpll3_m3x2_ck",
513 .ops = &clkops_omap2_dflt_wait,
514 .parent = &dpll3_m3_ck,
515 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
516 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
517 .flags = INVERT_ENABLE,
518 .clkdm_name = "dpll3_clkdm",
519 .recalc = &omap3_clkoutx2_recalc,
520};
521
522static struct clk emu_core_alwon_ck = {
523 .name = "emu_core_alwon_ck",
524 .ops = &clkops_null,
525 .parent = &dpll3_m3x2_ck,
526 .clkdm_name = "dpll3_clkdm",
527 .recalc = &followparent_recalc,
528};
529
530/* DPLL4 */
531/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
532/* Type: DPLL */
Richard Woodruff358965d2010-02-22 22:09:08 -0700[diff] [blame^]533static struct dpll_data dpll4_dd;
534static struct dpll_data dpll4_dd_34xx __initdata = {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]535 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
536 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
537 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
538 .clk_bypass = &sys_ck,
539 .clk_ref = &sys_ck,
540 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
541 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
542 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
543 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
544 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
545 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
546 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
547 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
548 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
549 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
550 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
551 .max_multiplier = OMAP3_MAX_DPLL_MULT,
552 .min_divider = 1,
553 .max_divider = OMAP3_MAX_DPLL_DIV,
554 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
555};
556
Richard Woodruff358965d2010-02-22 22:09:08 -0700[diff] [blame^]557static struct dpll_data dpll4_dd_3630 __initdata = {
558 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
559 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
560 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
561 .clk_bypass = &sys_ck,
562 .clk_ref = &sys_ck,
563 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
564 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
565 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
566 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
567 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
568 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
569 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
570 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
571 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
572 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
573 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
574 .min_divider = 1,
575 .max_divider = OMAP3_MAX_DPLL_DIV,
576 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
577 .flags = DPLL_J_TYPE
578};
579
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]580static struct clk dpll4_ck = {
581 .name = "dpll4_ck",
Tony Lindgren47512272010-02-15 09:27:25 -0800[diff] [blame]582 .ops = &omap3_clkops_noncore_dpll_ops,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]583 .parent = &sys_ck,
584 .dpll_data = &dpll4_dd,
585 .round_rate = &omap2_dpll_round_rate,
586 .set_rate = &omap3_dpll4_set_rate,
587 .clkdm_name = "dpll4_clkdm",
588 .recalc = &omap3_dpll_recalc,
589};
590
591/*
592 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
593 * DPLL isn't bypassed --
594 * XXX does this serve any downstream clocks?
595 */
596static struct clk dpll4_x2_ck = {
597 .name = "dpll4_x2_ck",
598 .ops = &clkops_null,
599 .parent = &dpll4_ck,
600 .clkdm_name = "dpll4_clkdm",
601 .recalc = &omap3_clkoutx2_recalc,
602};
603
604static const struct clksel div16_dpll4_clksel[] = {
605 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
606 { .parent = NULL }
607};
608
609/* This virtual clock is the source for dpll4_m2x2_ck */
610static struct clk dpll4_m2_ck = {
611 .name = "dpll4_m2_ck",
612 .ops = &clkops_null,
613 .parent = &dpll4_ck,
614 .init = &omap2_init_clksel_parent,
615 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
616 .clksel_mask = OMAP3430_DIV_96M_MASK,
617 .clksel = div16_dpll4_clksel,
618 .clkdm_name = "dpll4_clkdm",
619 .recalc = &omap2_clksel_recalc,
620};
621
622/* The PWRDN bit is apparently only available on 3430ES2 and above */
623static struct clk dpll4_m2x2_ck = {
624 .name = "dpll4_m2x2_ck",
625 .ops = &clkops_omap2_dflt_wait,
626 .parent = &dpll4_m2_ck,
627 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
628 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
629 .flags = INVERT_ENABLE,
630 .clkdm_name = "dpll4_clkdm",
631 .recalc = &omap3_clkoutx2_recalc,
632};
633
634/*
635 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
636 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
637 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
638 * CM_96K_(F)CLK.
639 */
640static struct clk omap_96m_alwon_fck = {
641 .name = "omap_96m_alwon_fck",
642 .ops = &clkops_null,
643 .parent = &dpll4_m2x2_ck,
644 .recalc = &followparent_recalc,
645};
646
647static struct clk cm_96m_fck = {
648 .name = "cm_96m_fck",
649 .ops = &clkops_null,
650 .parent = &omap_96m_alwon_fck,
651 .recalc = &followparent_recalc,
652};
653
654static const struct clksel_rate omap_96m_dpll_rates[] = {
655 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
656 { .div = 0 }
657};
658
659static const struct clksel_rate omap_96m_sys_rates[] = {
660 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
661 { .div = 0 }
662};
663
664static const struct clksel omap_96m_fck_clksel[] = {
665 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
666 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
667 { .parent = NULL }
668};
669
670static struct clk omap_96m_fck = {
671 .name = "omap_96m_fck",
672 .ops = &clkops_null,
673 .parent = &sys_ck,
674 .init = &omap2_init_clksel_parent,
675 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
676 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
677 .clksel = omap_96m_fck_clksel,
678 .recalc = &omap2_clksel_recalc,
679};
680
681/* This virtual clock is the source for dpll4_m3x2_ck */
682static struct clk dpll4_m3_ck = {
683 .name = "dpll4_m3_ck",
684 .ops = &clkops_null,
685 .parent = &dpll4_ck,
686 .init = &omap2_init_clksel_parent,
687 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
688 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
689 .clksel = div16_dpll4_clksel,
690 .clkdm_name = "dpll4_clkdm",
691 .recalc = &omap2_clksel_recalc,
692};
693
694/* The PWRDN bit is apparently only available on 3430ES2 and above */
695static struct clk dpll4_m3x2_ck = {
696 .name = "dpll4_m3x2_ck",
697 .ops = &clkops_omap2_dflt_wait,
698 .parent = &dpll4_m3_ck,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]699 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
700 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
701 .flags = INVERT_ENABLE,
702 .clkdm_name = "dpll4_clkdm",
703 .recalc = &omap3_clkoutx2_recalc,
704};
705
706static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
707 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
708 { .div = 0 }
709};
710
711static const struct clksel_rate omap_54m_alt_rates[] = {
712 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
713 { .div = 0 }
714};
715
716static const struct clksel omap_54m_clksel[] = {
717 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
718 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
719 { .parent = NULL }
720};
721
722static struct clk omap_54m_fck = {
723 .name = "omap_54m_fck",
724 .ops = &clkops_null,
725 .init = &omap2_init_clksel_parent,
726 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
727 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
728 .clksel = omap_54m_clksel,
729 .recalc = &omap2_clksel_recalc,
730};
731
732static const struct clksel_rate omap_48m_cm96m_rates[] = {
733 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
734 { .div = 0 }
735};
736
737static const struct clksel_rate omap_48m_alt_rates[] = {
738 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
739 { .div = 0 }
740};
741
742static const struct clksel omap_48m_clksel[] = {
743 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
744 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
745 { .parent = NULL }
746};
747
748static struct clk omap_48m_fck = {
749 .name = "omap_48m_fck",
750 .ops = &clkops_null,
751 .init = &omap2_init_clksel_parent,
752 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
753 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
754 .clksel = omap_48m_clksel,
755 .recalc = &omap2_clksel_recalc,
756};
757
758static struct clk omap_12m_fck = {
759 .name = "omap_12m_fck",
760 .ops = &clkops_null,
761 .parent = &omap_48m_fck,
762 .fixed_div = 4,
Paul Walmsleye9b98f62010-01-26 20:12:57 -0700[diff] [blame]763 .recalc = &omap_fixed_divisor_recalc,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]764};
765
766/* This virstual clock is the source for dpll4_m4x2_ck */
767static struct clk dpll4_m4_ck = {
768 .name = "dpll4_m4_ck",
769 .ops = &clkops_null,
770 .parent = &dpll4_ck,
771 .init = &omap2_init_clksel_parent,
772 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
773 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
774 .clksel = div16_dpll4_clksel,
775 .clkdm_name = "dpll4_clkdm",
776 .recalc = &omap2_clksel_recalc,
777 .set_rate = &omap2_clksel_set_rate,
778 .round_rate = &omap2_clksel_round_rate,
779};
780
781/* The PWRDN bit is apparently only available on 3430ES2 and above */
782static struct clk dpll4_m4x2_ck = {
783 .name = "dpll4_m4x2_ck",
784 .ops = &clkops_omap2_dflt_wait,
785 .parent = &dpll4_m4_ck,
786 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
787 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
788 .flags = INVERT_ENABLE,
789 .clkdm_name = "dpll4_clkdm",
790 .recalc = &omap3_clkoutx2_recalc,
791};
792
793/* This virtual clock is the source for dpll4_m5x2_ck */
794static struct clk dpll4_m5_ck = {
795 .name = "dpll4_m5_ck",
796 .ops = &clkops_null,
797 .parent = &dpll4_ck,
798 .init = &omap2_init_clksel_parent,
799 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
800 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
801 .clksel = div16_dpll4_clksel,
802 .clkdm_name = "dpll4_clkdm",
Tuukka Toivonen3e3ee152010-01-08 15:23:08 -0700[diff] [blame]803 .set_rate = &omap2_clksel_set_rate,
804 .round_rate = &omap2_clksel_round_rate,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]805 .recalc = &omap2_clksel_recalc,
806};
807
808/* The PWRDN bit is apparently only available on 3430ES2 and above */
809static struct clk dpll4_m5x2_ck = {
810 .name = "dpll4_m5x2_ck",
811 .ops = &clkops_omap2_dflt_wait,
812 .parent = &dpll4_m5_ck,
813 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
814 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
815 .flags = INVERT_ENABLE,
816 .clkdm_name = "dpll4_clkdm",
817 .recalc = &omap3_clkoutx2_recalc,
818};
819
820/* This virtual clock is the source for dpll4_m6x2_ck */
821static struct clk dpll4_m6_ck = {
822 .name = "dpll4_m6_ck",
823 .ops = &clkops_null,
824 .parent = &dpll4_ck,
825 .init = &omap2_init_clksel_parent,
826 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
827 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
828 .clksel = div16_dpll4_clksel,
829 .clkdm_name = "dpll4_clkdm",
830 .recalc = &omap2_clksel_recalc,
831};
832
833/* The PWRDN bit is apparently only available on 3430ES2 and above */
834static struct clk dpll4_m6x2_ck = {
835 .name = "dpll4_m6x2_ck",
836 .ops = &clkops_omap2_dflt_wait,
837 .parent = &dpll4_m6_ck,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]838 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
839 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
840 .flags = INVERT_ENABLE,
841 .clkdm_name = "dpll4_clkdm",
842 .recalc = &omap3_clkoutx2_recalc,
843};
844
845static struct clk emu_per_alwon_ck = {
846 .name = "emu_per_alwon_ck",
847 .ops = &clkops_null,
848 .parent = &dpll4_m6x2_ck,
849 .clkdm_name = "dpll4_clkdm",
850 .recalc = &followparent_recalc,
851};
852
853/* DPLL5 */
854/* Supplies 120MHz clock, USIM source clock */
855/* Type: DPLL */
856/* 3430ES2 only */
857static struct dpll_data dpll5_dd = {
858 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
859 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
860 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
861 .clk_bypass = &sys_ck,
862 .clk_ref = &sys_ck,
863 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
864 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
865 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
866 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
867 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
868 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
869 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
870 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
871 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
872 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
873 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
874 .max_multiplier = OMAP3_MAX_DPLL_MULT,
875 .min_divider = 1,
876 .max_divider = OMAP3_MAX_DPLL_DIV,
877 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
878};
879
880static struct clk dpll5_ck = {
881 .name = "dpll5_ck",
Tony Lindgren47512272010-02-15 09:27:25 -0800[diff] [blame]882 .ops = &omap3_clkops_noncore_dpll_ops,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]883 .parent = &sys_ck,
884 .dpll_data = &dpll5_dd,
885 .round_rate = &omap2_dpll_round_rate,
886 .set_rate = &omap3_noncore_dpll_set_rate,
887 .clkdm_name = "dpll5_clkdm",
888 .recalc = &omap3_dpll_recalc,
889};
890
891static const struct clksel div16_dpll5_clksel[] = {
892 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
893 { .parent = NULL }
894};
895
896static struct clk dpll5_m2_ck = {
897 .name = "dpll5_m2_ck",
898 .ops = &clkops_null,
899 .parent = &dpll5_ck,
900 .init = &omap2_init_clksel_parent,
901 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
902 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
903 .clksel = div16_dpll5_clksel,
904 .clkdm_name = "dpll5_clkdm",
905 .recalc = &omap2_clksel_recalc,
906};
907
908/* CM EXTERNAL CLOCK OUTPUTS */
909
910static const struct clksel_rate clkout2_src_core_rates[] = {
911 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
912 { .div = 0 }
913};
914
915static const struct clksel_rate clkout2_src_sys_rates[] = {
916 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
917 { .div = 0 }
918};
919
920static const struct clksel_rate clkout2_src_96m_rates[] = {
921 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
922 { .div = 0 }
923};
924
925static const struct clksel_rate clkout2_src_54m_rates[] = {
926 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
927 { .div = 0 }
928};
929
930static const struct clksel clkout2_src_clksel[] = {
931 { .parent = &core_ck, .rates = clkout2_src_core_rates },
932 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
933 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
934 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
935 { .parent = NULL }
936};
937
938static struct clk clkout2_src_ck = {
939 .name = "clkout2_src_ck",
940 .ops = &clkops_omap2_dflt,
941 .init = &omap2_init_clksel_parent,
942 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
943 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
944 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
945 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
946 .clksel = clkout2_src_clksel,
947 .clkdm_name = "core_clkdm",
948 .recalc = &omap2_clksel_recalc,
949};
950
951static const struct clksel_rate sys_clkout2_rates[] = {
952 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
953 { .div = 2, .val = 1, .flags = RATE_IN_343X },
954 { .div = 4, .val = 2, .flags = RATE_IN_343X },
955 { .div = 8, .val = 3, .flags = RATE_IN_343X },
956 { .div = 16, .val = 4, .flags = RATE_IN_343X },
957 { .div = 0 },
958};
959
960static const struct clksel sys_clkout2_clksel[] = {
961 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
962 { .parent = NULL },
963};
964
965static struct clk sys_clkout2 = {
966 .name = "sys_clkout2",
967 .ops = &clkops_null,
968 .init = &omap2_init_clksel_parent,
969 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
970 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
971 .clksel = sys_clkout2_clksel,
972 .recalc = &omap2_clksel_recalc,
973};
974
975/* CM OUTPUT CLOCKS */
976
977static struct clk corex2_fck = {
978 .name = "corex2_fck",
979 .ops = &clkops_null,
980 .parent = &dpll3_m2x2_ck,
981 .recalc = &followparent_recalc,
982};
983
984/* DPLL power domain clock controls */
985
986static const struct clksel_rate div4_rates[] = {
987 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
988 { .div = 2, .val = 2, .flags = RATE_IN_343X },
989 { .div = 4, .val = 4, .flags = RATE_IN_343X },
990 { .div = 0 }
991};
992
993static const struct clksel div4_core_clksel[] = {
994 { .parent = &core_ck, .rates = div4_rates },
995 { .parent = NULL }
996};
997
998/*
999 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1000 * may be inconsistent here?
1001 */
1002static struct clk dpll1_fck = {
1003 .name = "dpll1_fck",
1004 .ops = &clkops_null,
1005 .parent = &core_ck,
1006 .init = &omap2_init_clksel_parent,
1007 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1008 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1009 .clksel = div4_core_clksel,
1010 .recalc = &omap2_clksel_recalc,
1011};
1012
1013static struct clk mpu_ck = {
1014 .name = "mpu_ck",
1015 .ops = &clkops_null,
1016 .parent = &dpll1_x2m2_ck,
1017 .clkdm_name = "mpu_clkdm",
1018 .recalc = &followparent_recalc,
1019};
1020
1021/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1022static const struct clksel_rate arm_fck_rates[] = {
1023 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1024 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1025 { .div = 0 },
1026};
1027
1028static const struct clksel arm_fck_clksel[] = {
1029 { .parent = &mpu_ck, .rates = arm_fck_rates },
1030 { .parent = NULL }
1031};
1032
1033static struct clk arm_fck = {
1034 .name = "arm_fck",
1035 .ops = &clkops_null,
1036 .parent = &mpu_ck,
1037 .init = &omap2_init_clksel_parent,
1038 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1039 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1040 .clksel = arm_fck_clksel,
1041 .clkdm_name = "mpu_clkdm",
1042 .recalc = &omap2_clksel_recalc,
1043};
1044
1045/* XXX What about neon_clkdm ? */
1046
1047/*
1048 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1049 * although it is referenced - so this is a guess
1050 */
1051static struct clk emu_mpu_alwon_ck = {
1052 .name = "emu_mpu_alwon_ck",
1053 .ops = &clkops_null,
1054 .parent = &mpu_ck,
1055 .recalc = &followparent_recalc,
1056};
1057
1058static struct clk dpll2_fck = {
1059 .name = "dpll2_fck",
1060 .ops = &clkops_null,
1061 .parent = &core_ck,
1062 .init = &omap2_init_clksel_parent,
1063 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1064 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1065 .clksel = div4_core_clksel,
1066 .recalc = &omap2_clksel_recalc,
1067};
1068
1069static struct clk iva2_ck = {
1070 .name = "iva2_ck",
1071 .ops = &clkops_omap2_dflt_wait,
1072 .parent = &dpll2_m2_ck,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1073 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1074 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1075 .clkdm_name = "iva2_clkdm",
1076 .recalc = &followparent_recalc,
1077};
1078
1079/* Common interface clocks */
1080
1081static const struct clksel div2_core_clksel[] = {
1082 { .parent = &core_ck, .rates = div2_rates },
1083 { .parent = NULL }
1084};
1085
1086static struct clk l3_ick = {
1087 .name = "l3_ick",
1088 .ops = &clkops_null,
1089 .parent = &core_ck,
1090 .init = &omap2_init_clksel_parent,
1091 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1092 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1093 .clksel = div2_core_clksel,
1094 .clkdm_name = "core_l3_clkdm",
1095 .recalc = &omap2_clksel_recalc,
1096};
1097
1098static const struct clksel div2_l3_clksel[] = {
1099 { .parent = &l3_ick, .rates = div2_rates },
1100 { .parent = NULL }
1101};
1102
1103static struct clk l4_ick = {
1104 .name = "l4_ick",
1105 .ops = &clkops_null,
1106 .parent = &l3_ick,
1107 .init = &omap2_init_clksel_parent,
1108 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1109 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1110 .clksel = div2_l3_clksel,
1111 .clkdm_name = "core_l4_clkdm",
1112 .recalc = &omap2_clksel_recalc,
1113
1114};
1115
1116static const struct clksel div2_l4_clksel[] = {
1117 { .parent = &l4_ick, .rates = div2_rates },
1118 { .parent = NULL }
1119};
1120
1121static struct clk rm_ick = {
1122 .name = "rm_ick",
1123 .ops = &clkops_null,
1124 .parent = &l4_ick,
1125 .init = &omap2_init_clksel_parent,
1126 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1127 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1128 .clksel = div2_l4_clksel,
1129 .recalc = &omap2_clksel_recalc,
1130};
1131
1132/* GFX power domain */
1133
1134/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1135
1136static const struct clksel gfx_l3_clksel[] = {
1137 { .parent = &l3_ick, .rates = gfx_l3_rates },
1138 { .parent = NULL }
1139};
1140
1141/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1142static struct clk gfx_l3_ck = {
1143 .name = "gfx_l3_ck",
1144 .ops = &clkops_omap2_dflt_wait,
1145 .parent = &l3_ick,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1146 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1147 .enable_bit = OMAP_EN_GFX_SHIFT,
1148 .recalc = &followparent_recalc,
1149};
1150
1151static struct clk gfx_l3_fck = {
1152 .name = "gfx_l3_fck",
1153 .ops = &clkops_null,
1154 .parent = &gfx_l3_ck,
1155 .init = &omap2_init_clksel_parent,
1156 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1157 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1158 .clksel = gfx_l3_clksel,
1159 .clkdm_name = "gfx_3430es1_clkdm",
1160 .recalc = &omap2_clksel_recalc,
1161};
1162
1163static struct clk gfx_l3_ick = {
1164 .name = "gfx_l3_ick",
1165 .ops = &clkops_null,
1166 .parent = &gfx_l3_ck,
1167 .clkdm_name = "gfx_3430es1_clkdm",
1168 .recalc = &followparent_recalc,
1169};
1170
1171static struct clk gfx_cg1_ck = {
1172 .name = "gfx_cg1_ck",
1173 .ops = &clkops_omap2_dflt_wait,
1174 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1175 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1176 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1177 .clkdm_name = "gfx_3430es1_clkdm",
1178 .recalc = &followparent_recalc,
1179};
1180
1181static struct clk gfx_cg2_ck = {
1182 .name = "gfx_cg2_ck",
1183 .ops = &clkops_omap2_dflt_wait,
1184 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1185 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1186 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1187 .clkdm_name = "gfx_3430es1_clkdm",
1188 .recalc = &followparent_recalc,
1189};
1190
1191/* SGX power domain - 3430ES2 only */
1192
1193static const struct clksel_rate sgx_core_rates[] = {
1194 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1195 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1196 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1197 { .div = 0 },
1198};
1199
1200static const struct clksel_rate sgx_96m_rates[] = {
1201 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1202 { .div = 0 },
1203};
1204
1205static const struct clksel sgx_clksel[] = {
1206 { .parent = &core_ck, .rates = sgx_core_rates },
1207 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1208 { .parent = NULL },
1209};
1210
1211static struct clk sgx_fck = {
1212 .name = "sgx_fck",
1213 .ops = &clkops_omap2_dflt_wait,
1214 .init = &omap2_init_clksel_parent,
1215 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1216 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1217 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1218 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1219 .clksel = sgx_clksel,
1220 .clkdm_name = "sgx_clkdm",
1221 .recalc = &omap2_clksel_recalc,
1222};
1223
1224static struct clk sgx_ick = {
1225 .name = "sgx_ick",
1226 .ops = &clkops_omap2_dflt_wait,
1227 .parent = &l3_ick,
1228 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1229 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1230 .clkdm_name = "sgx_clkdm",
1231 .recalc = &followparent_recalc,
1232};
1233
1234/* CORE power domain */
1235
1236static struct clk d2d_26m_fck = {
1237 .name = "d2d_26m_fck",
1238 .ops = &clkops_omap2_dflt_wait,
1239 .parent = &sys_ck,
1240 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1241 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1242 .clkdm_name = "d2d_clkdm",
1243 .recalc = &followparent_recalc,
1244};
1245
1246static struct clk modem_fck = {
1247 .name = "modem_fck",
1248 .ops = &clkops_omap2_dflt_wait,
1249 .parent = &sys_ck,
1250 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1251 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
1252 .clkdm_name = "d2d_clkdm",
1253 .recalc = &followparent_recalc,
1254};
1255
1256static struct clk sad2d_ick = {
1257 .name = "sad2d_ick",
1258 .ops = &clkops_omap2_dflt_wait,
1259 .parent = &l3_ick,
1260 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1261 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
1262 .clkdm_name = "d2d_clkdm",
1263 .recalc = &followparent_recalc,
1264};
1265
1266static struct clk mad2d_ick = {
1267 .name = "mad2d_ick",
1268 .ops = &clkops_omap2_dflt_wait,
1269 .parent = &l3_ick,
1270 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1271 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1272 .clkdm_name = "d2d_clkdm",
1273 .recalc = &followparent_recalc,
1274};
1275
1276static const struct clksel omap343x_gpt_clksel[] = {
1277 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1278 { .parent = &sys_ck, .rates = gpt_sys_rates },
1279 { .parent = NULL}
1280};
1281
1282static struct clk gpt10_fck = {
1283 .name = "gpt10_fck",
1284 .ops = &clkops_omap2_dflt_wait,
1285 .parent = &sys_ck,
1286 .init = &omap2_init_clksel_parent,
1287 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1288 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1289 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1290 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1291 .clksel = omap343x_gpt_clksel,
1292 .clkdm_name = "core_l4_clkdm",
1293 .recalc = &omap2_clksel_recalc,
1294};
1295
1296static struct clk gpt11_fck = {
1297 .name = "gpt11_fck",
1298 .ops = &clkops_omap2_dflt_wait,
1299 .parent = &sys_ck,
1300 .init = &omap2_init_clksel_parent,
1301 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1302 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1303 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1304 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1305 .clksel = omap343x_gpt_clksel,
1306 .clkdm_name = "core_l4_clkdm",
1307 .recalc = &omap2_clksel_recalc,
1308};
1309
1310static struct clk cpefuse_fck = {
1311 .name = "cpefuse_fck",
1312 .ops = &clkops_omap2_dflt,
1313 .parent = &sys_ck,
1314 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1315 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1316 .recalc = &followparent_recalc,
1317};
1318
1319static struct clk ts_fck = {
1320 .name = "ts_fck",
1321 .ops = &clkops_omap2_dflt,
1322 .parent = &omap_32k_fck,
1323 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1324 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1325 .recalc = &followparent_recalc,
1326};
1327
1328static struct clk usbtll_fck = {
1329 .name = "usbtll_fck",
1330 .ops = &clkops_omap2_dflt,
1331 .parent = &dpll5_m2_ck,
1332 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1333 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1334 .recalc = &followparent_recalc,
1335};
1336
1337/* CORE 96M FCLK-derived clocks */
1338
1339static struct clk core_96m_fck = {
1340 .name = "core_96m_fck",
1341 .ops = &clkops_null,
1342 .parent = &omap_96m_fck,
1343 .clkdm_name = "core_l4_clkdm",
1344 .recalc = &followparent_recalc,
1345};
1346
1347static struct clk mmchs3_fck = {
1348 .name = "mmchs_fck",
1349 .ops = &clkops_omap2_dflt_wait,
1350 .id = 2,
1351 .parent = &core_96m_fck,
1352 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1353 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1354 .clkdm_name = "core_l4_clkdm",
1355 .recalc = &followparent_recalc,
1356};
1357
1358static struct clk mmchs2_fck = {
1359 .name = "mmchs_fck",
1360 .ops = &clkops_omap2_dflt_wait,
1361 .id = 1,
1362 .parent = &core_96m_fck,
1363 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1364 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1365 .clkdm_name = "core_l4_clkdm",
1366 .recalc = &followparent_recalc,
1367};
1368
1369static struct clk mspro_fck = {
1370 .name = "mspro_fck",
1371 .ops = &clkops_omap2_dflt_wait,
1372 .parent = &core_96m_fck,
1373 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1374 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1375 .clkdm_name = "core_l4_clkdm",
1376 .recalc = &followparent_recalc,
1377};
1378
1379static struct clk mmchs1_fck = {
1380 .name = "mmchs_fck",
1381 .ops = &clkops_omap2_dflt_wait,
1382 .parent = &core_96m_fck,
1383 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1384 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1385 .clkdm_name = "core_l4_clkdm",
1386 .recalc = &followparent_recalc,
1387};
1388
1389static struct clk i2c3_fck = {
1390 .name = "i2c_fck",
1391 .ops = &clkops_omap2_dflt_wait,
1392 .id = 3,
1393 .parent = &core_96m_fck,
1394 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1395 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1396 .clkdm_name = "core_l4_clkdm",
1397 .recalc = &followparent_recalc,
1398};
1399
1400static struct clk i2c2_fck = {
1401 .name = "i2c_fck",
1402 .ops = &clkops_omap2_dflt_wait,
1403 .id = 2,
1404 .parent = &core_96m_fck,
1405 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1406 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1407 .clkdm_name = "core_l4_clkdm",
1408 .recalc = &followparent_recalc,
1409};
1410
1411static struct clk i2c1_fck = {
1412 .name = "i2c_fck",
1413 .ops = &clkops_omap2_dflt_wait,
1414 .id = 1,
1415 .parent = &core_96m_fck,
1416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1417 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1418 .clkdm_name = "core_l4_clkdm",
1419 .recalc = &followparent_recalc,
1420};
1421
1422/*
1423 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1424 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1425 */
1426static const struct clksel_rate common_mcbsp_96m_rates[] = {
1427 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1428 { .div = 0 }
1429};
1430
1431static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1432 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1433 { .div = 0 }
1434};
1435
1436static const struct clksel mcbsp_15_clksel[] = {
1437 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1438 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1439 { .parent = NULL }
1440};
1441
1442static struct clk mcbsp5_fck = {
1443 .name = "mcbsp_fck",
1444 .ops = &clkops_omap2_dflt_wait,
1445 .id = 5,
1446 .init = &omap2_init_clksel_parent,
1447 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1448 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1449 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1450 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1451 .clksel = mcbsp_15_clksel,
1452 .clkdm_name = "core_l4_clkdm",
1453 .recalc = &omap2_clksel_recalc,
1454};
1455
1456static struct clk mcbsp1_fck = {
1457 .name = "mcbsp_fck",
1458 .ops = &clkops_omap2_dflt_wait,
1459 .id = 1,
1460 .init = &omap2_init_clksel_parent,
1461 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1462 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1463 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1464 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1465 .clksel = mcbsp_15_clksel,
1466 .clkdm_name = "core_l4_clkdm",
1467 .recalc = &omap2_clksel_recalc,
1468};
1469
1470/* CORE_48M_FCK-derived clocks */
1471
1472static struct clk core_48m_fck = {
1473 .name = "core_48m_fck",
1474 .ops = &clkops_null,
1475 .parent = &omap_48m_fck,
1476 .clkdm_name = "core_l4_clkdm",
1477 .recalc = &followparent_recalc,
1478};
1479
1480static struct clk mcspi4_fck = {
1481 .name = "mcspi_fck",
1482 .ops = &clkops_omap2_dflt_wait,
1483 .id = 4,
1484 .parent = &core_48m_fck,
1485 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1486 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1487 .recalc = &followparent_recalc,
1488};
1489
1490static struct clk mcspi3_fck = {
1491 .name = "mcspi_fck",
1492 .ops = &clkops_omap2_dflt_wait,
1493 .id = 3,
1494 .parent = &core_48m_fck,
1495 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1496 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1497 .recalc = &followparent_recalc,
1498};
1499
1500static struct clk mcspi2_fck = {
1501 .name = "mcspi_fck",
1502 .ops = &clkops_omap2_dflt_wait,
1503 .id = 2,
1504 .parent = &core_48m_fck,
1505 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1506 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1507 .recalc = &followparent_recalc,
1508};
1509
1510static struct clk mcspi1_fck = {
1511 .name = "mcspi_fck",
1512 .ops = &clkops_omap2_dflt_wait,
1513 .id = 1,
1514 .parent = &core_48m_fck,
1515 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1516 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1517 .recalc = &followparent_recalc,
1518};
1519
1520static struct clk uart2_fck = {
1521 .name = "uart2_fck",
1522 .ops = &clkops_omap2_dflt_wait,
1523 .parent = &core_48m_fck,
1524 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1525 .enable_bit = OMAP3430_EN_UART2_SHIFT,
Kevin Hilman9b5bc5f2010-01-08 15:23:06 -0700[diff] [blame]1526 .clkdm_name = "core_l4_clkdm",
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1527 .recalc = &followparent_recalc,
1528};
1529
1530static struct clk uart1_fck = {
1531 .name = "uart1_fck",
1532 .ops = &clkops_omap2_dflt_wait,
1533 .parent = &core_48m_fck,
1534 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1535 .enable_bit = OMAP3430_EN_UART1_SHIFT,
Kevin Hilman9b5bc5f2010-01-08 15:23:06 -0700[diff] [blame]1536 .clkdm_name = "core_l4_clkdm",
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1537 .recalc = &followparent_recalc,
1538};
1539
1540static struct clk fshostusb_fck = {
1541 .name = "fshostusb_fck",
1542 .ops = &clkops_omap2_dflt_wait,
1543 .parent = &core_48m_fck,
1544 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1545 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1546 .recalc = &followparent_recalc,
1547};
1548
1549/* CORE_12M_FCK based clocks */
1550
1551static struct clk core_12m_fck = {
1552 .name = "core_12m_fck",
1553 .ops = &clkops_null,
1554 .parent = &omap_12m_fck,
1555 .clkdm_name = "core_l4_clkdm",
1556 .recalc = &followparent_recalc,
1557};
1558
1559static struct clk hdq_fck = {
1560 .name = "hdq_fck",
1561 .ops = &clkops_omap2_dflt_wait,
1562 .parent = &core_12m_fck,
1563 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1564 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1565 .recalc = &followparent_recalc,
1566};
1567
1568/* DPLL3-derived clock */
1569
1570static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1571 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1572 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1573 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1574 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1575 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1576 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1577 { .div = 0 }
1578};
1579
1580static const struct clksel ssi_ssr_clksel[] = {
1581 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1582 { .parent = NULL }
1583};
1584
1585static struct clk ssi_ssr_fck_3430es1 = {
1586 .name = "ssi_ssr_fck",
1587 .ops = &clkops_omap2_dflt,
1588 .init = &omap2_init_clksel_parent,
1589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1590 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1591 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1592 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1593 .clksel = ssi_ssr_clksel,
1594 .clkdm_name = "core_l4_clkdm",
1595 .recalc = &omap2_clksel_recalc,
1596};
1597
1598static struct clk ssi_ssr_fck_3430es2 = {
1599 .name = "ssi_ssr_fck",
1600 .ops = &clkops_omap3430es2_ssi_wait,
1601 .init = &omap2_init_clksel_parent,
1602 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1603 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1604 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1605 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1606 .clksel = ssi_ssr_clksel,
1607 .clkdm_name = "core_l4_clkdm",
1608 .recalc = &omap2_clksel_recalc,
1609};
1610
1611static struct clk ssi_sst_fck_3430es1 = {
1612 .name = "ssi_sst_fck",
1613 .ops = &clkops_null,
1614 .parent = &ssi_ssr_fck_3430es1,
1615 .fixed_div = 2,
Paul Walmsleye9b98f62010-01-26 20:12:57 -0700[diff] [blame]1616 .recalc = &omap_fixed_divisor_recalc,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1617};
1618
1619static struct clk ssi_sst_fck_3430es2 = {
1620 .name = "ssi_sst_fck",
1621 .ops = &clkops_null,
1622 .parent = &ssi_ssr_fck_3430es2,
1623 .fixed_div = 2,
Paul Walmsleye9b98f62010-01-26 20:12:57 -0700[diff] [blame]1624 .recalc = &omap_fixed_divisor_recalc,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1625};
1626
1627
1628
1629/* CORE_L3_ICK based clocks */
1630
1631/*
1632 * XXX must add clk_enable/clk_disable for these if standard code won't
1633 * handle it
1634 */
1635static struct clk core_l3_ick = {
1636 .name = "core_l3_ick",
1637 .ops = &clkops_null,
1638 .parent = &l3_ick,
1639 .clkdm_name = "core_l3_clkdm",
1640 .recalc = &followparent_recalc,
1641};
1642
1643static struct clk hsotgusb_ick_3430es1 = {
1644 .name = "hsotgusb_ick",
1645 .ops = &clkops_omap2_dflt,
1646 .parent = &core_l3_ick,
1647 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1648 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1649 .clkdm_name = "core_l3_clkdm",
1650 .recalc = &followparent_recalc,
1651};
1652
1653static struct clk hsotgusb_ick_3430es2 = {
1654 .name = "hsotgusb_ick",
1655 .ops = &clkops_omap3430es2_hsotgusb_wait,
1656 .parent = &core_l3_ick,
1657 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1658 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1659 .clkdm_name = "core_l3_clkdm",
1660 .recalc = &followparent_recalc,
1661};
1662
1663static struct clk sdrc_ick = {
1664 .name = "sdrc_ick",
1665 .ops = &clkops_omap2_dflt_wait,
1666 .parent = &core_l3_ick,
1667 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1668 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1669 .flags = ENABLE_ON_INIT,
1670 .clkdm_name = "core_l3_clkdm",
1671 .recalc = &followparent_recalc,
1672};
1673
1674static struct clk gpmc_fck = {
1675 .name = "gpmc_fck",
1676 .ops = &clkops_null,
1677 .parent = &core_l3_ick,
1678 .flags = ENABLE_ON_INIT, /* huh? */
1679 .clkdm_name = "core_l3_clkdm",
1680 .recalc = &followparent_recalc,
1681};
1682
1683/* SECURITY_L3_ICK based clocks */
1684
1685static struct clk security_l3_ick = {
1686 .name = "security_l3_ick",
1687 .ops = &clkops_null,
1688 .parent = &l3_ick,
1689 .recalc = &followparent_recalc,
1690};
1691
1692static struct clk pka_ick = {
1693 .name = "pka_ick",
1694 .ops = &clkops_omap2_dflt_wait,
1695 .parent = &security_l3_ick,
1696 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1697 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1698 .recalc = &followparent_recalc,
1699};
1700
1701/* CORE_L4_ICK based clocks */
1702
1703static struct clk core_l4_ick = {
1704 .name = "core_l4_ick",
1705 .ops = &clkops_null,
1706 .parent = &l4_ick,
1707 .clkdm_name = "core_l4_clkdm",
1708 .recalc = &followparent_recalc,
1709};
1710
1711static struct clk usbtll_ick = {
1712 .name = "usbtll_ick",
1713 .ops = &clkops_omap2_dflt_wait,
1714 .parent = &core_l4_ick,
1715 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1716 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1717 .clkdm_name = "core_l4_clkdm",
1718 .recalc = &followparent_recalc,
1719};
1720
1721static struct clk mmchs3_ick = {
1722 .name = "mmchs_ick",
1723 .ops = &clkops_omap2_dflt_wait,
1724 .id = 2,
1725 .parent = &core_l4_ick,
1726 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1727 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1728 .clkdm_name = "core_l4_clkdm",
1729 .recalc = &followparent_recalc,
1730};
1731
1732/* Intersystem Communication Registers - chassis mode only */
1733static struct clk icr_ick = {
1734 .name = "icr_ick",
1735 .ops = &clkops_omap2_dflt_wait,
1736 .parent = &core_l4_ick,
1737 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1738 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1739 .clkdm_name = "core_l4_clkdm",
1740 .recalc = &followparent_recalc,
1741};
1742
1743static struct clk aes2_ick = {
1744 .name = "aes2_ick",
1745 .ops = &clkops_omap2_dflt_wait,
1746 .parent = &core_l4_ick,
1747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1748 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1749 .clkdm_name = "core_l4_clkdm",
1750 .recalc = &followparent_recalc,
1751};
1752
1753static struct clk sha12_ick = {
1754 .name = "sha12_ick",
1755 .ops = &clkops_omap2_dflt_wait,
1756 .parent = &core_l4_ick,
1757 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1758 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1759 .clkdm_name = "core_l4_clkdm",
1760 .recalc = &followparent_recalc,
1761};
1762
1763static struct clk des2_ick = {
1764 .name = "des2_ick",
1765 .ops = &clkops_omap2_dflt_wait,
1766 .parent = &core_l4_ick,
1767 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1768 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1769 .clkdm_name = "core_l4_clkdm",
1770 .recalc = &followparent_recalc,
1771};
1772
1773static struct clk mmchs2_ick = {
1774 .name = "mmchs_ick",
1775 .ops = &clkops_omap2_dflt_wait,
1776 .id = 1,
1777 .parent = &core_l4_ick,
1778 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1779 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1780 .clkdm_name = "core_l4_clkdm",
1781 .recalc = &followparent_recalc,
1782};
1783
1784static struct clk mmchs1_ick = {
1785 .name = "mmchs_ick",
1786 .ops = &clkops_omap2_dflt_wait,
1787 .parent = &core_l4_ick,
1788 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1789 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1790 .clkdm_name = "core_l4_clkdm",
1791 .recalc = &followparent_recalc,
1792};
1793
1794static struct clk mspro_ick = {
1795 .name = "mspro_ick",
1796 .ops = &clkops_omap2_dflt_wait,
1797 .parent = &core_l4_ick,
1798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1799 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1800 .clkdm_name = "core_l4_clkdm",
1801 .recalc = &followparent_recalc,
1802};
1803
1804static struct clk hdq_ick = {
1805 .name = "hdq_ick",
1806 .ops = &clkops_omap2_dflt_wait,
1807 .parent = &core_l4_ick,
1808 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1809 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1810 .clkdm_name = "core_l4_clkdm",
1811 .recalc = &followparent_recalc,
1812};
1813
1814static struct clk mcspi4_ick = {
1815 .name = "mcspi_ick",
1816 .ops = &clkops_omap2_dflt_wait,
1817 .id = 4,
1818 .parent = &core_l4_ick,
1819 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1820 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1821 .clkdm_name = "core_l4_clkdm",
1822 .recalc = &followparent_recalc,
1823};
1824
1825static struct clk mcspi3_ick = {
1826 .name = "mcspi_ick",
1827 .ops = &clkops_omap2_dflt_wait,
1828 .id = 3,
1829 .parent = &core_l4_ick,
1830 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1831 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1832 .clkdm_name = "core_l4_clkdm",
1833 .recalc = &followparent_recalc,
1834};
1835
1836static struct clk mcspi2_ick = {
1837 .name = "mcspi_ick",
1838 .ops = &clkops_omap2_dflt_wait,
1839 .id = 2,
1840 .parent = &core_l4_ick,
1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1842 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1843 .clkdm_name = "core_l4_clkdm",
1844 .recalc = &followparent_recalc,
1845};
1846
1847static struct clk mcspi1_ick = {
1848 .name = "mcspi_ick",
1849 .ops = &clkops_omap2_dflt_wait,
1850 .id = 1,
1851 .parent = &core_l4_ick,
1852 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1854 .clkdm_name = "core_l4_clkdm",
1855 .recalc = &followparent_recalc,
1856};
1857
1858static struct clk i2c3_ick = {
1859 .name = "i2c_ick",
1860 .ops = &clkops_omap2_dflt_wait,
1861 .id = 3,
1862 .parent = &core_l4_ick,
1863 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1864 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1865 .clkdm_name = "core_l4_clkdm",
1866 .recalc = &followparent_recalc,
1867};
1868
1869static struct clk i2c2_ick = {
1870 .name = "i2c_ick",
1871 .ops = &clkops_omap2_dflt_wait,
1872 .id = 2,
1873 .parent = &core_l4_ick,
1874 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1875 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1876 .clkdm_name = "core_l4_clkdm",
1877 .recalc = &followparent_recalc,
1878};
1879
1880static struct clk i2c1_ick = {
1881 .name = "i2c_ick",
1882 .ops = &clkops_omap2_dflt_wait,
1883 .id = 1,
1884 .parent = &core_l4_ick,
1885 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1886 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1887 .clkdm_name = "core_l4_clkdm",
1888 .recalc = &followparent_recalc,
1889};
1890
1891static struct clk uart2_ick = {
1892 .name = "uart2_ick",
1893 .ops = &clkops_omap2_dflt_wait,
1894 .parent = &core_l4_ick,
1895 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1896 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1897 .clkdm_name = "core_l4_clkdm",
1898 .recalc = &followparent_recalc,
1899};
1900
1901static struct clk uart1_ick = {
1902 .name = "uart1_ick",
1903 .ops = &clkops_omap2_dflt_wait,
1904 .parent = &core_l4_ick,
1905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1906 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1907 .clkdm_name = "core_l4_clkdm",
1908 .recalc = &followparent_recalc,
1909};
1910
1911static struct clk gpt11_ick = {
1912 .name = "gpt11_ick",
1913 .ops = &clkops_omap2_dflt_wait,
1914 .parent = &core_l4_ick,
1915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1916 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1917 .clkdm_name = "core_l4_clkdm",
1918 .recalc = &followparent_recalc,
1919};
1920
1921static struct clk gpt10_ick = {
1922 .name = "gpt10_ick",
1923 .ops = &clkops_omap2_dflt_wait,
1924 .parent = &core_l4_ick,
1925 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1926 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1927 .clkdm_name = "core_l4_clkdm",
1928 .recalc = &followparent_recalc,
1929};
1930
1931static struct clk mcbsp5_ick = {
1932 .name = "mcbsp_ick",
1933 .ops = &clkops_omap2_dflt_wait,
1934 .id = 5,
1935 .parent = &core_l4_ick,
1936 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1937 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1938 .clkdm_name = "core_l4_clkdm",
1939 .recalc = &followparent_recalc,
1940};
1941
1942static struct clk mcbsp1_ick = {
1943 .name = "mcbsp_ick",
1944 .ops = &clkops_omap2_dflt_wait,
1945 .id = 1,
1946 .parent = &core_l4_ick,
1947 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1948 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1949 .clkdm_name = "core_l4_clkdm",
1950 .recalc = &followparent_recalc,
1951};
1952
1953static struct clk fac_ick = {
1954 .name = "fac_ick",
1955 .ops = &clkops_omap2_dflt_wait,
1956 .parent = &core_l4_ick,
1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1958 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1959 .clkdm_name = "core_l4_clkdm",
1960 .recalc = &followparent_recalc,
1961};
1962
1963static struct clk mailboxes_ick = {
1964 .name = "mailboxes_ick",
1965 .ops = &clkops_omap2_dflt_wait,
1966 .parent = &core_l4_ick,
1967 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1968 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1969 .clkdm_name = "core_l4_clkdm",
1970 .recalc = &followparent_recalc,
1971};
1972
1973static struct clk omapctrl_ick = {
1974 .name = "omapctrl_ick",
1975 .ops = &clkops_omap2_dflt_wait,
1976 .parent = &core_l4_ick,
1977 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1978 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
1979 .flags = ENABLE_ON_INIT,
1980 .recalc = &followparent_recalc,
1981};
1982
1983/* SSI_L4_ICK based clocks */
1984
1985static struct clk ssi_l4_ick = {
1986 .name = "ssi_l4_ick",
1987 .ops = &clkops_null,
1988 .parent = &l4_ick,
1989 .clkdm_name = "core_l4_clkdm",
1990 .recalc = &followparent_recalc,
1991};
1992
1993static struct clk ssi_ick_3430es1 = {
1994 .name = "ssi_ick",
1995 .ops = &clkops_omap2_dflt,
1996 .parent = &ssi_l4_ick,
1997 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1998 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1999 .clkdm_name = "core_l4_clkdm",
2000 .recalc = &followparent_recalc,
2001};
2002
2003static struct clk ssi_ick_3430es2 = {
2004 .name = "ssi_ick",
2005 .ops = &clkops_omap3430es2_ssi_wait,
2006 .parent = &ssi_l4_ick,
2007 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2008 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2009 .clkdm_name = "core_l4_clkdm",
2010 .recalc = &followparent_recalc,
2011};
2012
2013/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2014 * but l4_ick makes more sense to me */
2015
2016static const struct clksel usb_l4_clksel[] = {
2017 { .parent = &l4_ick, .rates = div2_rates },
2018 { .parent = NULL },
2019};
2020
2021static struct clk usb_l4_ick = {
2022 .name = "usb_l4_ick",
2023 .ops = &clkops_omap2_dflt_wait,
2024 .parent = &l4_ick,
2025 .init = &omap2_init_clksel_parent,
2026 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2027 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2028 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2029 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2030 .clksel = usb_l4_clksel,
2031 .recalc = &omap2_clksel_recalc,
2032};
2033
2034/* SECURITY_L4_ICK2 based clocks */
2035
2036static struct clk security_l4_ick2 = {
2037 .name = "security_l4_ick2",
2038 .ops = &clkops_null,
2039 .parent = &l4_ick,
2040 .recalc = &followparent_recalc,
2041};
2042
2043static struct clk aes1_ick = {
2044 .name = "aes1_ick",
2045 .ops = &clkops_omap2_dflt_wait,
2046 .parent = &security_l4_ick2,
2047 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2048 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2049 .recalc = &followparent_recalc,
2050};
2051
2052static struct clk rng_ick = {
2053 .name = "rng_ick",
2054 .ops = &clkops_omap2_dflt_wait,
2055 .parent = &security_l4_ick2,
2056 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2057 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2058 .recalc = &followparent_recalc,
2059};
2060
2061static struct clk sha11_ick = {
2062 .name = "sha11_ick",
2063 .ops = &clkops_omap2_dflt_wait,
2064 .parent = &security_l4_ick2,
2065 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2066 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2067 .recalc = &followparent_recalc,
2068};
2069
2070static struct clk des1_ick = {
2071 .name = "des1_ick",
2072 .ops = &clkops_omap2_dflt_wait,
2073 .parent = &security_l4_ick2,
2074 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2075 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2076 .recalc = &followparent_recalc,
2077};
2078
2079/* DSS */
2080static struct clk dss1_alwon_fck_3430es1 = {
2081 .name = "dss1_alwon_fck",
2082 .ops = &clkops_omap2_dflt,
2083 .parent = &dpll4_m4x2_ck,
2084 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2085 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2086 .clkdm_name = "dss_clkdm",
2087 .recalc = &followparent_recalc,
2088};
2089
2090static struct clk dss1_alwon_fck_3430es2 = {
2091 .name = "dss1_alwon_fck",
2092 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2093 .parent = &dpll4_m4x2_ck,
2094 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2095 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2096 .clkdm_name = "dss_clkdm",
2097 .recalc = &followparent_recalc,
2098};
2099
2100static struct clk dss_tv_fck = {
2101 .name = "dss_tv_fck",
2102 .ops = &clkops_omap2_dflt,
2103 .parent = &omap_54m_fck,
2104 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2105 .enable_bit = OMAP3430_EN_TV_SHIFT,
2106 .clkdm_name = "dss_clkdm",
2107 .recalc = &followparent_recalc,
2108};
2109
2110static struct clk dss_96m_fck = {
2111 .name = "dss_96m_fck",
2112 .ops = &clkops_omap2_dflt,
2113 .parent = &omap_96m_fck,
2114 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2115 .enable_bit = OMAP3430_EN_TV_SHIFT,
2116 .clkdm_name = "dss_clkdm",
2117 .recalc = &followparent_recalc,
2118};
2119
2120static struct clk dss2_alwon_fck = {
2121 .name = "dss2_alwon_fck",
2122 .ops = &clkops_omap2_dflt,
2123 .parent = &sys_ck,
2124 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2125 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2126 .clkdm_name = "dss_clkdm",
2127 .recalc = &followparent_recalc,
2128};
2129
2130static struct clk dss_ick_3430es1 = {
2131 /* Handles both L3 and L4 clocks */
2132 .name = "dss_ick",
2133 .ops = &clkops_omap2_dflt,
2134 .parent = &l4_ick,
2135 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2136 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2137 .clkdm_name = "dss_clkdm",
2138 .recalc = &followparent_recalc,
2139};
2140
2141static struct clk dss_ick_3430es2 = {
2142 /* Handles both L3 and L4 clocks */
2143 .name = "dss_ick",
2144 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2145 .parent = &l4_ick,
2146 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2147 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2148 .clkdm_name = "dss_clkdm",
2149 .recalc = &followparent_recalc,
2150};
2151
2152/* CAM */
2153
2154static struct clk cam_mclk = {
2155 .name = "cam_mclk",
2156 .ops = &clkops_omap2_dflt,
2157 .parent = &dpll4_m5x2_ck,
2158 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2159 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2160 .clkdm_name = "cam_clkdm",
2161 .recalc = &followparent_recalc,
2162};
2163
2164static struct clk cam_ick = {
2165 /* Handles both L3 and L4 clocks */
2166 .name = "cam_ick",
2167 .ops = &clkops_omap2_dflt,
2168 .parent = &l4_ick,
2169 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2170 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2171 .clkdm_name = "cam_clkdm",
2172 .recalc = &followparent_recalc,
2173};
2174
2175static struct clk csi2_96m_fck = {
2176 .name = "csi2_96m_fck",
2177 .ops = &clkops_omap2_dflt,
2178 .parent = &core_96m_fck,
2179 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2180 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2181 .clkdm_name = "cam_clkdm",
2182 .recalc = &followparent_recalc,
2183};
2184
2185/* USBHOST - 3430ES2 only */
2186
2187static struct clk usbhost_120m_fck = {
2188 .name = "usbhost_120m_fck",
2189 .ops = &clkops_omap2_dflt,
2190 .parent = &dpll5_m2_ck,
2191 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2192 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2193 .clkdm_name = "usbhost_clkdm",
2194 .recalc = &followparent_recalc,
2195};
2196
2197static struct clk usbhost_48m_fck = {
2198 .name = "usbhost_48m_fck",
2199 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2200 .parent = &omap_48m_fck,
2201 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2202 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2203 .clkdm_name = "usbhost_clkdm",
2204 .recalc = &followparent_recalc,
2205};
2206
2207static struct clk usbhost_ick = {
2208 /* Handles both L3 and L4 clocks */
2209 .name = "usbhost_ick",
2210 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2211 .parent = &l4_ick,
2212 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2213 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2214 .clkdm_name = "usbhost_clkdm",
2215 .recalc = &followparent_recalc,
2216};
2217
2218/* WKUP */
2219
2220static const struct clksel_rate usim_96m_rates[] = {
2221 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2222 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2223 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2224 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2225 { .div = 0 },
2226};
2227
2228static const struct clksel_rate usim_120m_rates[] = {
2229 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2230 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2231 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2232 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2233 { .div = 0 },
2234};
2235
2236static const struct clksel usim_clksel[] = {
2237 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2238 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2239 { .parent = &sys_ck, .rates = div2_rates },
2240 { .parent = NULL },
2241};
2242
2243/* 3430ES2 only */
2244static struct clk usim_fck = {
2245 .name = "usim_fck",
2246 .ops = &clkops_omap2_dflt_wait,
2247 .init = &omap2_init_clksel_parent,
2248 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2249 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2250 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2251 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2252 .clksel = usim_clksel,
2253 .recalc = &omap2_clksel_recalc,
2254};
2255
2256/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2257static struct clk gpt1_fck = {
2258 .name = "gpt1_fck",
2259 .ops = &clkops_omap2_dflt_wait,
2260 .init = &omap2_init_clksel_parent,
2261 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2262 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2263 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2264 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2265 .clksel = omap343x_gpt_clksel,
2266 .clkdm_name = "wkup_clkdm",
2267 .recalc = &omap2_clksel_recalc,
2268};
2269
2270static struct clk wkup_32k_fck = {
2271 .name = "wkup_32k_fck",
2272 .ops = &clkops_null,
2273 .parent = &omap_32k_fck,
2274 .clkdm_name = "wkup_clkdm",
2275 .recalc = &followparent_recalc,
2276};
2277
2278static struct clk gpio1_dbck = {
2279 .name = "gpio1_dbck",
2280 .ops = &clkops_omap2_dflt,
2281 .parent = &wkup_32k_fck,
2282 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2283 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2284 .clkdm_name = "wkup_clkdm",
2285 .recalc = &followparent_recalc,
2286};
2287
2288static struct clk wdt2_fck = {
2289 .name = "wdt2_fck",
2290 .ops = &clkops_omap2_dflt_wait,
2291 .parent = &wkup_32k_fck,
2292 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2293 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2294 .clkdm_name = "wkup_clkdm",
2295 .recalc = &followparent_recalc,
2296};
2297
2298static struct clk wkup_l4_ick = {
2299 .name = "wkup_l4_ick",
2300 .ops = &clkops_null,
2301 .parent = &sys_ck,
2302 .clkdm_name = "wkup_clkdm",
2303 .recalc = &followparent_recalc,
2304};
2305
2306/* 3430ES2 only */
2307/* Never specifically named in the TRM, so we have to infer a likely name */
2308static struct clk usim_ick = {
2309 .name = "usim_ick",
2310 .ops = &clkops_omap2_dflt_wait,
2311 .parent = &wkup_l4_ick,
2312 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2313 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2314 .clkdm_name = "wkup_clkdm",
2315 .recalc = &followparent_recalc,
2316};
2317
2318static struct clk wdt2_ick = {
2319 .name = "wdt2_ick",
2320 .ops = &clkops_omap2_dflt_wait,
2321 .parent = &wkup_l4_ick,
2322 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2323 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2324 .clkdm_name = "wkup_clkdm",
2325 .recalc = &followparent_recalc,
2326};
2327
2328static struct clk wdt1_ick = {
2329 .name = "wdt1_ick",
2330 .ops = &clkops_omap2_dflt_wait,
2331 .parent = &wkup_l4_ick,
2332 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2333 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2334 .clkdm_name = "wkup_clkdm",
2335 .recalc = &followparent_recalc,
2336};
2337
2338static struct clk gpio1_ick = {
2339 .name = "gpio1_ick",
2340 .ops = &clkops_omap2_dflt_wait,
2341 .parent = &wkup_l4_ick,
2342 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2343 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2344 .clkdm_name = "wkup_clkdm",
2345 .recalc = &followparent_recalc,
2346};
2347
2348static struct clk omap_32ksync_ick = {
2349 .name = "omap_32ksync_ick",
2350 .ops = &clkops_omap2_dflt_wait,
2351 .parent = &wkup_l4_ick,
2352 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2353 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2354 .clkdm_name = "wkup_clkdm",
2355 .recalc = &followparent_recalc,
2356};
2357
2358/* XXX This clock no longer exists in 3430 TRM rev F */
2359static struct clk gpt12_ick = {
2360 .name = "gpt12_ick",
2361 .ops = &clkops_omap2_dflt_wait,
2362 .parent = &wkup_l4_ick,
2363 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2364 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2365 .clkdm_name = "wkup_clkdm",
2366 .recalc = &followparent_recalc,
2367};
2368
2369static struct clk gpt1_ick = {
2370 .name = "gpt1_ick",
2371 .ops = &clkops_omap2_dflt_wait,
2372 .parent = &wkup_l4_ick,
2373 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2374 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2375 .clkdm_name = "wkup_clkdm",
2376 .recalc = &followparent_recalc,
2377};
2378
2379
2380
2381/* PER clock domain */
2382
2383static struct clk per_96m_fck = {
2384 .name = "per_96m_fck",
2385 .ops = &clkops_null,
2386 .parent = &omap_96m_alwon_fck,
2387 .clkdm_name = "per_clkdm",
2388 .recalc = &followparent_recalc,
2389};
2390
2391static struct clk per_48m_fck = {
2392 .name = "per_48m_fck",
2393 .ops = &clkops_null,
2394 .parent = &omap_48m_fck,
2395 .clkdm_name = "per_clkdm",
2396 .recalc = &followparent_recalc,
2397};
2398
2399static struct clk uart3_fck = {
2400 .name = "uart3_fck",
2401 .ops = &clkops_omap2_dflt_wait,
2402 .parent = &per_48m_fck,
2403 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2404 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2405 .clkdm_name = "per_clkdm",
2406 .recalc = &followparent_recalc,
2407};
2408
2409static struct clk gpt2_fck = {
2410 .name = "gpt2_fck",
2411 .ops = &clkops_omap2_dflt_wait,
2412 .init = &omap2_init_clksel_parent,
2413 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2414 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2415 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2416 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2417 .clksel = omap343x_gpt_clksel,
2418 .clkdm_name = "per_clkdm",
2419 .recalc = &omap2_clksel_recalc,
2420};
2421
2422static struct clk gpt3_fck = {
2423 .name = "gpt3_fck",
2424 .ops = &clkops_omap2_dflt_wait,
2425 .init = &omap2_init_clksel_parent,
2426 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2427 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2428 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2429 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2430 .clksel = omap343x_gpt_clksel,
2431 .clkdm_name = "per_clkdm",
2432 .recalc = &omap2_clksel_recalc,
2433};
2434
2435static struct clk gpt4_fck = {
2436 .name = "gpt4_fck",
2437 .ops = &clkops_omap2_dflt_wait,
2438 .init = &omap2_init_clksel_parent,
2439 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2440 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2441 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2442 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2443 .clksel = omap343x_gpt_clksel,
2444 .clkdm_name = "per_clkdm",
2445 .recalc = &omap2_clksel_recalc,
2446};
2447
2448static struct clk gpt5_fck = {
2449 .name = "gpt5_fck",
2450 .ops = &clkops_omap2_dflt_wait,
2451 .init = &omap2_init_clksel_parent,
2452 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2453 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2454 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2455 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2456 .clksel = omap343x_gpt_clksel,
2457 .clkdm_name = "per_clkdm",
2458 .recalc = &omap2_clksel_recalc,
2459};
2460
2461static struct clk gpt6_fck = {
2462 .name = "gpt6_fck",
2463 .ops = &clkops_omap2_dflt_wait,
2464 .init = &omap2_init_clksel_parent,
2465 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2466 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2467 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2468 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2469 .clksel = omap343x_gpt_clksel,
2470 .clkdm_name = "per_clkdm",
2471 .recalc = &omap2_clksel_recalc,
2472};
2473
2474static struct clk gpt7_fck = {
2475 .name = "gpt7_fck",
2476 .ops = &clkops_omap2_dflt_wait,
2477 .init = &omap2_init_clksel_parent,
2478 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2479 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2480 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2481 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2482 .clksel = omap343x_gpt_clksel,
2483 .clkdm_name = "per_clkdm",
2484 .recalc = &omap2_clksel_recalc,
2485};
2486
2487static struct clk gpt8_fck = {
2488 .name = "gpt8_fck",
2489 .ops = &clkops_omap2_dflt_wait,
2490 .init = &omap2_init_clksel_parent,
2491 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2492 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2493 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2494 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2495 .clksel = omap343x_gpt_clksel,
2496 .clkdm_name = "per_clkdm",
2497 .recalc = &omap2_clksel_recalc,
2498};
2499
2500static struct clk gpt9_fck = {
2501 .name = "gpt9_fck",
2502 .ops = &clkops_omap2_dflt_wait,
2503 .init = &omap2_init_clksel_parent,
2504 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2505 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2506 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2507 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2508 .clksel = omap343x_gpt_clksel,
2509 .clkdm_name = "per_clkdm",
2510 .recalc = &omap2_clksel_recalc,
2511};
2512
2513static struct clk per_32k_alwon_fck = {
2514 .name = "per_32k_alwon_fck",
2515 .ops = &clkops_null,
2516 .parent = &omap_32k_fck,
2517 .clkdm_name = "per_clkdm",
2518 .recalc = &followparent_recalc,
2519};
2520
2521static struct clk gpio6_dbck = {
2522 .name = "gpio6_dbck",
2523 .ops = &clkops_omap2_dflt,
2524 .parent = &per_32k_alwon_fck,
2525 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2526 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2527 .clkdm_name = "per_clkdm",
2528 .recalc = &followparent_recalc,
2529};
2530
2531static struct clk gpio5_dbck = {
2532 .name = "gpio5_dbck",
2533 .ops = &clkops_omap2_dflt,
2534 .parent = &per_32k_alwon_fck,
2535 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2536 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2537 .clkdm_name = "per_clkdm",
2538 .recalc = &followparent_recalc,
2539};
2540
2541static struct clk gpio4_dbck = {
2542 .name = "gpio4_dbck",
2543 .ops = &clkops_omap2_dflt,
2544 .parent = &per_32k_alwon_fck,
2545 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2546 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2547 .clkdm_name = "per_clkdm",
2548 .recalc = &followparent_recalc,
2549};
2550
2551static struct clk gpio3_dbck = {
2552 .name = "gpio3_dbck",
2553 .ops = &clkops_omap2_dflt,
2554 .parent = &per_32k_alwon_fck,
2555 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2556 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2557 .clkdm_name = "per_clkdm",
2558 .recalc = &followparent_recalc,
2559};
2560
2561static struct clk gpio2_dbck = {
2562 .name = "gpio2_dbck",
2563 .ops = &clkops_omap2_dflt,
2564 .parent = &per_32k_alwon_fck,
2565 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2566 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2567 .clkdm_name = "per_clkdm",
2568 .recalc = &followparent_recalc,
2569};
2570
2571static struct clk wdt3_fck = {
2572 .name = "wdt3_fck",
2573 .ops = &clkops_omap2_dflt_wait,
2574 .parent = &per_32k_alwon_fck,
2575 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2576 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2577 .clkdm_name = "per_clkdm",
2578 .recalc = &followparent_recalc,
2579};
2580
2581static struct clk per_l4_ick = {
2582 .name = "per_l4_ick",
2583 .ops = &clkops_null,
2584 .parent = &l4_ick,
2585 .clkdm_name = "per_clkdm",
2586 .recalc = &followparent_recalc,
2587};
2588
2589static struct clk gpio6_ick = {
2590 .name = "gpio6_ick",
2591 .ops = &clkops_omap2_dflt_wait,
2592 .parent = &per_l4_ick,
2593 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2594 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2595 .clkdm_name = "per_clkdm",
2596 .recalc = &followparent_recalc,
2597};
2598
2599static struct clk gpio5_ick = {
2600 .name = "gpio5_ick",
2601 .ops = &clkops_omap2_dflt_wait,
2602 .parent = &per_l4_ick,
2603 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2604 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2605 .clkdm_name = "per_clkdm",
2606 .recalc = &followparent_recalc,
2607};
2608
2609static struct clk gpio4_ick = {
2610 .name = "gpio4_ick",
2611 .ops = &clkops_omap2_dflt_wait,
2612 .parent = &per_l4_ick,
2613 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2614 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2615 .clkdm_name = "per_clkdm",
2616 .recalc = &followparent_recalc,
2617};
2618
2619static struct clk gpio3_ick = {
2620 .name = "gpio3_ick",
2621 .ops = &clkops_omap2_dflt_wait,
2622 .parent = &per_l4_ick,
2623 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2624 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2625 .clkdm_name = "per_clkdm",
2626 .recalc = &followparent_recalc,
2627};
2628
2629static struct clk gpio2_ick = {
2630 .name = "gpio2_ick",
2631 .ops = &clkops_omap2_dflt_wait,
2632 .parent = &per_l4_ick,
2633 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2634 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2635 .clkdm_name = "per_clkdm",
2636 .recalc = &followparent_recalc,
2637};
2638
2639static struct clk wdt3_ick = {
2640 .name = "wdt3_ick",
2641 .ops = &clkops_omap2_dflt_wait,
2642 .parent = &per_l4_ick,
2643 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2644 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2645 .clkdm_name = "per_clkdm",
2646 .recalc = &followparent_recalc,
2647};
2648
2649static struct clk uart3_ick = {
2650 .name = "uart3_ick",
2651 .ops = &clkops_omap2_dflt_wait,
2652 .parent = &per_l4_ick,
2653 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2654 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2655 .clkdm_name = "per_clkdm",
2656 .recalc = &followparent_recalc,
2657};
2658
2659static struct clk gpt9_ick = {
2660 .name = "gpt9_ick",
2661 .ops = &clkops_omap2_dflt_wait,
2662 .parent = &per_l4_ick,
2663 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2664 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2665 .clkdm_name = "per_clkdm",
2666 .recalc = &followparent_recalc,
2667};
2668
2669static struct clk gpt8_ick = {
2670 .name = "gpt8_ick",
2671 .ops = &clkops_omap2_dflt_wait,
2672 .parent = &per_l4_ick,
2673 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2674 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2675 .clkdm_name = "per_clkdm",
2676 .recalc = &followparent_recalc,
2677};
2678
2679static struct clk gpt7_ick = {
2680 .name = "gpt7_ick",
2681 .ops = &clkops_omap2_dflt_wait,
2682 .parent = &per_l4_ick,
2683 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2684 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2685 .clkdm_name = "per_clkdm",
2686 .recalc = &followparent_recalc,
2687};
2688
2689static struct clk gpt6_ick = {
2690 .name = "gpt6_ick",
2691 .ops = &clkops_omap2_dflt_wait,
2692 .parent = &per_l4_ick,
2693 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2694 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2695 .clkdm_name = "per_clkdm",
2696 .recalc = &followparent_recalc,
2697};
2698
2699static struct clk gpt5_ick = {
2700 .name = "gpt5_ick",
2701 .ops = &clkops_omap2_dflt_wait,
2702 .parent = &per_l4_ick,
2703 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2704 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2705 .clkdm_name = "per_clkdm",
2706 .recalc = &followparent_recalc,
2707};
2708
2709static struct clk gpt4_ick = {
2710 .name = "gpt4_ick",
2711 .ops = &clkops_omap2_dflt_wait,
2712 .parent = &per_l4_ick,
2713 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2714 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2715 .clkdm_name = "per_clkdm",
2716 .recalc = &followparent_recalc,
2717};
2718
2719static struct clk gpt3_ick = {
2720 .name = "gpt3_ick",
2721 .ops = &clkops_omap2_dflt_wait,
2722 .parent = &per_l4_ick,
2723 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2724 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2725 .clkdm_name = "per_clkdm",
2726 .recalc = &followparent_recalc,
2727};
2728
2729static struct clk gpt2_ick = {
2730 .name = "gpt2_ick",
2731 .ops = &clkops_omap2_dflt_wait,
2732 .parent = &per_l4_ick,
2733 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2734 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2735 .clkdm_name = "per_clkdm",
2736 .recalc = &followparent_recalc,
2737};
2738
2739static struct clk mcbsp2_ick = {
2740 .name = "mcbsp_ick",
2741 .ops = &clkops_omap2_dflt_wait,
2742 .id = 2,
2743 .parent = &per_l4_ick,
2744 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2745 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2746 .clkdm_name = "per_clkdm",
2747 .recalc = &followparent_recalc,
2748};
2749
2750static struct clk mcbsp3_ick = {
2751 .name = "mcbsp_ick",
2752 .ops = &clkops_omap2_dflt_wait,
2753 .id = 3,
2754 .parent = &per_l4_ick,
2755 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2756 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2757 .clkdm_name = "per_clkdm",
2758 .recalc = &followparent_recalc,
2759};
2760
2761static struct clk mcbsp4_ick = {
2762 .name = "mcbsp_ick",
2763 .ops = &clkops_omap2_dflt_wait,
2764 .id = 4,
2765 .parent = &per_l4_ick,
2766 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2767 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2768 .clkdm_name = "per_clkdm",
2769 .recalc = &followparent_recalc,
2770};
2771
2772static const struct clksel mcbsp_234_clksel[] = {
Paul Walmsley073463c2010-01-08 15:23:07 -0700[diff] [blame]2773 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]2774 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2775 { .parent = NULL }
2776};
2777
2778static struct clk mcbsp2_fck = {
2779 .name = "mcbsp_fck",
2780 .ops = &clkops_omap2_dflt_wait,
2781 .id = 2,
2782 .init = &omap2_init_clksel_parent,
2783 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2784 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2785 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2786 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2787 .clksel = mcbsp_234_clksel,
2788 .clkdm_name = "per_clkdm",
2789 .recalc = &omap2_clksel_recalc,
2790};
2791
2792static struct clk mcbsp3_fck = {
2793 .name = "mcbsp_fck",
2794 .ops = &clkops_omap2_dflt_wait,
2795 .id = 3,
2796 .init = &omap2_init_clksel_parent,
2797 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2798 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2799 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2800 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2801 .clksel = mcbsp_234_clksel,
2802 .clkdm_name = "per_clkdm",
2803 .recalc = &omap2_clksel_recalc,
2804};
2805
2806static struct clk mcbsp4_fck = {
2807 .name = "mcbsp_fck",
2808 .ops = &clkops_omap2_dflt_wait,
2809 .id = 4,
2810 .init = &omap2_init_clksel_parent,
2811 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2812 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2813 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2814 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2815 .clksel = mcbsp_234_clksel,
2816 .clkdm_name = "per_clkdm",
2817 .recalc = &omap2_clksel_recalc,
2818};
2819
2820/* EMU clocks */
2821
2822/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2823
2824static const struct clksel_rate emu_src_sys_rates[] = {
2825 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2826 { .div = 0 },
2827};
2828
2829static const struct clksel_rate emu_src_core_rates[] = {
2830 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2831 { .div = 0 },
2832};
2833
2834static const struct clksel_rate emu_src_per_rates[] = {
2835 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2836 { .div = 0 },
2837};
2838
2839static const struct clksel_rate emu_src_mpu_rates[] = {
2840 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2841 { .div = 0 },
2842};
2843
2844static const struct clksel emu_src_clksel[] = {
2845 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2846 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2847 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2848 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2849 { .parent = NULL },
2850};
2851
2852/*
2853 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2854 * to switch the source of some of the EMU clocks.
2855 * XXX Are there CLKEN bits for these EMU clks?
2856 */
2857static struct clk emu_src_ck = {
2858 .name = "emu_src_ck",
2859 .ops = &clkops_null,
2860 .init = &omap2_init_clksel_parent,
2861 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2862 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2863 .clksel = emu_src_clksel,
2864 .clkdm_name = "emu_clkdm",
2865 .recalc = &omap2_clksel_recalc,
2866};
2867
2868static const struct clksel_rate pclk_emu_rates[] = {
2869 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2870 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2871 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2872 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2873 { .div = 0 },
2874};
2875
2876static const struct clksel pclk_emu_clksel[] = {
2877 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2878 { .parent = NULL },
2879};
2880
2881static struct clk pclk_fck = {
2882 .name = "pclk_fck",
2883 .ops = &clkops_null,
2884 .init = &omap2_init_clksel_parent,
2885 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2886 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2887 .clksel = pclk_emu_clksel,
2888 .clkdm_name = "emu_clkdm",
2889 .recalc = &omap2_clksel_recalc,
2890};
2891
2892static const struct clksel_rate pclkx2_emu_rates[] = {
2893 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2894 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2895 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2896 { .div = 0 },
2897};
2898
2899static const struct clksel pclkx2_emu_clksel[] = {
2900 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2901 { .parent = NULL },
2902};
2903
2904static struct clk pclkx2_fck = {
2905 .name = "pclkx2_fck",
2906 .ops = &clkops_null,
2907 .init = &omap2_init_clksel_parent,
2908 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2909 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2910 .clksel = pclkx2_emu_clksel,
2911 .clkdm_name = "emu_clkdm",
2912 .recalc = &omap2_clksel_recalc,
2913};
2914
2915static const struct clksel atclk_emu_clksel[] = {
2916 { .parent = &emu_src_ck, .rates = div2_rates },
2917 { .parent = NULL },
2918};
2919
2920static struct clk atclk_fck = {
2921 .name = "atclk_fck",
2922 .ops = &clkops_null,
2923 .init = &omap2_init_clksel_parent,
2924 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2925 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2926 .clksel = atclk_emu_clksel,
2927 .clkdm_name = "emu_clkdm",
2928 .recalc = &omap2_clksel_recalc,
2929};
2930
2931static struct clk traceclk_src_fck = {
2932 .name = "traceclk_src_fck",
2933 .ops = &clkops_null,
2934 .init = &omap2_init_clksel_parent,
2935 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2936 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2937 .clksel = emu_src_clksel,
2938 .clkdm_name = "emu_clkdm",
2939 .recalc = &omap2_clksel_recalc,
2940};
2941
2942static const struct clksel_rate traceclk_rates[] = {
2943 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2944 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2945 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2946 { .div = 0 },
2947};
2948
2949static const struct clksel traceclk_clksel[] = {
2950 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2951 { .parent = NULL },
2952};
2953
2954static struct clk traceclk_fck = {
2955 .name = "traceclk_fck",
2956 .ops = &clkops_null,
2957 .init = &omap2_init_clksel_parent,
2958 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2959 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2960 .clksel = traceclk_clksel,
2961 .clkdm_name = "emu_clkdm",
2962 .recalc = &omap2_clksel_recalc,
2963};
2964
2965/* SR clocks */
2966
2967/* SmartReflex fclk (VDD1) */
2968static struct clk sr1_fck = {
2969 .name = "sr1_fck",
2970 .ops = &clkops_omap2_dflt_wait,
2971 .parent = &sys_ck,
2972 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2973 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2974 .recalc = &followparent_recalc,
2975};
2976
2977/* SmartReflex fclk (VDD2) */
2978static struct clk sr2_fck = {
2979 .name = "sr2_fck",
2980 .ops = &clkops_omap2_dflt_wait,
2981 .parent = &sys_ck,
2982 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2983 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2984 .recalc = &followparent_recalc,
2985};
2986
2987static struct clk sr_l4_ick = {
2988 .name = "sr_l4_ick",
2989 .ops = &clkops_null, /* RMK: missing? */
2990 .parent = &l4_ick,
2991 .clkdm_name = "core_l4_clkdm",
2992 .recalc = &followparent_recalc,
2993};
2994
2995/* SECURE_32K_FCK clocks */
2996
2997static struct clk gpt12_fck = {
2998 .name = "gpt12_fck",
2999 .ops = &clkops_null,
3000 .parent = &secure_32k_fck,
3001 .recalc = &followparent_recalc,
3002};
3003
3004static struct clk wdt1_fck = {
3005 .name = "wdt1_fck",
3006 .ops = &clkops_null,
3007 .parent = &secure_32k_fck,
3008 .recalc = &followparent_recalc,
3009};
3010
Ranjith Lohithakshan3cc4a2f2010-02-24 12:05:55 -0700[diff] [blame]3011/* Clocks for AM35XX */
3012static struct clk ipss_ick = {
3013 .name = "ipss_ick",
3014 .ops = &clkops_am35xx_ipss_wait,
3015 .parent = &core_l3_ick,
3016 .clkdm_name = "core_l3_clkdm",
3017 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3018 .enable_bit = AM35XX_EN_IPSS_SHIFT,
3019 .recalc = &followparent_recalc,
3020};
3021
3022static struct clk emac_ick = {
3023 .name = "emac_ick",
3024 .ops = &clkops_am35xx_ipss_module_wait,
3025 .parent = &ipss_ick,
3026 .clkdm_name = "core_l3_clkdm",
3027 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3028 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3029 .recalc = &followparent_recalc,
3030};
3031
3032static struct clk rmii_ck = {
3033 .name = "rmii_ck",
3034 .ops = &clkops_null,
3035 .flags = RATE_FIXED,
3036 .rate = 50000000,
3037};
3038
3039static struct clk emac_fck = {
3040 .name = "emac_fck",
3041 .ops = &clkops_omap2_dflt,
3042 .parent = &rmii_ck,
3043 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3044 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
3045 .recalc = &followparent_recalc,
3046};
3047
3048static struct clk hsotgusb_ick_am35xx = {
3049 .name = "hsotgusb_ick",
3050 .ops = &clkops_am35xx_ipss_module_wait,
3051 .parent = &ipss_ick,
3052 .clkdm_name = "core_l3_clkdm",
3053 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3054 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3055 .recalc = &followparent_recalc,
3056};
3057
3058static struct clk hsotgusb_fck_am35xx = {
3059 .name = "hsotgusb_fck",
3060 .ops = &clkops_omap2_dflt,
3061 .parent = &sys_ck,
3062 .clkdm_name = "core_l3_clkdm",
3063 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3064 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
3065 .recalc = &followparent_recalc,
3066};
3067
3068static struct clk hecc_ck = {
3069 .name = "hecc_ck",
3070 .ops = &clkops_am35xx_ipss_module_wait,
3071 .parent = &sys_ck,
3072 .clkdm_name = "core_l3_clkdm",
3073 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3074 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
3075 .recalc = &followparent_recalc,
3076};
3077
3078static struct clk vpfe_ick = {
3079 .name = "vpfe_ick",
3080 .ops = &clkops_am35xx_ipss_module_wait,
3081 .parent = &ipss_ick,
3082 .clkdm_name = "core_l3_clkdm",
3083 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3084 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3085 .recalc = &followparent_recalc,
3086};
3087
3088static struct clk pclk_ck = {
3089 .name = "pclk_ck",
3090 .ops = &clkops_null,
3091 .flags = RATE_FIXED,
3092 .rate = 27000000,
3093};
3094
3095static struct clk vpfe_fck = {
3096 .name = "vpfe_fck",
3097 .ops = &clkops_omap2_dflt,
3098 .parent = &pclk_ck,
3099 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3100 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3101 .recalc = &followparent_recalc,
3102};
3103
3104/*
3105 * The UART1/2 functional clock acts as the functional
3106 * clock for UART4. No separate fclk control available.
3107 */
3108static struct clk uart4_ick_am35xx = {
3109 .name = "uart4_ick",
3110 .ops = &clkops_omap2_dflt_wait,
3111 .parent = &core_l4_ick,
3112 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3113 .enable_bit = AM35XX_EN_UART4_SHIFT,
3114 .clkdm_name = "core_l4_clkdm",
3115 .recalc = &followparent_recalc,
3116};
3117
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3118
3119/*
3120 * clkdev
3121 */
3122
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3123/* XXX At some point we should rename this file to clock3xxx_data.c */
3124static struct omap_clk omap3xxx_clks[] = {
3125 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3126 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3127 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3128 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
3129 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3130 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
3131 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3132 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3133 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3134 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3135 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3136 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3137 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3138 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3139 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3140 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
3141 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3142 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3143 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3144 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
3145 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
3146 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3147 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3148 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3149 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3150 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3151 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
3152 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3153 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3154 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3155 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
3156 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
3157 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
3158 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
3159 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3160 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
3161 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3162 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
3163 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3164 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
3165 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3166 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3167 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3168 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3169 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX),
3170 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX),
3171 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3172 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3173 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
3174 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3175 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3176 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3177 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3178 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
3179 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3180 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3181 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3182 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3183 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3184 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3185 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3186 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3187 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3188 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517),
3189 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3190 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3191 CLK(NULL, "modem_fck", &modem_fck, CK_343X),
3192 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
3193 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3194 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3195 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3196 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX),
3197 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX),
3198 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX),
3199 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3200 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX),
3201 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3202 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3203 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
3204 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX),
3205 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX),
3206 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_3XXX),
3207 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX),
3208 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX),
3209 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3210 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX),
3211 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX),
3212 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX),
3213 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX),
3214 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3215 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3216 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3217 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3218 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3219 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3220 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
3221 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3222 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3223 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3224 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3225 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3226 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3227 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3228 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
3229 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3230 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3231 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX),
3232 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3233 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
3234 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
3235 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
3236 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3237 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
3238 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3239 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3240 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3241 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3242 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3243 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3244 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3245 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_3XXX),
3246 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_3XXX),
3247 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_3XXX),
3248 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3249 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3250 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3251 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3252 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3253 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3254 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3255 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3256 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3257 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
3258 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3259 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
3260 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3261 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
3262 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
3263 CLK("omap_rng", "ick", &rng_ick, CK_343X),
3264 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
3265 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
3266 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3267 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
3268 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX),
3269 CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX),
3270 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3271 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3272 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3273 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
3274 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
3275 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3276 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
3277 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
3278 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3279 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3280 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3281 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3282 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3283 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3284 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
3285 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3286 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3287 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3288 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3289 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3290 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3291 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3292 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3293 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3294 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3295 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3296 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3297 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3298 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3299 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3300 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3301 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3302 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3303 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3304 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3305 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3306 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3307 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3308 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3309 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3310 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3311 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3312 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3313 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3314 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3315 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3316 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3317 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3318 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3319 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3320 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3321 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3322 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3323 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3324 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3325 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3326 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3327 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3328 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3329 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX),
3330 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX),
3331 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX),
3332 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3333 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3334 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3335 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3336 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3337 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3338 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
3339 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
3340 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3341 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3342 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3343 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
Ranjith Lohithakshan3cc4a2f2010-02-24 12:05:55 -0700[diff] [blame]3344 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3345 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3346 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3347 CLK("davinci_emac", "ick", &emac_ick, CK_AM35XX),
3348 CLK("davinci_emac", "fck", &emac_fck, CK_AM35XX),
3349 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3350 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3351 CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3352 CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3353 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3354 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3355};
3356
3357
Paul Walmsleye80a9722010-01-26 20:13:12 -0700[diff] [blame]3358int __init omap3xxx_clk_init(void)
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3359{
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3360 struct omap_clk *c;
Paul Walmsley2c8a1772010-01-26 20:12:56 -0700[diff] [blame]3361 u32 cpu_clkflg = CK_3XXX;
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3362
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3363 if (cpu_is_omap3517()) {
3364 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3365 cpu_clkflg |= CK_3517;
3366 } else if (cpu_is_omap3505()) {
3367 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3368 cpu_clkflg |= CK_3505;
3369 } else if (cpu_is_omap34xx()) {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3370 cpu_mask = RATE_IN_343X;
Paul Walmsley2c8a1772010-01-26 20:12:56 -0700[diff] [blame]3371 cpu_clkflg |= CK_343X;
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3372
3373 /*
3374 * Update this if there are further clock changes between ES2
3375 * and production parts
3376 */
3377 if (omap_rev() == OMAP3430_REV_ES1_0) {
3378 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3379 cpu_clkflg |= CK_3430ES1;
3380 } else {
3381 cpu_mask |= RATE_IN_3430ES2;
3382 cpu_clkflg |= CK_3430ES2;
3383 }
3384 }
3385
Mike Turquettea7e069f2010-02-24 12:06:00 -0700[diff] [blame]3386 if (cpu_is_omap3630()) {
3387 /*
3388 * For 3630: override clkops_omap2_dflt_wait for the
3389 * clocks affected from PWRDN reset Limitation
3390 */
3391 dpll3_m3x2_ck.ops =
3392 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3393 dpll4_m2x2_ck.ops =
3394 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3395 dpll4_m3x2_ck.ops =
3396 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3397 dpll4_m4x2_ck.ops =
3398 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3399 dpll4_m5x2_ck.ops =
3400 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3401 dpll4_m6x2_ck.ops =
3402 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3403 }
3404
Richard Woodruff358965d2010-02-22 22:09:08 -0700[diff] [blame^]3405 if (cpu_is_omap3630())
3406 dpll4_dd = dpll4_dd_3630;
3407 else
3408 dpll4_dd = dpll4_dd_34xx;
3409
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3410 clk_init(&omap2_clk_functions);
3411
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3412 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++)
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3413 clk_preinit(c->lk.clk);
3414
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3415 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++)
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3416 if (c->cpu & cpu_clkflg) {
3417 clkdev_add(&c->lk);
3418 clk_register(c->lk.clk);
3419 omap2_init_clk_clkdm(c->lk.clk);
3420 }
3421
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3422 recalculate_root_clocks();
3423
3424 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
3425 "%ld.%01ld/%ld/%ld MHz\n",
3426 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3427 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3428
3429 /*
3430 * Only enable those clocks we will need, let the drivers
3431 * enable other clocks as necessary
3432 */
3433 clk_enable_init_clocks();
3434
3435 /*
3436 * Lock DPLL5 and put it in autoidle.
3437 */
3438 if (omap_rev() >= OMAP3430_REV_ES2_0)
3439 omap3_clk_lock_dpll5();
3440
3441 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3442 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3443 arm_fck_p = clk_get(NULL, "arm_fck");
3444
3445 return 0;
3446}