blob: 6ba197c107ed5cda043ce8f83f327480f96bafa5 [file] [log] [blame]
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#ifndef _QED_HSI_H
10#define _QED_HSI_H
11
12#include <linux/types.h>
13#include <linux/io.h>
14#include <linux/bitops.h>
15#include <linux/delay.h>
16#include <linux/kernel.h>
17#include <linux/list.h>
18#include <linux/slab.h>
19#include <linux/qed/common_hsi.h>
Yuval Mintz25c089d2015-10-26 11:02:26 +020020#include <linux/qed/eth_common.h>
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020021
22struct qed_hwfn;
23struct qed_ptt;
24/********************************/
25/* Add include to common target */
26/********************************/
27
28/* opcodes for the event ring */
29enum common_event_opcode {
30 COMMON_EVENT_PF_START,
31 COMMON_EVENT_PF_STOP,
32 COMMON_EVENT_RESERVED,
33 COMMON_EVENT_RESERVED2,
Yuval Mintz37bff2b2016-05-11 16:36:13 +030034 COMMON_EVENT_VF_PF_CHANNEL,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020035 COMMON_EVENT_RESERVED4,
36 COMMON_EVENT_RESERVED5,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -050037 COMMON_EVENT_RESERVED6,
38 COMMON_EVENT_EMPTY,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020039 MAX_COMMON_EVENT_OPCODE
40};
41
42/* Common Ramrod Command IDs */
43enum common_ramrod_cmd_id {
44 COMMON_RAMROD_UNUSED,
45 COMMON_RAMROD_PF_START /* PF Function Start Ramrod */,
46 COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */,
47 COMMON_RAMROD_RESERVED,
48 COMMON_RAMROD_RESERVED2,
Manish Chopra464f6642016-04-14 01:38:29 -040049 COMMON_RAMROD_PF_UPDATE,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -050050 COMMON_RAMROD_EMPTY,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020051 MAX_COMMON_RAMROD_CMD_ID
52};
53
54/* The core storm context for the Ystorm */
55struct ystorm_core_conn_st_ctx {
56 __le32 reserved[4];
57};
58
59/* The core storm context for the Pstorm */
60struct pstorm_core_conn_st_ctx {
61 __le32 reserved[4];
62};
63
64/* Core Slowpath Connection storm context of Xstorm */
65struct xstorm_core_conn_st_ctx {
66 __le32 spq_base_lo /* SPQ Ring Base Address low dword */;
67 __le32 spq_base_hi /* SPQ Ring Base Address high dword */;
68 struct regpair consolid_base_addr;
69 __le16 spq_cons /* SPQ Ring Consumer */;
70 __le16 consolid_cons /* Consolidation Ring Consumer */;
71 __le32 reserved0[55] /* Pad to 15 cycles */;
72};
73
74struct xstorm_core_conn_ag_ctx {
75 u8 reserved0 /* cdu_validation */;
76 u8 core_state /* state */;
77 u8 flags0;
78#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
79#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
80#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
81#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
82#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
83#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
84#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
85#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
86#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
87#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
88#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
89#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
90#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
91#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
92#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
93#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
94 u8 flags1;
95#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
96#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
97#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
98#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
99#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */
100#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
101#define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
102#define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
103#define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
104#define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
105#define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
106#define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
107#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */
108#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
109#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */
110#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
111 u8 flags2;
112#define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
113#define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
114#define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
115#define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
116#define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
117#define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
118#define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
119#define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
120 u8 flags3;
121#define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
122#define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
123#define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
124#define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
125#define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
126#define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
127#define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
128#define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
129 u8 flags4;
130#define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
131#define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
132#define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
133#define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
134#define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
135#define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
136#define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
137#define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
138 u8 flags5;
139#define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
140#define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
141#define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
142#define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
143#define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
144#define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
145#define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
146#define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
147 u8 flags6;
148#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 /* cf16 */
149#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
150#define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
151#define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
152#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */
153#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
154#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */
155#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
156 u8 flags7;
157#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
158#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
159#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */
160#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
161#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
162#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
163#define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
164#define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
165#define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
166#define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
167 u8 flags8;
168#define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
169#define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
170#define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
171#define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
172#define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
173#define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
174#define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
175#define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
176#define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
177#define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
178#define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
179#define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
180#define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
181#define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
182#define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
183#define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
184 u8 flags9;
185#define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
186#define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
187#define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
188#define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
189#define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
190#define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
191#define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
192#define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
193#define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
194#define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
195#define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
196#define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
197#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 /* cf16en */
198#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
199#define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
200#define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
201 u8 flags10;
202#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */
203#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
204#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */
205#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
206#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */
207#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
208#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */
209#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
210#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
211#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
212#define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
213#define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
214#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */
215#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
216#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */
217#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
218 u8 flags11;
219#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */
220#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
221#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */
222#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
223#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */
224#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
225#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
226#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
227#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
228#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
229#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
230#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
231#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
232#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
233#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
234#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
235 u8 flags12;
236#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
237#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
238#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
239#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
240#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
241#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
242#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
243#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
244#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
245#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
246#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
247#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
248#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
249#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
250#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
251#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
252 u8 flags13;
253#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
254#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
255#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
256#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
257#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
258#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
259#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
260#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
261#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
262#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
263#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
264#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
265#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
266#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
267#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
268#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
269 u8 flags14;
270#define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */
271#define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
272#define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
273#define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
274#define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */
275#define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
276#define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */
277#define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
278#define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */
279#define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
280#define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */
281#define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
282#define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
283#define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
284 u8 byte2 /* byte2 */;
285 __le16 physical_q0 /* physical_q0 */;
286 __le16 consolid_prod /* physical_q1 */;
287 __le16 reserved16 /* physical_q2 */;
288 __le16 tx_bd_cons /* word3 */;
289 __le16 tx_bd_or_spq_prod /* word4 */;
290 __le16 word5 /* word5 */;
291 __le16 conn_dpi /* conn_dpi */;
292 u8 byte3 /* byte3 */;
293 u8 byte4 /* byte4 */;
294 u8 byte5 /* byte5 */;
295 u8 byte6 /* byte6 */;
296 __le32 reg0 /* reg0 */;
297 __le32 reg1 /* reg1 */;
298 __le32 reg2 /* reg2 */;
299 __le32 reg3 /* reg3 */;
300 __le32 reg4 /* reg4 */;
301 __le32 reg5 /* cf_array0 */;
302 __le32 reg6 /* cf_array1 */;
303 __le16 word7 /* word7 */;
304 __le16 word8 /* word8 */;
305 __le16 word9 /* word9 */;
306 __le16 word10 /* word10 */;
307 __le32 reg7 /* reg7 */;
308 __le32 reg8 /* reg8 */;
309 __le32 reg9 /* reg9 */;
310 u8 byte7 /* byte7 */;
311 u8 byte8 /* byte8 */;
312 u8 byte9 /* byte9 */;
313 u8 byte10 /* byte10 */;
314 u8 byte11 /* byte11 */;
315 u8 byte12 /* byte12 */;
316 u8 byte13 /* byte13 */;
317 u8 byte14 /* byte14 */;
318 u8 byte15 /* byte15 */;
319 u8 byte16 /* byte16 */;
320 __le16 word11 /* word11 */;
321 __le32 reg10 /* reg10 */;
322 __le32 reg11 /* reg11 */;
323 __le32 reg12 /* reg12 */;
324 __le32 reg13 /* reg13 */;
325 __le32 reg14 /* reg14 */;
326 __le32 reg15 /* reg15 */;
327 __le32 reg16 /* reg16 */;
328 __le32 reg17 /* reg17 */;
329 __le32 reg18 /* reg18 */;
330 __le32 reg19 /* reg19 */;
331 __le16 word12 /* word12 */;
332 __le16 word13 /* word13 */;
333 __le16 word14 /* word14 */;
334 __le16 word15 /* word15 */;
335};
336
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500337struct tstorm_core_conn_ag_ctx {
338 u8 byte0 /* cdu_validation */;
339 u8 byte1 /* state */;
340 u8 flags0;
341#define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
342#define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
343#define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
344#define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
345#define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
346#define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
347#define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
348#define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
349#define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
350#define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
351#define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
352#define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
353#define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
354#define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
355 u8 flags1;
356#define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
357#define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
358#define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
359#define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
360#define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
361#define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
362#define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
363#define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
364 u8 flags2;
365#define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
366#define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
367#define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
368#define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
369#define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
370#define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
371#define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
372#define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
373 u8 flags3;
374#define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
375#define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
376#define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
377#define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
378#define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
379#define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
380#define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
381#define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
382#define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
383#define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
384#define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
385#define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
386 u8 flags4;
387#define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
388#define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
389#define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
390#define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
391#define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
392#define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
393#define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
394#define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
395#define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
396#define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
397#define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
398#define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
399#define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
400#define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
401#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
402#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
403 u8 flags5;
404#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
405#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
406#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
407#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
408#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
409#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
410#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
411#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
412#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
413#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
414#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
415#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
416#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
417#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
418#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
419#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
420 __le32 reg0 /* reg0 */;
421 __le32 reg1 /* reg1 */;
422 __le32 reg2 /* reg2 */;
423 __le32 reg3 /* reg3 */;
424 __le32 reg4 /* reg4 */;
425 __le32 reg5 /* reg5 */;
426 __le32 reg6 /* reg6 */;
427 __le32 reg7 /* reg7 */;
428 __le32 reg8 /* reg8 */;
429 u8 byte2 /* byte2 */;
430 u8 byte3 /* byte3 */;
431 __le16 word0 /* word0 */;
432 u8 byte4 /* byte4 */;
433 u8 byte5 /* byte5 */;
434 __le16 word1 /* word1 */;
435 __le16 word2 /* conn_dpi */;
436 __le16 word3 /* word3 */;
437 __le32 reg9 /* reg9 */;
438 __le32 reg10 /* reg10 */;
439};
440
441struct ustorm_core_conn_ag_ctx {
442 u8 reserved /* cdu_validation */;
443 u8 byte1 /* state */;
444 u8 flags0;
445#define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
446#define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
447#define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
448#define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
449#define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
450#define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
451#define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
452#define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
453#define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
454#define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
455 u8 flags1;
456#define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
457#define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
458#define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
459#define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
460#define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
461#define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
462#define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
463#define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
464 u8 flags2;
465#define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
466#define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
467#define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
468#define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
469#define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
470#define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
471#define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
472#define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
473#define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
474#define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
475#define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
476#define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
477#define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
478#define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
479#define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
480#define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
481 u8 flags3;
482#define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
483#define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
484#define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
485#define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
486#define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
487#define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
488#define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
489#define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
490#define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
491#define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
492#define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
493#define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
494#define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
495#define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
496#define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
497#define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
498 u8 byte2 /* byte2 */;
499 u8 byte3 /* byte3 */;
500 __le16 word0 /* conn_dpi */;
501 __le16 word1 /* word1 */;
502 __le32 rx_producers /* reg0 */;
503 __le32 reg1 /* reg1 */;
504 __le32 reg2 /* reg2 */;
505 __le32 reg3 /* reg3 */;
506 __le16 word2 /* word2 */;
507 __le16 word3 /* word3 */;
508};
509
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200510/* The core storm context for the Mstorm */
511struct mstorm_core_conn_st_ctx {
512 __le32 reserved[24];
513};
514
515/* The core storm context for the Ustorm */
516struct ustorm_core_conn_st_ctx {
517 __le32 reserved[4];
518};
519
520/* core connection context */
521struct core_conn_context {
522 struct ystorm_core_conn_st_ctx ystorm_st_context;
523 struct regpair ystorm_st_padding[2] /* padding */;
524 struct pstorm_core_conn_st_ctx pstorm_st_context;
525 struct regpair pstorm_st_padding[2];
526 struct xstorm_core_conn_st_ctx xstorm_st_context;
527 struct xstorm_core_conn_ag_ctx xstorm_ag_context;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500528 struct tstorm_core_conn_ag_ctx tstorm_ag_context;
529 struct ustorm_core_conn_ag_ctx ustorm_ag_context;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200530 struct mstorm_core_conn_st_ctx mstorm_st_context;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200531 struct ustorm_core_conn_st_ctx ustorm_st_context;
532 struct regpair ustorm_st_padding[2] /* padding */;
533};
534
Manish Chopra9df2ed02015-10-26 11:02:33 +0200535struct eth_mstorm_per_queue_stat {
536 struct regpair ttl0_discard;
537 struct regpair packet_too_big_discard;
538 struct regpair no_buff_discard;
539 struct regpair not_active_discard;
540 struct regpair tpa_coalesced_pkts;
541 struct regpair tpa_coalesced_events;
542 struct regpair tpa_aborts_num;
543 struct regpair tpa_coalesced_bytes;
544};
545
546struct eth_pstorm_per_queue_stat {
547 struct regpair sent_ucast_bytes;
548 struct regpair sent_mcast_bytes;
549 struct regpair sent_bcast_bytes;
550 struct regpair sent_ucast_pkts;
551 struct regpair sent_mcast_pkts;
552 struct regpair sent_bcast_pkts;
553 struct regpair error_drop_pkts;
554};
555
556struct eth_ustorm_per_queue_stat {
557 struct regpair rcv_ucast_bytes;
558 struct regpair rcv_mcast_bytes;
559 struct regpair rcv_bcast_bytes;
560 struct regpair rcv_ucast_pkts;
561 struct regpair rcv_mcast_pkts;
562 struct regpair rcv_bcast_pkts;
563};
564
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200565/* Event Ring Next Page Address */
566struct event_ring_next_addr {
567 struct regpair addr /* Next Page Address */;
568 __le32 reserved[2] /* Reserved */;
569};
570
571union event_ring_element {
572 struct event_ring_entry entry /* Event Ring Entry */;
573 struct event_ring_next_addr next_addr;
574};
575
576enum personality_type {
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500577 BAD_PERSONALITY_TYP,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200578 PERSONALITY_RESERVED,
579 PERSONALITY_RESERVED2,
580 PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp */,
581 PERSONALITY_RESERVED3,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500582 PERSONALITY_CORE,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200583 PERSONALITY_ETH /* Ethernet */,
584 PERSONALITY_RESERVED4,
585 MAX_PERSONALITY_TYPE
586};
587
588struct pf_start_tunnel_config {
589 u8 set_vxlan_udp_port_flg;
590 u8 set_geneve_udp_port_flg;
591 u8 tx_enable_vxlan /* If set, enable VXLAN tunnel in TX path. */;
592 u8 tx_enable_l2geneve;
593 u8 tx_enable_ipgeneve;
594 u8 tx_enable_l2gre /* If set, enable l2 GRE tunnel in TX path. */;
595 u8 tx_enable_ipgre /* If set, enable IP GRE tunnel in TX path. */;
596 u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;
597 u8 tunnel_clss_l2geneve;
598 u8 tunnel_clss_ipgeneve;
599 u8 tunnel_clss_l2gre;
600 u8 tunnel_clss_ipgre;
601 __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
602 __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */;
603};
604
605/* Ramrod data for PF start ramrod */
606struct pf_start_ramrod_data {
607 struct regpair event_ring_pbl_addr;
608 struct regpair consolid_q_pbl_addr;
609 struct pf_start_tunnel_config tunnel_config;
610 __le16 event_ring_sb_id;
611 u8 base_vf_id;
612 u8 num_vfs;
613 u8 event_ring_num_pages;
614 u8 event_ring_sb_index;
615 u8 path_id;
616 u8 warning_as_error;
617 u8 dont_log_ramrods;
618 u8 personality;
619 __le16 log_type_mask;
620 u8 mf_mode /* Multi function mode */;
621 u8 integ_phase /* Integration phase */;
622 u8 allow_npar_tx_switching;
623 u8 inner_to_outer_pri_map[8];
624 u8 pri_map_valid;
625 u32 outer_tag;
626 u8 reserved0[4];
627};
628
Manish Chopra464f6642016-04-14 01:38:29 -0400629/* tunnel configuration */
630struct pf_update_tunnel_config {
631 u8 update_rx_pf_clss;
632 u8 update_tx_pf_clss;
633 u8 set_vxlan_udp_port_flg;
634 u8 set_geneve_udp_port_flg;
635 u8 tx_enable_vxlan;
636 u8 tx_enable_l2geneve;
637 u8 tx_enable_ipgeneve;
638 u8 tx_enable_l2gre;
639 u8 tx_enable_ipgre;
640 u8 tunnel_clss_vxlan;
641 u8 tunnel_clss_l2geneve;
642 u8 tunnel_clss_ipgeneve;
643 u8 tunnel_clss_l2gre;
644 u8 tunnel_clss_ipgre;
645 __le16 vxlan_udp_port;
646 __le16 geneve_udp_port;
647 __le16 reserved[3];
648};
649
650struct pf_update_ramrod_data {
651 u32 reserved[2];
652 u32 reserved_1[6];
653 struct pf_update_tunnel_config tunnel_config;
654};
655
656/* Tunnel classification scheme */
657enum tunnel_clss {
658 TUNNEL_CLSS_MAC_VLAN = 0,
659 TUNNEL_CLSS_MAC_VNI,
660 TUNNEL_CLSS_INNER_MAC_VLAN,
661 TUNNEL_CLSS_INNER_MAC_VNI,
662 MAX_TUNNEL_CLSS
663};
664
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200665enum ports_mode {
666 ENGX2_PORTX1 /* 2 engines x 1 port */,
667 ENGX2_PORTX2 /* 2 engines x 2 ports */,
668 ENGX1_PORTX1 /* 1 engine x 1 port */,
669 ENGX1_PORTX2 /* 1 engine x 2 ports */,
670 ENGX1_PORTX4 /* 1 engine x 4 ports */,
671 MAX_PORTS_MODE
672};
673
674/* Ramrod Header of SPQE */
675struct ramrod_header {
676 __le32 cid /* Slowpath Connection CID */;
677 u8 cmd_id /* Ramrod Cmd (Per Protocol Type) */;
678 u8 protocol_id /* Ramrod Protocol ID */;
679 __le16 echo /* Ramrod echo */;
680};
681
682/* Slowpath Element (SPQE) */
683struct slow_path_element {
684 struct ramrod_header hdr /* Ramrod Header */;
685 struct regpair data_ptr;
686};
687
688struct tstorm_per_port_stat {
689 struct regpair trunc_error_discard;
690 struct regpair mac_error_discard;
691 struct regpair mftag_filter_discard;
692 struct regpair eth_mac_filter_discard;
693 struct regpair ll2_mac_filter_discard;
694 struct regpair ll2_conn_disabled_discard;
695 struct regpair iscsi_irregular_pkt;
696 struct regpair fcoe_irregular_pkt;
697 struct regpair roce_irregular_pkt;
698 struct regpair eth_irregular_pkt;
699 struct regpair toe_irregular_pkt;
700 struct regpair preroce_irregular_pkt;
701};
702
703struct atten_status_block {
704 __le32 atten_bits;
705 __le32 atten_ack;
706 __le16 reserved0;
707 __le16 sb_index /* status block running index */;
708 __le32 reserved1;
709};
710
711enum block_addr {
712 GRCBASE_GRC = 0x50000,
713 GRCBASE_MISCS = 0x9000,
714 GRCBASE_MISC = 0x8000,
715 GRCBASE_DBU = 0xa000,
716 GRCBASE_PGLUE_B = 0x2a8000,
717 GRCBASE_CNIG = 0x218000,
718 GRCBASE_CPMU = 0x30000,
719 GRCBASE_NCSI = 0x40000,
720 GRCBASE_OPTE = 0x53000,
721 GRCBASE_BMB = 0x540000,
722 GRCBASE_PCIE = 0x54000,
723 GRCBASE_MCP = 0xe00000,
724 GRCBASE_MCP2 = 0x52000,
725 GRCBASE_PSWHST = 0x2a0000,
726 GRCBASE_PSWHST2 = 0x29e000,
727 GRCBASE_PSWRD = 0x29c000,
728 GRCBASE_PSWRD2 = 0x29d000,
729 GRCBASE_PSWWR = 0x29a000,
730 GRCBASE_PSWWR2 = 0x29b000,
731 GRCBASE_PSWRQ = 0x280000,
732 GRCBASE_PSWRQ2 = 0x240000,
733 GRCBASE_PGLCS = 0x0,
734 GRCBASE_PTU = 0x560000,
735 GRCBASE_DMAE = 0xc000,
736 GRCBASE_TCM = 0x1180000,
737 GRCBASE_MCM = 0x1200000,
738 GRCBASE_UCM = 0x1280000,
739 GRCBASE_XCM = 0x1000000,
740 GRCBASE_YCM = 0x1080000,
741 GRCBASE_PCM = 0x1100000,
742 GRCBASE_QM = 0x2f0000,
743 GRCBASE_TM = 0x2c0000,
744 GRCBASE_DORQ = 0x100000,
745 GRCBASE_BRB = 0x340000,
746 GRCBASE_SRC = 0x238000,
747 GRCBASE_PRS = 0x1f0000,
748 GRCBASE_TSDM = 0xfb0000,
749 GRCBASE_MSDM = 0xfc0000,
750 GRCBASE_USDM = 0xfd0000,
751 GRCBASE_XSDM = 0xf80000,
752 GRCBASE_YSDM = 0xf90000,
753 GRCBASE_PSDM = 0xfa0000,
754 GRCBASE_TSEM = 0x1700000,
755 GRCBASE_MSEM = 0x1800000,
756 GRCBASE_USEM = 0x1900000,
757 GRCBASE_XSEM = 0x1400000,
758 GRCBASE_YSEM = 0x1500000,
759 GRCBASE_PSEM = 0x1600000,
760 GRCBASE_RSS = 0x238800,
761 GRCBASE_TMLD = 0x4d0000,
762 GRCBASE_MULD = 0x4e0000,
763 GRCBASE_YULD = 0x4c8000,
764 GRCBASE_XYLD = 0x4c0000,
765 GRCBASE_PRM = 0x230000,
766 GRCBASE_PBF_PB1 = 0xda0000,
767 GRCBASE_PBF_PB2 = 0xda4000,
768 GRCBASE_RPB = 0x23c000,
769 GRCBASE_BTB = 0xdb0000,
770 GRCBASE_PBF = 0xd80000,
771 GRCBASE_RDIF = 0x300000,
772 GRCBASE_TDIF = 0x310000,
773 GRCBASE_CDU = 0x580000,
774 GRCBASE_CCFC = 0x2e0000,
775 GRCBASE_TCFC = 0x2d0000,
776 GRCBASE_IGU = 0x180000,
777 GRCBASE_CAU = 0x1c0000,
778 GRCBASE_UMAC = 0x51000,
779 GRCBASE_XMAC = 0x210000,
780 GRCBASE_DBG = 0x10000,
781 GRCBASE_NIG = 0x500000,
782 GRCBASE_WOL = 0x600000,
783 GRCBASE_BMBN = 0x610000,
784 GRCBASE_IPC = 0x20000,
785 GRCBASE_NWM = 0x800000,
786 GRCBASE_NWS = 0x700000,
787 GRCBASE_MS = 0x6a0000,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500788 GRCBASE_PHY_PCIE = 0x620000,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200789 GRCBASE_MISC_AEU = 0x8000,
790 GRCBASE_BAR0_MAP = 0x1c00000,
791 MAX_BLOCK_ADDR
792};
793
794enum block_id {
795 BLOCK_GRC,
796 BLOCK_MISCS,
797 BLOCK_MISC,
798 BLOCK_DBU,
799 BLOCK_PGLUE_B,
800 BLOCK_CNIG,
801 BLOCK_CPMU,
802 BLOCK_NCSI,
803 BLOCK_OPTE,
804 BLOCK_BMB,
805 BLOCK_PCIE,
806 BLOCK_MCP,
807 BLOCK_MCP2,
808 BLOCK_PSWHST,
809 BLOCK_PSWHST2,
810 BLOCK_PSWRD,
811 BLOCK_PSWRD2,
812 BLOCK_PSWWR,
813 BLOCK_PSWWR2,
814 BLOCK_PSWRQ,
815 BLOCK_PSWRQ2,
816 BLOCK_PGLCS,
817 BLOCK_PTU,
818 BLOCK_DMAE,
819 BLOCK_TCM,
820 BLOCK_MCM,
821 BLOCK_UCM,
822 BLOCK_XCM,
823 BLOCK_YCM,
824 BLOCK_PCM,
825 BLOCK_QM,
826 BLOCK_TM,
827 BLOCK_DORQ,
828 BLOCK_BRB,
829 BLOCK_SRC,
830 BLOCK_PRS,
831 BLOCK_TSDM,
832 BLOCK_MSDM,
833 BLOCK_USDM,
834 BLOCK_XSDM,
835 BLOCK_YSDM,
836 BLOCK_PSDM,
837 BLOCK_TSEM,
838 BLOCK_MSEM,
839 BLOCK_USEM,
840 BLOCK_XSEM,
841 BLOCK_YSEM,
842 BLOCK_PSEM,
843 BLOCK_RSS,
844 BLOCK_TMLD,
845 BLOCK_MULD,
846 BLOCK_YULD,
847 BLOCK_XYLD,
848 BLOCK_PRM,
849 BLOCK_PBF_PB1,
850 BLOCK_PBF_PB2,
851 BLOCK_RPB,
852 BLOCK_BTB,
853 BLOCK_PBF,
854 BLOCK_RDIF,
855 BLOCK_TDIF,
856 BLOCK_CDU,
857 BLOCK_CCFC,
858 BLOCK_TCFC,
859 BLOCK_IGU,
860 BLOCK_CAU,
861 BLOCK_UMAC,
862 BLOCK_XMAC,
863 BLOCK_DBG,
864 BLOCK_NIG,
865 BLOCK_WOL,
866 BLOCK_BMBN,
867 BLOCK_IPC,
868 BLOCK_NWM,
869 BLOCK_NWS,
870 BLOCK_MS,
871 BLOCK_PHY_PCIE,
872 BLOCK_MISC_AEU,
873 BLOCK_BAR0_MAP,
874 MAX_BLOCK_ID
875};
876
877enum command_type_bit {
878 IGU_COMMAND_TYPE_NOP = 0,
879 IGU_COMMAND_TYPE_SET = 1,
880 MAX_COMMAND_TYPE_BIT
881};
882
883struct dmae_cmd {
884 __le32 opcode;
885#define DMAE_CMD_SRC_MASK 0x1
886#define DMAE_CMD_SRC_SHIFT 0
887#define DMAE_CMD_DST_MASK 0x3
888#define DMAE_CMD_DST_SHIFT 1
889#define DMAE_CMD_C_DST_MASK 0x1
890#define DMAE_CMD_C_DST_SHIFT 3
891#define DMAE_CMD_CRC_RESET_MASK 0x1
892#define DMAE_CMD_CRC_RESET_SHIFT 4
893#define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
894#define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
895#define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
896#define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
897#define DMAE_CMD_COMP_FUNC_MASK 0x1
898#define DMAE_CMD_COMP_FUNC_SHIFT 7
899#define DMAE_CMD_COMP_WORD_EN_MASK 0x1
900#define DMAE_CMD_COMP_WORD_EN_SHIFT 8
901#define DMAE_CMD_COMP_CRC_EN_MASK 0x1
902#define DMAE_CMD_COMP_CRC_EN_SHIFT 9
903#define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
904#define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
905#define DMAE_CMD_RESERVED1_MASK 0x1
906#define DMAE_CMD_RESERVED1_SHIFT 13
907#define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
908#define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
909#define DMAE_CMD_ERR_HANDLING_MASK 0x3
910#define DMAE_CMD_ERR_HANDLING_SHIFT 16
911#define DMAE_CMD_PORT_ID_MASK 0x3
912#define DMAE_CMD_PORT_ID_SHIFT 18
913#define DMAE_CMD_SRC_PF_ID_MASK 0xF
914#define DMAE_CMD_SRC_PF_ID_SHIFT 20
915#define DMAE_CMD_DST_PF_ID_MASK 0xF
916#define DMAE_CMD_DST_PF_ID_SHIFT 24
917#define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
918#define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
919#define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
920#define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
921#define DMAE_CMD_RESERVED2_MASK 0x3
922#define DMAE_CMD_RESERVED2_SHIFT 30
923 __le32 src_addr_lo;
924 __le32 src_addr_hi;
925 __le32 dst_addr_lo;
926 __le32 dst_addr_hi;
927 __le16 length /* Length in DW */;
928 __le16 opcode_b;
929#define DMAE_CMD_SRC_VF_ID_MASK 0xFF /* Source VF id */
930#define DMAE_CMD_SRC_VF_ID_SHIFT 0
931#define DMAE_CMD_DST_VF_ID_MASK 0xFF /* Destination VF id */
932#define DMAE_CMD_DST_VF_ID_SHIFT 8
933 __le32 comp_addr_lo /* PCIe completion address low or grc address */;
934 __le32 comp_addr_hi;
935 __le32 comp_val /* Value to write to copmletion address */;
936 __le32 crc32 /* crc16 result */;
937 __le32 crc_32_c /* crc32_c result */;
938 __le16 crc16 /* crc16 result */;
939 __le16 crc16_c /* crc16_c result */;
940 __le16 crc10 /* crc_t10 result */;
941 __le16 reserved;
942 __le16 xsum16 /* checksum16 result */;
943 __le16 xsum8 /* checksum8 result */;
944};
945
946struct igu_cleanup {
947 __le32 sb_id_and_flags;
948#define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
949#define IGU_CLEANUP_RESERVED0_SHIFT 0
950#define IGU_CLEANUP_CLEANUP_SET_MASK 0x1 /* cleanup clear - 0, set - 1 */
951#define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
952#define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
953#define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
954#define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
955#define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
956 __le32 reserved1;
957};
958
959union igu_command {
960 struct igu_prod_cons_update prod_cons_update;
961 struct igu_cleanup cleanup;
962};
963
964struct igu_command_reg_ctrl {
965 __le16 opaque_fid;
966 __le16 igu_command_reg_ctrl_fields;
967#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
968#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
969#define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
970#define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
971#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
972#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
973};
974
975struct igu_mapping_line {
976 __le32 igu_mapping_line_fields;
977#define IGU_MAPPING_LINE_VALID_MASK 0x1
978#define IGU_MAPPING_LINE_VALID_SHIFT 0
979#define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
980#define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
981#define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
982#define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
983#define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 /* PF-1, VF-0 */
984#define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
985#define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
986#define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
987#define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
988#define IGU_MAPPING_LINE_RESERVED_SHIFT 24
989};
990
991struct igu_msix_vector {
992 struct regpair address;
993 __le32 data;
994 __le32 msix_vector_fields;
995#define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
996#define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
997#define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
998#define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
999#define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
1000#define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
1001#define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
1002#define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
1003};
1004
1005enum init_modes {
1006 MODE_BB_A0,
Yuval Mintz12e09c62016-03-02 20:26:01 +02001007 MODE_BB_B0,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001008 MODE_RESERVED2,
1009 MODE_ASIC,
1010 MODE_RESERVED3,
1011 MODE_RESERVED4,
1012 MODE_RESERVED5,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001013 MODE_RESERVED6,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001014 MODE_SF,
1015 MODE_MF_SD,
1016 MODE_MF_SI,
1017 MODE_PORTS_PER_ENG_1,
1018 MODE_PORTS_PER_ENG_2,
1019 MODE_PORTS_PER_ENG_4,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001020 MODE_100G,
1021 MODE_EAGLE_ENG1_WORKAROUND,
1022 MAX_INIT_MODES
1023};
1024
1025enum init_phases {
1026 PHASE_ENGINE,
1027 PHASE_PORT,
1028 PHASE_PF,
1029 PHASE_RESERVED,
1030 PHASE_QM_PF,
1031 MAX_INIT_PHASES
1032};
1033
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001034/* per encapsulation type enabling flags */
1035struct prs_reg_encapsulation_type_en {
1036 u8 flags;
1037#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1038#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1039#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1040#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
1041#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1042#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
1043#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1044#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
1045#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1046#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
1047#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1048#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
1049#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1050#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
1051};
1052
1053enum pxp_tph_st_hint {
1054 TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */,
1055 TPH_ST_HINT_REQUESTER /* Read/Write access by Device */,
1056 TPH_ST_HINT_TARGET,
1057 TPH_ST_HINT_TARGET_PRIO,
1058 MAX_PXP_TPH_ST_HINT
1059};
1060
1061/* QM hardware structure of enable bypass credit mask */
1062struct qm_rf_bypass_mask {
1063 u8 flags;
1064#define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1065#define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1066#define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1067#define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
1068#define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1069#define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
1070#define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1071#define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
1072#define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1073#define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
1074#define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1075#define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
1076#define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1077#define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
1078#define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1079#define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
1080};
1081
1082/* QM hardware structure of opportunistic credit mask */
1083struct qm_rf_opportunistic_mask {
1084 __le16 flags;
1085#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1086#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1087#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1088#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
1089#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1090#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
1091#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1092#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
1093#define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1094#define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
1095#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1096#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
1097#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1098#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
1099#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1100#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
1101#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1102#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
1103#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1104#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
1105};
1106
1107/* QM hardware structure of QM map memory */
1108struct qm_rf_pq_map {
1109 u32 reg;
1110#define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1 /* PQ active */
1111#define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
1112#define QM_RF_PQ_MAP_RL_ID_MASK 0xFF /* RL ID */
1113#define QM_RF_PQ_MAP_RL_ID_SHIFT 1
1114#define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
1115#define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
1116#define QM_RF_PQ_MAP_VOQ_MASK 0x1F /* VOQ */
1117#define QM_RF_PQ_MAP_VOQ_SHIFT 18
1118#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */
1119#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
1120#define QM_RF_PQ_MAP_RL_VALID_MASK 0x1 /* RL active */
1121#define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
1122#define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
1123#define QM_RF_PQ_MAP_RESERVED_SHIFT 26
1124};
1125
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001126/* Completion params for aggregated interrupt completion */
1127struct sdm_agg_int_comp_params {
1128 __le16 params;
1129#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1130#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1131#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1132#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1133#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1134#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
1135};
1136
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001137/* SDM operation gen command (generate aggregative interrupt) */
1138struct sdm_op_gen {
1139 __le32 command;
1140#define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF /* completion parameters 0-15 */
1141#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1142#define SDM_OP_GEN_COMP_TYPE_MASK 0xF /* completion type 16-19 */
1143#define SDM_OP_GEN_COMP_TYPE_SHIFT 16
1144#define SDM_OP_GEN_RESERVED_MASK 0xFFF /* reserved 20-31 */
1145#define SDM_OP_GEN_RESERVED_SHIFT 20
1146};
1147
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001148/*********************************** Init ************************************/
1149
1150/* Width of GRC address in bits (addresses are specified in dwords) */
1151#define GRC_ADDR_BITS 23
1152#define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
1153
1154/* indicates an init that should be applied to any phase ID */
1155#define ANY_PHASE_ID 0xffff
1156
1157/* init pattern size in bytes */
1158#define INIT_PATTERN_SIZE_BITS 4
1159#define MAX_INIT_PATTERN_SIZE BIT(INIT_PATTERN_SIZE_BITS)
1160
1161/* Max size in dwords of a zipped array */
1162#define MAX_ZIPPED_SIZE 8192
1163
1164/* Global PXP window */
1165#define NUM_OF_PXP_WIN 19
1166#define PXP_WIN_DWORD_SIZE_BITS 10
1167#define PXP_WIN_DWORD_SIZE BIT(PXP_WIN_DWORD_SIZE_BITS)
1168#define PXP_WIN_BYTE_SIZE_BITS (PXP_WIN_DWORD_SIZE_BITS + 2)
1169#define PXP_WIN_BYTE_SIZE (PXP_WIN_DWORD_SIZE * 4)
1170
1171/********************************* GRC Dump **********************************/
1172
1173/* width of GRC dump register sequence length in bits */
1174#define DUMP_SEQ_LEN_BITS 8
1175#define DUMP_SEQ_LEN_MAX_VAL ((1 << DUMP_SEQ_LEN_BITS) - 1)
1176
1177/* width of GRC dump memory length in bits */
1178#define DUMP_MEM_LEN_BITS 18
1179#define DUMP_MEM_LEN_MAX_VAL ((1 << DUMP_MEM_LEN_BITS) - 1)
1180
1181/* width of register type ID in bits */
1182#define REG_TYPE_ID_BITS 6
1183#define REG_TYPE_ID_MAX_VAL ((1 << REG_TYPE_ID_BITS) - 1)
1184
1185/* width of block ID in bits */
1186#define BLOCK_ID_BITS 8
1187#define BLOCK_ID_MAX_VAL ((1 << BLOCK_ID_BITS) - 1)
1188
1189/******************************** Idle Check *********************************/
1190
1191/* max number of idle check predicate immediates */
1192#define MAX_IDLE_CHK_PRED_IMM 3
1193
1194/* max number of idle check argument registers */
1195#define MAX_IDLE_CHK_READ_REGS 3
1196
1197/* max number of idle check loops */
1198#define MAX_IDLE_CHK_LOOPS 0x10000
1199
1200/* max idle check address increment */
1201#define MAX_IDLE_CHK_INCREMENT 0x10000
1202
1203/* inicates an undefined idle check line index */
1204#define IDLE_CHK_UNDEFINED_LINE_IDX 0xffffff
1205
1206/* max number of register values following the idle check header */
1207#define IDLE_CHK_MAX_DUMP_REGS 2
1208
1209/* arguments for IDLE_CHK_MACRO_TYPE_QM_RD_WR */
1210#define IDLE_CHK_QM_RD_WR_PTR 0
1211#define IDLE_CHK_QM_RD_WR_BANK 1
1212
1213/**************************************/
1214/* HSI Functions constants and macros */
1215/**************************************/
1216
1217/* Number of VLAN priorities */
1218#define NUM_OF_VLAN_PRIORITIES 8
1219
1220/* the MCP Trace meta data signautre is duplicated in the perl script that
1221 * generats the NVRAM images.
1222 */
1223#define MCP_TRACE_META_IMAGE_SIGNATURE 0x669955aa
1224
1225/* Binary buffer header */
1226struct bin_buffer_hdr {
1227 u32 offset;
1228 u32 length /* buffer length in bytes */;
1229};
1230
1231/* binary buffer types */
1232enum bin_buffer_type {
1233 BIN_BUF_FW_VER_INFO /* fw_ver_info struct */,
1234 BIN_BUF_INIT_CMD /* init commands */,
1235 BIN_BUF_INIT_VAL /* init data */,
1236 BIN_BUF_INIT_MODE_TREE /* init modes tree */,
1237 BIN_BUF_IRO /* internal RAM offsets array */,
1238 MAX_BIN_BUFFER_TYPE
1239};
1240
1241/* Chip IDs */
1242enum chip_ids {
1243 CHIP_BB_A0 /* BB A0 chip ID */,
1244 CHIP_BB_B0 /* BB B0 chip ID */,
1245 CHIP_K2 /* AH chip ID */,
1246 MAX_CHIP_IDS
1247};
1248
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001249struct init_array_raw_hdr {
1250 __le32 data;
1251#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
1252#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
1253#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */
1254#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
1255};
1256
1257struct init_array_standard_hdr {
1258 __le32 data;
1259#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
1260#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
1261#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
1262#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
1263};
1264
1265struct init_array_zipped_hdr {
1266 __le32 data;
1267#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
1268#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
1269#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
1270#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
1271};
1272
1273struct init_array_pattern_hdr {
1274 __le32 data;
1275#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
1276#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
1277#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
1278#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
1279#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
1280#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
1281};
1282
1283union init_array_hdr {
1284 struct init_array_raw_hdr raw /* raw init array header */;
1285 struct init_array_standard_hdr standard;
1286 struct init_array_zipped_hdr zipped /* zipped init array header */;
1287 struct init_array_pattern_hdr pattern /* pattern init array header */;
1288};
1289
1290enum init_array_types {
1291 INIT_ARR_STANDARD /* standard init array */,
1292 INIT_ARR_ZIPPED /* zipped init array */,
1293 INIT_ARR_PATTERN /* a repeated pattern */,
1294 MAX_INIT_ARRAY_TYPES
1295};
1296
1297/* init operation: callback */
1298struct init_callback_op {
1299 __le32 op_data;
1300#define INIT_CALLBACK_OP_OP_MASK 0xF
1301#define INIT_CALLBACK_OP_OP_SHIFT 0
1302#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
1303#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
1304 __le16 callback_id /* Callback ID */;
1305 __le16 block_id /* Blocks ID */;
1306};
1307
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001308/* init operation: delay */
1309struct init_delay_op {
1310 __le32 op_data;
1311#define INIT_DELAY_OP_OP_MASK 0xF
1312#define INIT_DELAY_OP_OP_SHIFT 0
1313#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
1314#define INIT_DELAY_OP_RESERVED_SHIFT 4
1315 __le32 delay /* delay in us */;
1316};
1317
1318/* init operation: if_mode */
1319struct init_if_mode_op {
1320 __le32 op_data;
1321#define INIT_IF_MODE_OP_OP_MASK 0xF
1322#define INIT_IF_MODE_OP_OP_SHIFT 0
1323#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
1324#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
1325#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
1326#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
1327 __le16 reserved2;
1328 __le16 modes_buf_offset;
1329};
1330
1331/* init operation: if_phase */
1332struct init_if_phase_op {
1333 __le32 op_data;
1334#define INIT_IF_PHASE_OP_OP_MASK 0xF
1335#define INIT_IF_PHASE_OP_OP_SHIFT 0
1336#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
1337#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
1338#define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
1339#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
1340#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
1341#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
1342 __le32 phase_data;
1343#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */
1344#define INIT_IF_PHASE_OP_PHASE_SHIFT 0
1345#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
1346#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
1347#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */
1348#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
1349};
1350
1351/* init mode operators */
1352enum init_mode_ops {
1353 INIT_MODE_OP_NOT /* init mode not operator */,
1354 INIT_MODE_OP_OR /* init mode or operator */,
1355 INIT_MODE_OP_AND /* init mode and operator */,
1356 MAX_INIT_MODE_OPS
1357};
1358
1359/* init operation: raw */
1360struct init_raw_op {
1361 __le32 op_data;
1362#define INIT_RAW_OP_OP_MASK 0xF
1363#define INIT_RAW_OP_OP_SHIFT 0
1364#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */
1365#define INIT_RAW_OP_PARAM1_SHIFT 4
1366 __le32 param2 /* Init param 2 */;
1367};
1368
1369/* init array params */
1370struct init_op_array_params {
1371 __le16 size /* array size in dwords */;
1372 __le16 offset /* array start offset in dwords */;
1373};
1374
1375/* Write init operation arguments */
1376union init_write_args {
1377 __le32 inline_val;
1378 __le32 zeros_count;
1379 __le32 array_offset;
1380 struct init_op_array_params runtime;
1381};
1382
1383/* init operation: write */
1384struct init_write_op {
1385 __le32 data;
1386#define INIT_WRITE_OP_OP_MASK 0xF
1387#define INIT_WRITE_OP_OP_SHIFT 0
1388#define INIT_WRITE_OP_SOURCE_MASK 0x7
1389#define INIT_WRITE_OP_SOURCE_SHIFT 4
1390#define INIT_WRITE_OP_RESERVED_MASK 0x1
1391#define INIT_WRITE_OP_RESERVED_SHIFT 7
1392#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
1393#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
1394#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
1395#define INIT_WRITE_OP_ADDRESS_SHIFT 9
1396 union init_write_args args /* Write init operation arguments */;
1397};
1398
1399/* init operation: read */
1400struct init_read_op {
1401 __le32 op_data;
1402#define INIT_READ_OP_OP_MASK 0xF
1403#define INIT_READ_OP_OP_SHIFT 0
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001404#define INIT_READ_OP_POLL_TYPE_MASK 0xF
1405#define INIT_READ_OP_POLL_TYPE_SHIFT 4
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001406#define INIT_READ_OP_RESERVED_MASK 0x1
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001407#define INIT_READ_OP_RESERVED_SHIFT 8
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001408#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
1409#define INIT_READ_OP_ADDRESS_SHIFT 9
1410 __le32 expected_val;
1411};
1412
1413/* Init operations union */
1414union init_op {
1415 struct init_raw_op raw /* raw init operation */;
1416 struct init_write_op write /* write init operation */;
1417 struct init_read_op read /* read init operation */;
1418 struct init_if_mode_op if_mode /* if_mode init operation */;
1419 struct init_if_phase_op if_phase /* if_phase init operation */;
1420 struct init_callback_op callback /* callback init operation */;
1421 struct init_delay_op delay /* delay init operation */;
1422};
1423
1424/* Init command operation types */
1425enum init_op_types {
1426 INIT_OP_READ /* GRC read init command */,
1427 INIT_OP_WRITE /* GRC write init command */,
1428 INIT_OP_IF_MODE,
1429 INIT_OP_IF_PHASE,
1430 INIT_OP_DELAY /* delay init command */,
1431 INIT_OP_CALLBACK /* callback init command */,
1432 MAX_INIT_OP_TYPES
1433};
1434
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001435enum init_poll_types {
1436 INIT_POLL_NONE /* No polling */,
1437 INIT_POLL_EQ /* init value is included in the init command */,
1438 INIT_POLL_OR /* init value is all zeros */,
1439 INIT_POLL_AND /* init value is an array of values */,
1440 MAX_INIT_POLL_TYPES
1441};
1442
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001443/* init source types */
1444enum init_source_types {
1445 INIT_SRC_INLINE /* init value is included in the init command */,
1446 INIT_SRC_ZEROS /* init value is all zeros */,
1447 INIT_SRC_ARRAY /* init value is an array of values */,
1448 INIT_SRC_RUNTIME /* init value is provided during runtime */,
1449 MAX_INIT_SOURCE_TYPES
1450};
1451
1452/* Internal RAM Offsets macro data */
1453struct iro {
1454 u32 base /* RAM field offset */;
1455 u16 m1 /* multiplier 1 */;
1456 u16 m2 /* multiplier 2 */;
1457 u16 m3 /* multiplier 3 */;
1458 u16 size /* RAM field size */;
1459};
1460
1461/* QM per-port init parameters */
1462struct init_qm_port_params {
1463 u8 active /* Indicates if this port is active */;
1464 u8 num_active_phys_tcs;
1465 u16 num_pbf_cmd_lines;
1466 u16 num_btb_blocks;
1467 __le16 reserved;
1468};
1469
1470/* QM per-PQ init parameters */
1471struct init_qm_pq_params {
1472 u8 vport_id /* VPORT ID */;
1473 u8 tc_id /* TC ID */;
1474 u8 wrr_group /* WRR group */;
1475 u8 reserved;
1476};
1477
1478/* QM per-vport init parameters */
1479struct init_qm_vport_params {
1480 u32 vport_rl;
1481 u16 vport_wfq;
1482 u16 first_tx_pq_id[NUM_OF_TCS];
1483};
1484
1485/* Win 2 */
1486#define GTT_BAR0_MAP_REG_IGU_CMD \
1487 0x00f000UL
1488/* Win 3 */
1489#define GTT_BAR0_MAP_REG_TSDM_RAM \
1490 0x010000UL
1491/* Win 4 */
1492#define GTT_BAR0_MAP_REG_MSDM_RAM \
1493 0x011000UL
1494/* Win 5 */
1495#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 \
1496 0x012000UL
1497/* Win 6 */
1498#define GTT_BAR0_MAP_REG_USDM_RAM \
1499 0x013000UL
1500/* Win 7 */
1501#define GTT_BAR0_MAP_REG_USDM_RAM_1024 \
1502 0x014000UL
1503/* Win 8 */
1504#define GTT_BAR0_MAP_REG_USDM_RAM_2048 \
1505 0x015000UL
1506/* Win 9 */
1507#define GTT_BAR0_MAP_REG_XSDM_RAM \
1508 0x016000UL
1509/* Win 10 */
1510#define GTT_BAR0_MAP_REG_YSDM_RAM \
1511 0x017000UL
1512/* Win 11 */
1513#define GTT_BAR0_MAP_REG_PSDM_RAM \
1514 0x018000UL
1515
1516/**
1517 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
1518 *
1519 * Returns the required host memory size in 4KB units.
1520 * Must be called before all QM init HSI functions.
1521 *
1522 * @param pf_id - physical function ID
1523 * @param num_pf_cids - number of connections used by this PF
1524 * @param num_vf_cids - number of connections used by VFs of this PF
1525 * @param num_tids - number of tasks used by this PF
1526 * @param num_pf_pqs - number of PQs used by this PF
1527 * @param num_vf_pqs - number of PQs used by VFs of this PF
1528 *
1529 * @return The required host memory size in 4KB units.
1530 */
1531u32 qed_qm_pf_mem_size(u8 pf_id,
1532 u32 num_pf_cids,
1533 u32 num_vf_cids,
1534 u32 num_tids,
1535 u16 num_pf_pqs,
1536 u16 num_vf_pqs);
1537
1538struct qed_qm_common_rt_init_params {
1539 u8 max_ports_per_engine;
1540 u8 max_phys_tcs_per_port;
1541 bool pf_rl_en;
1542 bool pf_wfq_en;
1543 bool vport_rl_en;
1544 bool vport_wfq_en;
1545 struct init_qm_port_params *port_params;
1546};
1547
1548/**
1549 * @brief qed_qm_common_rt_init - Prepare QM runtime init values for the
1550 * engine phase.
1551 *
1552 * @param p_hwfn
1553 * @param max_ports_per_engine - max number of ports per engine in HW
1554 * @param max_phys_tcs_per_port - max number of physical TCs per port in HW
1555 * @param pf_rl_en - enable per-PF rate limiters
1556 * @param pf_wfq_en - enable per-PF WFQ
1557 * @param vport_rl_en - enable per-VPORT rate limiters
1558 * @param vport_wfq_en - enable per-VPORT WFQ
1559 * @param port_params - array of size MAX_NUM_PORTS with
1560 * arameters for each port
1561 *
1562 * @return 0 on success, -1 on error.
1563 */
1564int qed_qm_common_rt_init(
1565 struct qed_hwfn *p_hwfn,
1566 struct qed_qm_common_rt_init_params *p_params);
1567
1568struct qed_qm_pf_rt_init_params {
1569 u8 port_id;
1570 u8 pf_id;
1571 u8 max_phys_tcs_per_port;
1572 bool is_first_pf;
1573 u32 num_pf_cids;
1574 u32 num_vf_cids;
1575 u32 num_tids;
1576 u16 start_pq;
1577 u16 num_pf_pqs;
1578 u16 num_vf_pqs;
1579 u8 start_vport;
1580 u8 num_vports;
1581 u8 pf_wfq;
1582 u32 pf_rl;
1583 struct init_qm_pq_params *pq_params;
1584 struct init_qm_vport_params *vport_params;
1585};
1586
1587int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
1588 struct qed_ptt *p_ptt,
1589 struct qed_qm_pf_rt_init_params *p_params);
1590
1591/**
1592 * @brief qed_init_pf_rl Initializes the rate limit of the specified PF
1593 *
1594 * @param p_hwfn
1595 * @param p_ptt - ptt window used for writing the registers
1596 * @param pf_id - PF ID
1597 * @param pf_rl - rate limit in Mb/sec units
1598 *
1599 * @return 0 on success, -1 on error.
1600 */
1601int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
1602 struct qed_ptt *p_ptt,
1603 u8 pf_id,
1604 u32 pf_rl);
1605
1606/**
1607 * @brief qed_init_vport_rl Initializes the rate limit of the specified VPORT
1608 *
1609 * @param p_hwfn
1610 * @param p_ptt - ptt window used for writing the registers
1611 * @param vport_id - VPORT ID
1612 * @param vport_rl - rate limit in Mb/sec units
1613 *
1614 * @return 0 on success, -1 on error.
1615 */
1616
1617int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
1618 struct qed_ptt *p_ptt,
1619 u8 vport_id,
1620 u32 vport_rl);
1621/**
1622 * @brief qed_send_qm_stop_cmd Sends a stop command to the QM
1623 *
1624 * @param p_hwfn
1625 * @param p_ptt - ptt window used for writing the registers
1626 * @param is_release_cmd - true for release, false for stop.
1627 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
1628 * @param start_pq - first PQ ID to stop
1629 * @param num_pqs - Number of PQs to stop, starting from start_pq.
1630 *
1631 * @return bool, true if successful, false if timeout occurred while waiting
1632 * for QM command done.
1633 */
1634
1635bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
1636 struct qed_ptt *p_ptt,
1637 bool is_release_cmd,
1638 bool is_tx_pq,
1639 u16 start_pq,
1640 u16 num_pqs);
1641
Manish Chopra464f6642016-04-14 01:38:29 -04001642void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
1643 struct qed_ptt *p_ptt, u16 dest_port);
1644void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
1645 struct qed_ptt *p_ptt, bool vxlan_enable);
1646void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
1647 struct qed_ptt *p_ptt, bool eth_gre_enable,
1648 bool ip_gre_enable);
1649void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
1650 struct qed_ptt *p_ptt, u16 dest_port);
1651void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
1652 struct qed_ptt *p_ptt, bool eth_geneve_enable,
1653 bool ip_geneve_enable);
1654
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001655/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001656#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
1657#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001658/* Tstorm port statistics */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001659#define TSTORM_PORT_STAT_OFFSET(port_id) (IRO[1].base + ((port_id) * IRO[1].m1))
1660#define TSTORM_PORT_STAT_SIZE (IRO[1].size)
1661/* Tstorm ll2 port statistics */
1662#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
1663 (IRO[2].base + ((port_id) * IRO[2].m1))
1664#define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001665/* Ustorm VF-PF Channel ready flag */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001666#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
1667 (IRO[3].base + ((vf_id) * IRO[3].m1))
1668#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001669/* Ustorm Final flr cleanup ack */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001670#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) (IRO[4].base + ((pf_id) * IRO[4].m1))
1671#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001672/* Ustorm Event ring consumer */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001673#define USTORM_EQE_CONS_OFFSET(pf_id) (IRO[5].base + ((pf_id) * IRO[5].m1))
1674#define USTORM_EQE_CONS_SIZE (IRO[5].size)
1675/* Ustorm Common Queue ring consumer */
1676#define USTORM_COMMON_QUEUE_CONS_OFFSET(global_queue_id) \
1677 (IRO[6].base + ((global_queue_id) * IRO[6].m1))
1678#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[6].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001679/* Xstorm Integration Test Data */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001680#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[7].base)
1681#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[7].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001682/* Ystorm Integration Test Data */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001683#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[8].base)
1684#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[8].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001685/* Pstorm Integration Test Data */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001686#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
1687#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001688/* Tstorm Integration Test Data */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001689#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
1690#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001691/* Mstorm Integration Test Data */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001692#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
1693#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001694/* Ustorm Integration Test Data */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001695#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
1696#define USTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001697/* Tstorm producers */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001698#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
1699 (IRO[13].base + ((core_rx_queue_id) * IRO[13].m1))
1700#define TSTORM_LL2_RX_PRODS_SIZE (IRO[13].size)
1701/* Tstorm LightL2 queue statistics */
1702#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
1703 (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
1704#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[14].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001705/* Ustorm LiteL2 queue statistics */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001706#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
1707 (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
1708#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001709/* Pstorm LiteL2 queue statistics */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001710#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
1711 (IRO[16].base + ((core_tx_stats_id) * IRO[16].m1))
1712#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001713/* Mstorm queue statistics */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001714#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1715 (IRO[17].base + ((stat_counter_id) * IRO[17].m1))
1716#define MSTORM_QUEUE_STAT_SIZE (IRO[17].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001717/* Mstorm producers */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001718#define MSTORM_PRODS_OFFSET(queue_id) (IRO[18].base + ((queue_id) * IRO[18].m1))
1719#define MSTORM_PRODS_SIZE (IRO[18].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001720/* TPA agregation timeout in us resolution (on ASIC) */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001721#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[19].base)
1722#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[19].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001723/* Ustorm queue statistics */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001724#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1725 (IRO[20].base + ((stat_counter_id) * IRO[20].m1))
1726#define USTORM_QUEUE_STAT_SIZE (IRO[20].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001727/* Ustorm queue zone */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001728#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
1729 (IRO[21].base + ((queue_id) * IRO[21].m1))
1730#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[21].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001731/* Pstorm queue statistics */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001732#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1733 (IRO[22].base + ((stat_counter_id) * IRO[22].m1))
1734#define PSTORM_QUEUE_STAT_SIZE (IRO[22].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001735/* Tstorm last parser message */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001736#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[23].base)
1737#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[23].size)
1738/* Tstorm Eth limit Rx rate */
1739#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) (IRO[24].base + ((pf_id) * IRO[24].m1))
1740#define ETH_RX_RATE_LIMIT_SIZE (IRO[24].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001741/* Ystorm queue zone */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001742#define YSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
1743 (IRO[25].base + ((queue_id) * IRO[25].m1))
1744#define YSTORM_ETH_QUEUE_ZONE_SIZE (IRO[25].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001745/* Ystorm cqe producer */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001746#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
1747 (IRO[26].base + ((rss_id) * IRO[26].m1))
1748#define YSTORM_TOE_CQ_PROD_SIZE (IRO[26].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001749/* Ustorm cqe producer */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001750#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
1751 (IRO[27].base + ((rss_id) * IRO[27].m1))
1752#define USTORM_TOE_CQ_PROD_SIZE (IRO[27].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001753/* Ustorm grq producer */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001754#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
1755 (IRO[28].base + ((pf_id) * IRO[28].m1))
1756#define USTORM_TOE_GRQ_PROD_SIZE (IRO[28].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001757/* Tstorm cmdq-cons of given command queue-id */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001758#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
1759 (IRO[29].base + ((cmdq_queue_id) * IRO[29].m1))
1760#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[29].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001761/* Mstorm rq-cons of given queue-id */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001762#define MSTORM_SCSI_RQ_CONS_OFFSET(rq_queue_id) \
1763 (IRO[30].base + ((rq_queue_id) * IRO[30].m1))
1764#define MSTORM_SCSI_RQ_CONS_SIZE (IRO[30].size)
1765/* Mstorm bdq-external-producer of given BDQ function ID, BDqueue-id */
1766#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
1767 (IRO[31].base + ((func_id) * IRO[31].m1) + ((bdq_id) * IRO[31].m2))
1768#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[31].size)
1769/* Tstorm (reflects M-Storm) bdq-external-producer of given fn ID, BDqueue-id */
1770#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
1771 (IRO[32].base + ((func_id) * IRO[32].m1) + ((bdq_id) * IRO[32].m2))
1772#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[32].size)
1773/* Tstorm iSCSI RX stats */
1774#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1775 (IRO[33].base + ((pf_id) * IRO[33].m1))
1776#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[33].size)
1777/* Mstorm iSCSI RX stats */
1778#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1779 (IRO[34].base + ((pf_id) * IRO[34].m1))
1780#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[34].size)
1781/* Ustorm iSCSI RX stats */
1782#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1783 (IRO[35].base + ((pf_id) * IRO[35].m1))
1784#define USTORM_ISCSI_RX_STATS_SIZE (IRO[35].size)
1785/* Xstorm iSCSI TX stats */
1786#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1787 (IRO[36].base + ((pf_id) * IRO[36].m1))
1788#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[36].size)
1789/* Ystorm iSCSI TX stats */
1790#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1791 (IRO[37].base + ((pf_id) * IRO[37].m1))
1792#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[37].size)
1793/* Pstorm iSCSI TX stats */
1794#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1795 (IRO[38].base + ((pf_id) * IRO[38].m1))
1796#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[38].size)
1797/* Tstorm FCoE RX stats */
1798#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
1799 (IRO[39].base + ((pf_id) * IRO[39].m1))
1800#define TSTORM_FCOE_RX_STATS_SIZE (IRO[39].size)
1801/* Mstorm FCoE RX stats */
1802#define MSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
1803 (IRO[40].base + ((pf_id) * IRO[40].m1))
1804#define MSTORM_FCOE_RX_STATS_SIZE (IRO[40].size)
1805/* Pstorm FCoE TX stats */
1806#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
1807 (IRO[41].base + ((pf_id) * IRO[41].m1))
1808#define PSTORM_FCOE_TX_STATS_SIZE (IRO[41].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001809/* Pstorm RoCE statistics */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001810#define PSTORM_ROCE_STAT_OFFSET(stat_counter_id) \
1811 (IRO[42].base + ((stat_counter_id) * IRO[42].m1))
1812#define PSTORM_ROCE_STAT_SIZE (IRO[42].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001813/* Tstorm RoCE statistics */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001814#define TSTORM_ROCE_STAT_OFFSET(stat_counter_id) \
1815 (IRO[43].base + ((stat_counter_id) * IRO[43].m1))
1816#define TSTORM_ROCE_STAT_SIZE (IRO[43].size)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001817
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001818static const struct iro iro_arr[44] = {
1819 { 0x10, 0x0, 0x0, 0x0, 0x8 },
1820 { 0x47c8, 0x60, 0x0, 0x0, 0x60 },
1821 { 0x5e30, 0x20, 0x0, 0x0, 0x20 },
1822 { 0x510, 0x8, 0x0, 0x0, 0x4 },
1823 { 0x490, 0x8, 0x0, 0x0, 0x4 },
1824 { 0x10, 0x8, 0x0, 0x0, 0x2 },
1825 { 0x90, 0x8, 0x0, 0x0, 0x2 },
1826 { 0x4940, 0x0, 0x0, 0x0, 0x78 },
1827 { 0x3de0, 0x0, 0x0, 0x0, 0x78 },
1828 { 0x2998, 0x0, 0x0, 0x0, 0x78 },
1829 { 0x4750, 0x0, 0x0, 0x0, 0x78 },
1830 { 0x56d0, 0x0, 0x0, 0x0, 0x78 },
1831 { 0x7e50, 0x0, 0x0, 0x0, 0x78 },
1832 { 0x100, 0x8, 0x0, 0x0, 0x8 },
1833 { 0x5c10, 0x10, 0x0, 0x0, 0x10 },
1834 { 0xb508, 0x30, 0x0, 0x0, 0x30 },
1835 { 0x95c0, 0x30, 0x0, 0x0, 0x30 },
1836 { 0x58a0, 0x40, 0x0, 0x0, 0x40 },
1837 { 0x200, 0x10, 0x0, 0x0, 0x8 },
1838 { 0xa230, 0x0, 0x0, 0x0, 0x4 },
1839 { 0x8058, 0x40, 0x0, 0x0, 0x30 },
1840 { 0xd00, 0x8, 0x0, 0x0, 0x8 },
1841 { 0x2b30, 0x80, 0x0, 0x0, 0x38 },
1842 { 0xa808, 0x0, 0x0, 0x0, 0xf0 },
1843 { 0xa8f8, 0x8, 0x0, 0x0, 0x8 },
1844 { 0x80, 0x8, 0x0, 0x0, 0x8 },
1845 { 0xac0, 0x8, 0x0, 0x0, 0x8 },
1846 { 0x2580, 0x8, 0x0, 0x0, 0x8 },
1847 { 0x2500, 0x8, 0x0, 0x0, 0x8 },
1848 { 0x440, 0x8, 0x0, 0x0, 0x2 },
1849 { 0x1800, 0x8, 0x0, 0x0, 0x2 },
1850 { 0x1a00, 0x10, 0x8, 0x0, 0x2 },
1851 { 0x640, 0x10, 0x8, 0x0, 0x2 },
1852 { 0xd9b8, 0x38, 0x0, 0x0, 0x24 },
1853 { 0x11048, 0x10, 0x0, 0x0, 0x8 },
1854 { 0x11678, 0x38, 0x0, 0x0, 0x18 },
1855 { 0xaec0, 0x30, 0x0, 0x0, 0x10 },
1856 { 0x8700, 0x28, 0x0, 0x0, 0x18 },
1857 { 0xec00, 0x10, 0x0, 0x0, 0x10 },
1858 { 0xde38, 0x40, 0x0, 0x0, 0x30 },
1859 { 0x121a8, 0x38, 0x0, 0x0, 0x8 },
1860 { 0xf068, 0x20, 0x0, 0x0, 0x20 },
1861 { 0x2b68, 0x80, 0x0, 0x0, 0x10 },
1862 { 0x4ab8, 0x10, 0x0, 0x0, 0x10 },
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001863};
1864
1865/* Runtime array offsets */
1866#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
1867#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
1868#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
1869#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
1870#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
1871#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
1872#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
1873#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
1874#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
1875#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
1876#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
1877#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
1878#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
1879#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
1880#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
1881#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
1882#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001883#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
1884#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
1885#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
1886#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
1887#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
1888#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
1889#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
1890#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
1891#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001892#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001893#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001894#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001895#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001896#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001897#define CAU_REG_PI_MEMORY_RT_OFFSET 2233
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001898#define CAU_REG_PI_MEMORY_RT_SIZE 4416
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001899#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
1900#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
1901#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
1902#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
1903#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
1904#define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
1905#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
1906#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
1907#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
1908#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
1909#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
1910#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
1911#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
1912#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
1913#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
1914#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
1915#define SRC_REG_FIRSTFREE_RT_OFFSET 6665
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001916#define SRC_REG_FIRSTFREE_RT_SIZE 2
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001917#define SRC_REG_LASTFREE_RT_OFFSET 6667
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001918#define SRC_REG_LASTFREE_RT_SIZE 2
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001919#define SRC_REG_COUNTFREE_RT_OFFSET 6669
1920#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
1921#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
1922#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
1923#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
1924#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
1925#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
1926#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6676
1927#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6677
1928#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6678
1929#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6679
1930#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6680
1931#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6681
1932#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6682
1933#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6683
1934#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6684
1935#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6685
1936#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6686
1937#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6687
1938#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6688
1939#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
1940#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
1941#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6691
1942#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6692
1943#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6693
1944#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6694
1945#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6695
1946#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6696
1947#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6697
1948#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6698
1949#define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6699
1950#define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6700
1951#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6701
1952#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6702
1953#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6703
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001954#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001955#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28703
1956#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28704
1957#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28705
1958#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28706
1959#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28707
1960#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28708
1961#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28709
1962#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28710
1963#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28711
1964#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28712
1965#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28713
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001966#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001967#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29129
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001968#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001969#define QM_REG_MAXPQSIZE_0_RT_OFFSET 29641
1970#define QM_REG_MAXPQSIZE_1_RT_OFFSET 29642
1971#define QM_REG_MAXPQSIZE_2_RT_OFFSET 29643
1972#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29644
1973#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29645
1974#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29646
1975#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29647
1976#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29648
1977#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29649
1978#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29650
1979#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29651
1980#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29652
1981#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29653
1982#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29654
1983#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29655
1984#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29656
1985#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29657
1986#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29658
1987#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29659
1988#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29660
1989#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29661
1990#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29662
1991#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29663
1992#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29664
1993#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29665
1994#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29666
1995#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29667
1996#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29668
1997#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29669
1998#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29670
1999#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29671
2000#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29672
2001#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29673
2002#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29674
2003#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29675
2004#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29676
2005#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29677
2006#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29678
2007#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29679
2008#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29680
2009#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29681
2010#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29682
2011#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29683
2012#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29684
2013#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29685
2014#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29686
2015#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29687
2016#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29688
2017#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29689
2018#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29690
2019#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29691
2020#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29692
2021#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29693
2022#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29694
2023#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29695
2024#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29696
2025#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29697
2026#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29698
2027#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29699
2028#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29700
2029#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29701
2030#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29702
2031#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29703
2032#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29704
2033#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29705
2034#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29706
2035#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29707
2036#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29708
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002037#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002038#define QM_REG_VOQCRDLINE_RT_OFFSET 29836
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002039#define QM_REG_VOQCRDLINE_RT_SIZE 20
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002040#define QM_REG_VOQINITCRDLINE_RT_OFFSET 29856
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002041#define QM_REG_VOQINITCRDLINE_RT_SIZE 20
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002042#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29876
2043#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29877
2044#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29878
2045#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29879
2046#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29880
2047#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29881
2048#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29882
2049#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29883
2050#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29884
2051#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29885
2052#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29886
2053#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29887
2054#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29888
2055#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29889
2056#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29890
2057#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29891
2058#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29892
2059#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29893
2060#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29894
2061#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29895
2062#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29896
2063#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29897
2064#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29898
2065#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29899
2066#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29900
2067#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29901
2068#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29902
2069#define QM_REG_PQTX2PF_0_RT_OFFSET 29903
2070#define QM_REG_PQTX2PF_1_RT_OFFSET 29904
2071#define QM_REG_PQTX2PF_2_RT_OFFSET 29905
2072#define QM_REG_PQTX2PF_3_RT_OFFSET 29906
2073#define QM_REG_PQTX2PF_4_RT_OFFSET 29907
2074#define QM_REG_PQTX2PF_5_RT_OFFSET 29908
2075#define QM_REG_PQTX2PF_6_RT_OFFSET 29909
2076#define QM_REG_PQTX2PF_7_RT_OFFSET 29910
2077#define QM_REG_PQTX2PF_8_RT_OFFSET 29911
2078#define QM_REG_PQTX2PF_9_RT_OFFSET 29912
2079#define QM_REG_PQTX2PF_10_RT_OFFSET 29913
2080#define QM_REG_PQTX2PF_11_RT_OFFSET 29914
2081#define QM_REG_PQTX2PF_12_RT_OFFSET 29915
2082#define QM_REG_PQTX2PF_13_RT_OFFSET 29916
2083#define QM_REG_PQTX2PF_14_RT_OFFSET 29917
2084#define QM_REG_PQTX2PF_15_RT_OFFSET 29918
2085#define QM_REG_PQTX2PF_16_RT_OFFSET 29919
2086#define QM_REG_PQTX2PF_17_RT_OFFSET 29920
2087#define QM_REG_PQTX2PF_18_RT_OFFSET 29921
2088#define QM_REG_PQTX2PF_19_RT_OFFSET 29922
2089#define QM_REG_PQTX2PF_20_RT_OFFSET 29923
2090#define QM_REG_PQTX2PF_21_RT_OFFSET 29924
2091#define QM_REG_PQTX2PF_22_RT_OFFSET 29925
2092#define QM_REG_PQTX2PF_23_RT_OFFSET 29926
2093#define QM_REG_PQTX2PF_24_RT_OFFSET 29927
2094#define QM_REG_PQTX2PF_25_RT_OFFSET 29928
2095#define QM_REG_PQTX2PF_26_RT_OFFSET 29929
2096#define QM_REG_PQTX2PF_27_RT_OFFSET 29930
2097#define QM_REG_PQTX2PF_28_RT_OFFSET 29931
2098#define QM_REG_PQTX2PF_29_RT_OFFSET 29932
2099#define QM_REG_PQTX2PF_30_RT_OFFSET 29933
2100#define QM_REG_PQTX2PF_31_RT_OFFSET 29934
2101#define QM_REG_PQTX2PF_32_RT_OFFSET 29935
2102#define QM_REG_PQTX2PF_33_RT_OFFSET 29936
2103#define QM_REG_PQTX2PF_34_RT_OFFSET 29937
2104#define QM_REG_PQTX2PF_35_RT_OFFSET 29938
2105#define QM_REG_PQTX2PF_36_RT_OFFSET 29939
2106#define QM_REG_PQTX2PF_37_RT_OFFSET 29940
2107#define QM_REG_PQTX2PF_38_RT_OFFSET 29941
2108#define QM_REG_PQTX2PF_39_RT_OFFSET 29942
2109#define QM_REG_PQTX2PF_40_RT_OFFSET 29943
2110#define QM_REG_PQTX2PF_41_RT_OFFSET 29944
2111#define QM_REG_PQTX2PF_42_RT_OFFSET 29945
2112#define QM_REG_PQTX2PF_43_RT_OFFSET 29946
2113#define QM_REG_PQTX2PF_44_RT_OFFSET 29947
2114#define QM_REG_PQTX2PF_45_RT_OFFSET 29948
2115#define QM_REG_PQTX2PF_46_RT_OFFSET 29949
2116#define QM_REG_PQTX2PF_47_RT_OFFSET 29950
2117#define QM_REG_PQTX2PF_48_RT_OFFSET 29951
2118#define QM_REG_PQTX2PF_49_RT_OFFSET 29952
2119#define QM_REG_PQTX2PF_50_RT_OFFSET 29953
2120#define QM_REG_PQTX2PF_51_RT_OFFSET 29954
2121#define QM_REG_PQTX2PF_52_RT_OFFSET 29955
2122#define QM_REG_PQTX2PF_53_RT_OFFSET 29956
2123#define QM_REG_PQTX2PF_54_RT_OFFSET 29957
2124#define QM_REG_PQTX2PF_55_RT_OFFSET 29958
2125#define QM_REG_PQTX2PF_56_RT_OFFSET 29959
2126#define QM_REG_PQTX2PF_57_RT_OFFSET 29960
2127#define QM_REG_PQTX2PF_58_RT_OFFSET 29961
2128#define QM_REG_PQTX2PF_59_RT_OFFSET 29962
2129#define QM_REG_PQTX2PF_60_RT_OFFSET 29963
2130#define QM_REG_PQTX2PF_61_RT_OFFSET 29964
2131#define QM_REG_PQTX2PF_62_RT_OFFSET 29965
2132#define QM_REG_PQTX2PF_63_RT_OFFSET 29966
2133#define QM_REG_PQOTHER2PF_0_RT_OFFSET 29967
2134#define QM_REG_PQOTHER2PF_1_RT_OFFSET 29968
2135#define QM_REG_PQOTHER2PF_2_RT_OFFSET 29969
2136#define QM_REG_PQOTHER2PF_3_RT_OFFSET 29970
2137#define QM_REG_PQOTHER2PF_4_RT_OFFSET 29971
2138#define QM_REG_PQOTHER2PF_5_RT_OFFSET 29972
2139#define QM_REG_PQOTHER2PF_6_RT_OFFSET 29973
2140#define QM_REG_PQOTHER2PF_7_RT_OFFSET 29974
2141#define QM_REG_PQOTHER2PF_8_RT_OFFSET 29975
2142#define QM_REG_PQOTHER2PF_9_RT_OFFSET 29976
2143#define QM_REG_PQOTHER2PF_10_RT_OFFSET 29977
2144#define QM_REG_PQOTHER2PF_11_RT_OFFSET 29978
2145#define QM_REG_PQOTHER2PF_12_RT_OFFSET 29979
2146#define QM_REG_PQOTHER2PF_13_RT_OFFSET 29980
2147#define QM_REG_PQOTHER2PF_14_RT_OFFSET 29981
2148#define QM_REG_PQOTHER2PF_15_RT_OFFSET 29982
2149#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29983
2150#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29984
2151#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29985
2152#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29986
2153#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29987
2154#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29988
2155#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29989
2156#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29990
2157#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29991
2158#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29992
2159#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29993
2160#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29994
2161#define QM_REG_RLGLBLINCVAL_RT_OFFSET 29995
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002162#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002163#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30251
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002164#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002165#define QM_REG_RLGLBLCRD_RT_OFFSET 30507
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002166#define QM_REG_RLGLBLCRD_RT_SIZE 256
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002167#define QM_REG_RLGLBLENABLE_RT_OFFSET 30763
2168#define QM_REG_RLPFPERIOD_RT_OFFSET 30764
2169#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30765
2170#define QM_REG_RLPFINCVAL_RT_OFFSET 30766
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002171#define QM_REG_RLPFINCVAL_RT_SIZE 16
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002172#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30782
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002173#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002174#define QM_REG_RLPFCRD_RT_OFFSET 30798
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002175#define QM_REG_RLPFCRD_RT_SIZE 16
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002176#define QM_REG_RLPFENABLE_RT_OFFSET 30814
2177#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30815
2178#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30816
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002179#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002180#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30832
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002181#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002182#define QM_REG_WFQPFCRD_RT_OFFSET 30848
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002183#define QM_REG_WFQPFCRD_RT_SIZE 160
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002184#define QM_REG_WFQPFENABLE_RT_OFFSET 31008
2185#define QM_REG_WFQVPENABLE_RT_OFFSET 31009
2186#define QM_REG_BASEADDRTXPQ_RT_OFFSET 31010
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002187#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002188#define QM_REG_TXPQMAP_RT_OFFSET 31522
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002189#define QM_REG_TXPQMAP_RT_SIZE 512
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002190#define QM_REG_WFQVPWEIGHT_RT_OFFSET 32034
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002191#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002192#define QM_REG_WFQVPCRD_RT_OFFSET 32546
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002193#define QM_REG_WFQVPCRD_RT_SIZE 512
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002194#define QM_REG_WFQVPMAP_RT_OFFSET 33058
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002195#define QM_REG_WFQVPMAP_RT_SIZE 512
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002196#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33570
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002197#define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002198#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33730
2199#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33731
2200#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33732
2201#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33733
2202#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33734
2203#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33735
2204#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33736
2205#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33737
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002206#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002207#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33741
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002208#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002209#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33745
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002210#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002211#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33749
2212#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33750
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002213#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002214#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33782
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002215#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002216#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33798
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002217#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002218#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33814
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002219#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002220#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33830
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002221#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002222#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33846
2223#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33847
2224#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33848
2225#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33849
2226#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33850
2227#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33851
2228#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33852
2229#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33853
2230#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33854
2231#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33855
2232#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33856
2233#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33857
2234#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33858
2235#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33859
2236#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33860
2237#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33861
2238#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33862
2239#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33863
2240#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33864
2241#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33865
2242#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33866
2243#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33867
2244#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33868
2245#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33869
2246#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33870
2247#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33871
2248#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33872
2249#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33873
2250#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33874
2251#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33875
2252#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33876
2253#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33877
2254#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33878
2255#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33879
2256#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33880
2257#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33881
2258#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33882
2259#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33883
2260#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33884
2261#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33885
2262#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33886
2263#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33887
2264#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33888
2265#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33889
2266#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33890
2267#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33891
2268#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33892
2269#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33893
2270#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33894
2271#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33895
2272#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33896
2273#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33897
2274#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33898
2275#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33899
2276#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33900
2277#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33901
2278#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33902
2279#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33903
2280#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33904
2281#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33905
2282#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33906
2283#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33907
2284#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33908
2285#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33909
2286#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33910
2287#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33911
2288#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33912
2289#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33913
2290#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33914
2291#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33915
2292#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33916
2293#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33917
2294#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33918
2295#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33919
2296#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33920
2297#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33921
2298#define XCM_REG_CON_PHY_Q3_RT_OFFSET 33922
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002299
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002300#define RUNTIME_ARRAY_SIZE 33923
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002301
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002302/* The eth storm context for the Tstorm */
2303struct tstorm_eth_conn_st_ctx {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002304 __le32 reserved[4];
2305};
2306
2307/* The eth storm context for the Pstorm */
2308struct pstorm_eth_conn_st_ctx {
2309 __le32 reserved[8];
2310};
2311
2312/* The eth storm context for the Xstorm */
2313struct xstorm_eth_conn_st_ctx {
2314 __le32 reserved[60];
2315};
2316
2317struct xstorm_eth_conn_ag_ctx {
2318 u8 reserved0 /* cdu_validation */;
2319 u8 eth_state /* state */;
2320 u8 flags0;
2321#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
2322#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
2323#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
2324#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
2325#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
2326#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
2327#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
2328#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
2329#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
2330#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
2331#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
2332#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
2333#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
2334#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
2335#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
2336#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
2337 u8 flags1;
2338#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
2339#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
2340#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
2341#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
2342#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */
2343#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
2344#define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
2345#define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
2346#define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
2347#define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
2348#define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
2349#define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
2350#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */
2351#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
2352#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */
2353#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
2354 u8 flags2;
2355#define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
2356#define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
2357#define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
2358#define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
2359#define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2360#define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
2361#define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
2362#define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
2363 u8 flags3;
2364#define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
2365#define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
2366#define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
2367#define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
2368#define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
2369#define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
2370#define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
2371#define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
2372 u8 flags4;
2373#define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
2374#define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
2375#define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
2376#define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
2377#define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
2378#define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
2379#define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
2380#define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
2381 u8 flags5;
2382#define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
2383#define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
2384#define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
2385#define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
2386#define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
2387#define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
2388#define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
2389#define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
2390 u8 flags6;
2391#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */
2392#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
2393#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
2394#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
2395#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */
2396#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
2397#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */
2398#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
2399 u8 flags7;
2400#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
2401#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
2402#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */
2403#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
2404#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
2405#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
2406#define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2407#define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
2408#define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2409#define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
2410 u8 flags8;
2411#define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2412#define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
2413#define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2414#define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
2415#define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
2416#define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
2417#define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
2418#define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
2419#define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
2420#define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
2421#define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
2422#define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
2423#define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
2424#define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
2425#define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
2426#define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
2427 u8 flags9;
2428#define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
2429#define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
2430#define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
2431#define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
2432#define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
2433#define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
2434#define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
2435#define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
2436#define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
2437#define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
2438#define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
2439#define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
2440#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */
2441#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
2442#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
2443#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
2444 u8 flags10;
2445#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */
2446#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
2447#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */
2448#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
2449#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */
2450#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
2451#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */
2452#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
2453#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
2454#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
2455#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */
2456#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2457#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */
2458#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
2459#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */
2460#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
2461 u8 flags11;
2462#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */
2463#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
2464#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */
2465#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
2466#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */
2467#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
2468#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2469#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
2470#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
2471#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
2472#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2473#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
2474#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
2475#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
2476#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
2477#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
2478 u8 flags12;
2479#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
2480#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
2481#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
2482#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
2483#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
2484#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
2485#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
2486#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
2487#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
2488#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
2489#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
2490#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
2491#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
2492#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
2493#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
2494#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
2495 u8 flags13;
2496#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
2497#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
2498#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
2499#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
2500#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
2501#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
2502#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
2503#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
2504#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
2505#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
2506#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
2507#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
2508#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
2509#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
2510#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
2511#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
2512 u8 flags14;
2513#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */
2514#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
2515#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */
2516#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
2517#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */
2518#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
2519#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */
2520#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
2521#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */
2522#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
2523#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */
2524#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2525#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */
2526#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
2527 u8 edpm_event_id /* byte2 */;
2528 __le16 physical_q0 /* physical_q0 */;
2529 __le16 word1 /* physical_q1 */;
2530 __le16 edpm_num_bds /* physical_q2 */;
2531 __le16 tx_bd_cons /* word3 */;
2532 __le16 tx_bd_prod /* word4 */;
2533 __le16 go_to_bd_cons /* word5 */;
2534 __le16 conn_dpi /* conn_dpi */;
2535 u8 byte3 /* byte3 */;
2536 u8 byte4 /* byte4 */;
2537 u8 byte5 /* byte5 */;
2538 u8 byte6 /* byte6 */;
2539 __le32 reg0 /* reg0 */;
2540 __le32 reg1 /* reg1 */;
2541 __le32 reg2 /* reg2 */;
2542 __le32 reg3 /* reg3 */;
2543 __le32 reg4 /* reg4 */;
2544 __le32 reg5 /* cf_array0 */;
2545 __le32 reg6 /* cf_array1 */;
2546 __le16 word7 /* word7 */;
2547 __le16 word8 /* word8 */;
2548 __le16 word9 /* word9 */;
2549 __le16 word10 /* word10 */;
2550 __le32 reg7 /* reg7 */;
2551 __le32 reg8 /* reg8 */;
2552 __le32 reg9 /* reg9 */;
2553 u8 byte7 /* byte7 */;
2554 u8 byte8 /* byte8 */;
2555 u8 byte9 /* byte9 */;
2556 u8 byte10 /* byte10 */;
2557 u8 byte11 /* byte11 */;
2558 u8 byte12 /* byte12 */;
2559 u8 byte13 /* byte13 */;
2560 u8 byte14 /* byte14 */;
2561 u8 byte15 /* byte15 */;
2562 u8 byte16 /* byte16 */;
2563 __le16 word11 /* word11 */;
2564 __le32 reg10 /* reg10 */;
2565 __le32 reg11 /* reg11 */;
2566 __le32 reg12 /* reg12 */;
2567 __le32 reg13 /* reg13 */;
2568 __le32 reg14 /* reg14 */;
2569 __le32 reg15 /* reg15 */;
2570 __le32 reg16 /* reg16 */;
2571 __le32 reg17 /* reg17 */;
2572 __le32 reg18 /* reg18 */;
2573 __le32 reg19 /* reg19 */;
2574 __le16 word12 /* word12 */;
2575 __le16 word13 /* word13 */;
2576 __le16 word14 /* word14 */;
2577 __le16 word15 /* word15 */;
2578};
2579
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002580/* The eth storm context for the Ystorm */
2581struct ystorm_eth_conn_st_ctx {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002582 __le32 reserved[8];
2583};
2584
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002585struct ystorm_eth_conn_ag_ctx {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002586 u8 byte0 /* cdu_validation */;
2587 u8 byte1 /* state */;
2588 u8 flags0;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002589#define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2590#define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
2591#define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2592#define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
2593#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */
2594#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
2595#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */
2596#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
2597#define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2598#define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002599 u8 flags1;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002600#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf0en */
2601#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
2602#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */
2603#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
2604#define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2605#define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
2606#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2607#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
2608#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2609#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
2610#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2611#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
2612#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2613#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
2614#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2615#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
2616 u8 byte2 /* byte2 */;
2617 u8 byte3 /* byte3 */;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002618 __le16 word0 /* word0 */;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002619 __le32 terminate_spqe /* reg0 */;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002620 __le32 reg1 /* reg1 */;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002621 __le16 tx_bd_cons_upd /* word1 */;
2622 __le16 word2 /* word2 */;
2623 __le16 word3 /* word3 */;
2624 __le16 word4 /* word4 */;
2625 __le32 reg2 /* reg2 */;
2626 __le32 reg3 /* reg3 */;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002627};
2628
2629struct tstorm_eth_conn_ag_ctx {
2630 u8 byte0 /* cdu_validation */;
2631 u8 byte1 /* state */;
2632 u8 flags0;
2633#define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2634#define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
2635#define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2636#define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
2637#define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
2638#define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
2639#define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
2640#define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
2641#define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
2642#define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
2643#define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
2644#define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
2645#define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
2646#define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
2647 u8 flags1;
2648#define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
2649#define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
2650#define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2651#define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
2652#define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
2653#define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
2654#define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
2655#define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
2656 u8 flags2;
2657#define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
2658#define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
2659#define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
2660#define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
2661#define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
2662#define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
2663#define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
2664#define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
2665 u8 flags3;
2666#define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
2667#define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
2668#define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
2669#define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
2670#define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2671#define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
2672#define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2673#define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
2674#define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2675#define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
2676#define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2677#define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
2678 u8 flags4;
2679#define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
2680#define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
2681#define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
2682#define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
2683#define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
2684#define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
2685#define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
2686#define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
2687#define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
2688#define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
2689#define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
2690#define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
2691#define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
2692#define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
2693#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2694#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
2695 u8 flags5;
2696#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2697#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
2698#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2699#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
2700#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2701#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
2702#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2703#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
2704#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2705#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
2706#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */
2707#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
2708#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2709#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
2710#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
2711#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
2712 __le32 reg0 /* reg0 */;
2713 __le32 reg1 /* reg1 */;
2714 __le32 reg2 /* reg2 */;
2715 __le32 reg3 /* reg3 */;
2716 __le32 reg4 /* reg4 */;
2717 __le32 reg5 /* reg5 */;
2718 __le32 reg6 /* reg6 */;
2719 __le32 reg7 /* reg7 */;
2720 __le32 reg8 /* reg8 */;
2721 u8 byte2 /* byte2 */;
2722 u8 byte3 /* byte3 */;
2723 __le16 rx_bd_cons /* word0 */;
2724 u8 byte4 /* byte4 */;
2725 u8 byte5 /* byte5 */;
2726 __le16 rx_bd_prod /* word1 */;
2727 __le16 word2 /* conn_dpi */;
2728 __le16 word3 /* word3 */;
2729 __le32 reg9 /* reg9 */;
2730 __le32 reg10 /* reg10 */;
2731};
2732
2733struct ustorm_eth_conn_ag_ctx {
2734 u8 byte0 /* cdu_validation */;
2735 u8 byte1 /* state */;
2736 u8 flags0;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002737#define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002738#define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002739#define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002740#define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002741#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 /* timer0cf */
2742#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
2743#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 /* timer1cf */
2744#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
2745#define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002746#define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
2747 u8 flags1;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002748#define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
2749#define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
2750#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */
2751#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
2752#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */
2753#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
2754#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */
2755#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002756 u8 flags2;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002757#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf0en */
2758#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
2759#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */
2760#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
2761#define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2762#define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
2763#define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2764#define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
2765#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */
2766#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
2767#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */
2768#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
2769#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */
2770#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
2771#define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2772#define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002773 u8 flags3;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002774#define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2775#define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
2776#define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2777#define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
2778#define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2779#define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
2780#define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2781#define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
2782#define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2783#define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
2784#define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
2785#define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
2786#define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2787#define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
2788#define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
2789#define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002790 u8 byte2 /* byte2 */;
2791 u8 byte3 /* byte3 */;
2792 __le16 word0 /* conn_dpi */;
2793 __le16 tx_bd_cons /* word1 */;
2794 __le32 reg0 /* reg0 */;
2795 __le32 reg1 /* reg1 */;
2796 __le32 reg2 /* reg2 */;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002797 __le32 tx_int_coallecing_timeset /* reg3 */;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002798 __le16 tx_drv_bd_cons /* word2 */;
2799 __le16 rx_drv_cqe_cons /* word3 */;
2800};
2801
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002802/* The eth storm context for the Ustorm */
2803struct ustorm_eth_conn_st_ctx {
2804 __le32 reserved[40];
2805};
2806
2807/* The eth storm context for the Mstorm */
2808struct mstorm_eth_conn_st_ctx {
2809 __le32 reserved[8];
2810};
2811
2812/* eth connection context */
2813struct eth_conn_context {
2814 struct tstorm_eth_conn_st_ctx tstorm_st_context;
2815 struct regpair tstorm_st_padding[2];
2816 struct pstorm_eth_conn_st_ctx pstorm_st_context;
2817 struct xstorm_eth_conn_st_ctx xstorm_st_context;
2818 struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
2819 struct ystorm_eth_conn_st_ctx ystorm_st_context;
2820 struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
2821 struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
2822 struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
2823 struct ustorm_eth_conn_st_ctx ustorm_st_context;
2824 struct mstorm_eth_conn_st_ctx mstorm_st_context;
2825};
2826
2827enum eth_filter_action {
2828 ETH_FILTER_ACTION_REMOVE,
2829 ETH_FILTER_ACTION_ADD,
2830 ETH_FILTER_ACTION_REMOVE_ALL,
2831 MAX_ETH_FILTER_ACTION
2832};
2833
2834struct eth_filter_cmd {
2835 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */;
2836 u8 vport_id /* the vport id */;
2837 u8 action /* filter command action: add/remove/replace */;
2838 u8 reserved0;
2839 __le32 vni;
2840 __le16 mac_lsb;
2841 __le16 mac_mid;
2842 __le16 mac_msb;
2843 __le16 vlan_id;
2844};
2845
2846struct eth_filter_cmd_header {
2847 u8 rx;
2848 u8 tx;
2849 u8 cmd_cnt;
2850 u8 assert_on_error;
2851 u8 reserved1[4];
2852};
2853
2854enum eth_filter_type {
2855 ETH_FILTER_TYPE_MAC,
2856 ETH_FILTER_TYPE_VLAN,
2857 ETH_FILTER_TYPE_PAIR,
2858 ETH_FILTER_TYPE_INNER_MAC,
2859 ETH_FILTER_TYPE_INNER_VLAN,
2860 ETH_FILTER_TYPE_INNER_PAIR,
2861 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
2862 ETH_FILTER_TYPE_MAC_VNI_PAIR,
2863 ETH_FILTER_TYPE_VNI,
2864 MAX_ETH_FILTER_TYPE
2865};
2866
2867enum eth_ramrod_cmd_id {
2868 ETH_RAMROD_UNUSED,
2869 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */,
2870 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */,
2871 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */,
2872 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
2873 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
2874 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
2875 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
2876 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
2877 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
2878 ETH_RAMROD_RESERVED,
2879 ETH_RAMROD_RESERVED2,
2880 ETH_RAMROD_RESERVED3,
2881 ETH_RAMROD_RESERVED4,
2882 ETH_RAMROD_RESERVED5,
2883 ETH_RAMROD_RESERVED6,
2884 ETH_RAMROD_RESERVED7,
2885 ETH_RAMROD_RESERVED8,
2886 MAX_ETH_RAMROD_CMD_ID
2887};
2888
2889enum eth_tx_err {
2890 ETH_TX_ERR_DROP /* Drop erronous packet. */,
2891 ETH_TX_ERR_ASSERT_MALICIOUS,
2892 MAX_ETH_TX_ERR
2893};
2894
2895struct eth_tx_err_vals {
2896 __le16 values;
2897#define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
2898#define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
2899#define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
2900#define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
2901#define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
2902#define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
2903#define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
2904#define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
2905#define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
2906#define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
2907#define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
2908#define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
2909#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
2910#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
2911#define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
2912#define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
2913};
2914
2915struct eth_vport_rss_config {
2916 __le16 capabilities;
2917#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
2918#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
2919#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
2920#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
2921#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
2922#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
2923#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
2924#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
2925#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
2926#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
2927#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
2928#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
2929#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
2930#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
2931#define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
2932#define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
2933 u8 rss_id;
2934 u8 rss_mode;
2935 u8 update_rss_key;
2936 u8 update_rss_ind_table;
2937 u8 update_rss_capabilities;
2938 u8 tbl_size;
2939 __le32 reserved2[2];
2940 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
2941 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
2942 __le32 reserved3[2];
2943};
2944
2945enum eth_vport_rss_mode {
2946 ETH_VPORT_RSS_MODE_DISABLED,
2947 ETH_VPORT_RSS_MODE_REGULAR,
2948 MAX_ETH_VPORT_RSS_MODE
2949};
2950
2951struct eth_vport_rx_mode {
2952 __le16 state;
2953#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
2954#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
2955#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
2956#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
2957#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
2958#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
2959#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
2960#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
2961#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
2962#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
2963#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
2964#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
2965#define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
2966#define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
2967 __le16 reserved2[3];
2968};
2969
2970struct eth_vport_tpa_param {
Manish Chopra088c8612016-03-04 12:35:05 -05002971 u8 tpa_ipv4_en_flg;
2972 u8 tpa_ipv6_en_flg;
2973 u8 tpa_ipv4_tunn_en_flg;
2974 u8 tpa_ipv6_tunn_en_flg;
2975 u8 tpa_pkt_split_flg;
2976 u8 tpa_hdr_data_split_flg;
2977 u8 tpa_gro_consistent_flg;
2978 u8 tpa_max_aggs_num;
2979 u16 tpa_max_size;
2980 u16 tpa_min_size_to_start;
2981 u16 tpa_min_size_to_cont;
2982 u8 max_buff_num;
2983 u8 reserved;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002984};
2985
2986struct eth_vport_tx_mode {
2987 __le16 state;
2988#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
2989#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
2990#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
2991#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
2992#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
2993#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
2994#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
2995#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
2996#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
2997#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
2998#define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
2999#define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
3000 __le16 reserved2[3];
3001};
3002
3003struct rx_queue_start_ramrod_data {
3004 __le16 rx_queue_id;
3005 __le16 num_of_pbl_pages;
3006 __le16 bd_max_bytes;
3007 __le16 sb_id;
3008 u8 sb_index;
3009 u8 vport_id;
3010 u8 default_rss_queue_flg;
3011 u8 complete_cqe_flg;
3012 u8 complete_event_flg;
3013 u8 stats_counter_id;
3014 u8 pin_context;
3015 u8 pxp_tph_valid_bd;
3016 u8 pxp_tph_valid_pkt;
3017 u8 pxp_st_hint;
3018 __le16 pxp_st_index;
3019 u8 pmd_mode;
3020 u8 notify_en;
3021 u8 toggle_val;
3022 u8 reserved[7];
3023 __le16 reserved1;
3024 struct regpair cqe_pbl_addr;
3025 struct regpair bd_base;
3026 struct regpair reserved2;
3027};
3028
3029struct rx_queue_stop_ramrod_data {
3030 __le16 rx_queue_id;
3031 u8 complete_cqe_flg;
3032 u8 complete_event_flg;
3033 u8 vport_id;
3034 u8 reserved[3];
3035};
3036
3037struct rx_queue_update_ramrod_data {
3038 __le16 rx_queue_id;
3039 u8 complete_cqe_flg;
3040 u8 complete_event_flg;
3041 u8 vport_id;
3042 u8 reserved[4];
3043 u8 reserved1;
3044 u8 reserved2;
3045 u8 reserved3;
3046 __le16 reserved4;
3047 __le16 reserved5;
3048 struct regpair reserved6;
3049};
3050
3051struct tx_queue_start_ramrod_data {
3052 __le16 sb_id;
3053 u8 sb_index;
3054 u8 vport_id;
3055 u8 reserved0;
3056 u8 stats_counter_id;
3057 __le16 qm_pq_id;
3058 u8 flags;
3059#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
3060#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
3061#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
3062#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
3063#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
3064#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
3065#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
3066#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
3067#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
3068#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
3069#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
3070#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
3071#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
3072#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
3073 u8 pxp_st_hint;
3074 u8 pxp_tph_valid_bd;
3075 u8 pxp_tph_valid_pkt;
3076 __le16 pxp_st_index;
3077 __le16 comp_agg_size;
3078 __le16 queue_zone_id;
3079 __le16 test_dup_count;
3080 __le16 pbl_size;
3081 __le16 tx_queue_id;
3082 struct regpair pbl_base_addr;
3083 struct regpair bd_cons_address;
3084};
3085
3086struct tx_queue_stop_ramrod_data {
3087 __le16 reserved[4];
3088};
3089
3090struct vport_filter_update_ramrod_data {
3091 struct eth_filter_cmd_header filter_cmd_hdr;
3092 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
3093};
3094
3095struct vport_start_ramrod_data {
3096 u8 vport_id;
3097 u8 sw_fid;
3098 __le16 mtu;
3099 u8 drop_ttl0_en;
3100 u8 inner_vlan_removal_en;
3101 struct eth_vport_rx_mode rx_mode;
3102 struct eth_vport_tx_mode tx_mode;
3103 struct eth_vport_tpa_param tpa_param;
3104 __le16 default_vlan;
3105 u8 tx_switching_en;
3106 u8 anti_spoofing_en;
3107 u8 default_vlan_en;
3108 u8 handle_ptp_pkts;
3109 u8 silent_vlan_removal_en;
3110 u8 untagged;
3111 struct eth_tx_err_vals tx_err_behav;
3112 u8 zero_placement_offset;
3113 u8 reserved[7];
3114};
3115
3116struct vport_stop_ramrod_data {
3117 u8 vport_id;
3118 u8 reserved[7];
3119};
3120
3121struct vport_update_ramrod_data_cmn {
3122 u8 vport_id;
3123 u8 update_rx_active_flg;
3124 u8 rx_active_flg;
3125 u8 update_tx_active_flg;
3126 u8 tx_active_flg;
3127 u8 update_rx_mode_flg;
3128 u8 update_tx_mode_flg;
3129 u8 update_approx_mcast_flg;
3130 u8 update_rss_flg;
3131 u8 update_inner_vlan_removal_en_flg;
3132 u8 inner_vlan_removal_en;
3133 u8 update_tpa_param_flg;
3134 u8 update_tpa_en_flg;
3135 u8 update_tx_switching_en_flg;
3136 u8 tx_switching_en;
3137 u8 update_anti_spoofing_en_flg;
3138 u8 anti_spoofing_en;
3139 u8 update_handle_ptp_pkts;
3140 u8 handle_ptp_pkts;
3141 u8 update_default_vlan_en_flg;
3142 u8 default_vlan_en;
3143 u8 update_default_vlan_flg;
3144 __le16 default_vlan;
3145 u8 update_accept_any_vlan_flg;
3146 u8 accept_any_vlan;
3147 u8 silent_vlan_removal_en;
3148 u8 update_mtu_flg;
3149 __le16 mtu;
3150 u8 reserved[2];
3151};
3152
3153struct vport_update_ramrod_mcast {
3154 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
3155};
3156
3157struct vport_update_ramrod_data {
3158 struct vport_update_ramrod_data_cmn common;
3159 struct eth_vport_rx_mode rx_mode;
3160 struct eth_vport_tx_mode tx_mode;
3161 struct eth_vport_tpa_param tpa_param;
3162 struct vport_update_ramrod_mcast approx_mcast;
3163 struct eth_vport_rss_config rss_config;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003164};
3165
3166#define VF_MAX_STATIC 192 /* In case of K2 */
3167
3168#define MCP_GLOB_PATH_MAX 2
3169#define MCP_PORT_MAX 2 /* Global */
3170#define MCP_GLOB_PORT_MAX 4 /* Global */
3171#define MCP_GLOB_FUNC_MAX 16 /* Global */
3172
3173typedef u32 offsize_t; /* In DWORDS !!! */
3174/* Offset from the beginning of the MCP scratchpad */
3175#define OFFSIZE_OFFSET_SHIFT 0
3176#define OFFSIZE_OFFSET_MASK 0x0000ffff
3177/* Size of specific element (not the whole array if any) */
3178#define OFFSIZE_SIZE_SHIFT 16
3179#define OFFSIZE_SIZE_MASK 0xffff0000
3180
3181/* SECTION_OFFSET is calculating the offset in bytes out of offsize */
3182#define SECTION_OFFSET(_offsize) ((((_offsize & \
3183 OFFSIZE_OFFSET_MASK) >> \
3184 OFFSIZE_OFFSET_SHIFT) << 2))
3185
3186/* QED_SECTION_SIZE is calculating the size in bytes out of offsize */
3187#define QED_SECTION_SIZE(_offsize) (((_offsize & \
3188 OFFSIZE_SIZE_MASK) >> \
3189 OFFSIZE_SIZE_SHIFT) << 2)
3190
3191/* SECTION_ADDR returns the GRC addr of a section, given offsize and index
3192 * within section.
3193 */
3194#define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \
3195 SECTION_OFFSET(_offsize) + \
3196 (QED_SECTION_SIZE(_offsize) * idx))
3197
3198/* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address.
3199 * Use offsetof, since the OFFSETUP collide with the firmware definition
3200 */
3201#define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base + \
3202 offsetof(struct \
3203 mcp_public_data, \
3204 sections[_section]))
3205/* PHY configuration */
3206struct pmm_phy_cfg {
3207 u32 speed;
3208#define PMM_SPEED_AUTONEG 0
3209
3210 u32 pause; /* bitmask */
3211#define PMM_PAUSE_NONE 0x0
3212#define PMM_PAUSE_AUTONEG 0x1
3213#define PMM_PAUSE_RX 0x2
3214#define PMM_PAUSE_TX 0x4
3215
3216 u32 adv_speed; /* Default should be the speed_cap_mask */
3217 u32 loopback_mode;
3218#define PMM_LOOPBACK_NONE 0
3219#define PMM_LOOPBACK_INT_PHY 1
3220#define PMM_LOOPBACK_EXT_PHY 2
3221#define PMM_LOOPBACK_EXT 3
3222#define PMM_LOOPBACK_MAC 4
3223
3224 /* features */
3225 u32 feature_config_flags;
3226};
3227
3228struct port_mf_cfg {
3229 u32 dynamic_cfg; /* device control channel */
3230#define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
3231#define PORT_MF_CFG_OV_TAG_SHIFT 0
3232#define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
3233
3234 u32 reserved[1];
3235};
3236
3237/* DO NOT add new fields in the middle
3238 * MUST be synced with struct pmm_stats_map
3239 */
3240struct pmm_stats {
3241 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
3242 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
3243 u64 r255;
3244 u64 r511;
3245 u64 r1023;
3246 u64 r1518;
3247 u64 r1522;
3248 u64 r2047;
3249 u64 r4095;
3250 u64 r9216;
3251 u64 r16383;
3252 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
3253 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/
3254 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/
3255 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
3256 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/
3257 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */
3258 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
3259 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */
3260 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */
3261 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */
3262 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
3263 u64 t127;
3264 u64 t255;
3265 u64 t511;
3266 u64 t1023;
3267 u64 t1518;
3268 u64 t2047;
3269 u64 t4095;
3270 u64 t9216;
3271 u64 t16383;
3272 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */
3273 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */
3274 u64 tlpiec;
3275 u64 tncl;
3276 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */
3277 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */
3278 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */
3279 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */
3280 u64 rxpok;
3281 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */
3282 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */
3283 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */
3284 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */
3285 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */
3286};
3287
3288struct brb_stats {
3289 u64 brb_truncate[8];
3290 u64 brb_discard[8];
3291};
3292
3293struct port_stats {
3294 struct brb_stats brb;
3295 struct pmm_stats pmm;
3296};
3297
3298#define CMT_TEAM0 0
3299#define CMT_TEAM1 1
3300#define CMT_TEAM_MAX 2
3301
3302struct couple_mode_teaming {
3303 u8 port_cmt[MCP_GLOB_PORT_MAX];
3304#define PORT_CMT_IN_TEAM BIT(0)
3305
3306#define PORT_CMT_PORT_ROLE BIT(1)
3307#define PORT_CMT_PORT_INACTIVE (0 << 1)
3308#define PORT_CMT_PORT_ACTIVE BIT(1)
3309
3310#define PORT_CMT_TEAM_MASK BIT(2)
3311#define PORT_CMT_TEAM0 (0 << 2)
3312#define PORT_CMT_TEAM1 BIT(2)
3313};
3314
3315/**************************************
3316* LLDP and DCBX HSI structures
3317**************************************/
3318#define LLDP_CHASSIS_ID_STAT_LEN 4
3319#define LLDP_PORT_ID_STAT_LEN 4
3320#define DCBX_MAX_APP_PROTOCOL 32
3321#define MAX_SYSTEM_LLDP_TLV_DATA 32
3322
3323enum lldp_agent_e {
3324 LLDP_NEAREST_BRIDGE = 0,
3325 LLDP_NEAREST_NON_TPMR_BRIDGE,
3326 LLDP_NEAREST_CUSTOMER_BRIDGE,
3327 LLDP_MAX_LLDP_AGENTS
3328};
3329
3330struct lldp_config_params_s {
3331 u32 config;
3332#define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
3333#define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
3334#define LLDP_CONFIG_HOLD_MASK 0x00000f00
3335#define LLDP_CONFIG_HOLD_SHIFT 8
3336#define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
3337#define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
3338#define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
3339#define LLDP_CONFIG_ENABLE_RX_SHIFT 30
3340#define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
3341#define LLDP_CONFIG_ENABLE_TX_SHIFT 31
3342 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3343 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
3344};
3345
3346struct lldp_status_params_s {
3347 u32 prefix_seq_num;
3348 u32 status; /* TBD */
3349
3350 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
3351 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3352
3353 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
3354 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
3355 u32 suffix_seq_num;
3356};
3357
3358struct dcbx_ets_feature {
3359 u32 flags;
3360#define DCBX_ETS_ENABLED_MASK 0x00000001
3361#define DCBX_ETS_ENABLED_SHIFT 0
3362#define DCBX_ETS_WILLING_MASK 0x00000002
3363#define DCBX_ETS_WILLING_SHIFT 1
3364#define DCBX_ETS_ERROR_MASK 0x00000004
3365#define DCBX_ETS_ERROR_SHIFT 2
3366#define DCBX_ETS_CBS_MASK 0x00000008
3367#define DCBX_ETS_CBS_SHIFT 3
3368#define DCBX_ETS_MAX_TCS_MASK 0x000000f0
3369#define DCBX_ETS_MAX_TCS_SHIFT 4
3370 u32 pri_tc_tbl[1];
3371#define DCBX_ISCSI_OOO_TC 4
3372#define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_ISCSI_OOO_TC + 1)
3373 u32 tc_bw_tbl[2];
3374 u32 tc_tsa_tbl[2];
3375#define DCBX_ETS_TSA_STRICT 0
3376#define DCBX_ETS_TSA_CBS 1
3377#define DCBX_ETS_TSA_ETS 2
3378};
3379
3380struct dcbx_app_priority_entry {
3381 u32 entry;
3382#define DCBX_APP_PRI_MAP_MASK 0x000000ff
3383#define DCBX_APP_PRI_MAP_SHIFT 0
3384#define DCBX_APP_PRI_0 0x01
3385#define DCBX_APP_PRI_1 0x02
3386#define DCBX_APP_PRI_2 0x04
3387#define DCBX_APP_PRI_3 0x08
3388#define DCBX_APP_PRI_4 0x10
3389#define DCBX_APP_PRI_5 0x20
3390#define DCBX_APP_PRI_6 0x40
3391#define DCBX_APP_PRI_7 0x80
3392#define DCBX_APP_SF_MASK 0x00000300
3393#define DCBX_APP_SF_SHIFT 8
3394#define DCBX_APP_SF_ETHTYPE 0
3395#define DCBX_APP_SF_PORT 1
3396#define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
3397#define DCBX_APP_PROTOCOL_ID_SHIFT 16
3398};
3399
3400/* FW structure in BE */
3401struct dcbx_app_priority_feature {
3402 u32 flags;
3403#define DCBX_APP_ENABLED_MASK 0x00000001
3404#define DCBX_APP_ENABLED_SHIFT 0
3405#define DCBX_APP_WILLING_MASK 0x00000002
3406#define DCBX_APP_WILLING_SHIFT 1
3407#define DCBX_APP_ERROR_MASK 0x00000004
3408#define DCBX_APP_ERROR_SHIFT 2
3409/* Not in use
3410 * #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00
3411 * #define DCBX_APP_DEFAULT_PRI_SHIFT 8
3412 */
3413#define DCBX_APP_MAX_TCS_MASK 0x0000f000
3414#define DCBX_APP_MAX_TCS_SHIFT 12
3415#define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
3416#define DCBX_APP_NUM_ENTRIES_SHIFT 16
3417 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
3418};
3419
3420/* FW structure in BE */
3421struct dcbx_features {
3422 /* PG feature */
3423 struct dcbx_ets_feature ets;
3424
3425 /* PFC feature */
3426 u32 pfc;
3427#define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
3428#define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
3429#define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
3430#define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
3431#define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
3432#define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
3433#define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
3434#define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
3435#define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
3436#define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
3437
3438#define DCBX_PFC_FLAGS_MASK 0x0000ff00
3439#define DCBX_PFC_FLAGS_SHIFT 8
3440#define DCBX_PFC_CAPS_MASK 0x00000f00
3441#define DCBX_PFC_CAPS_SHIFT 8
3442#define DCBX_PFC_MBC_MASK 0x00004000
3443#define DCBX_PFC_MBC_SHIFT 14
3444#define DCBX_PFC_WILLING_MASK 0x00008000
3445#define DCBX_PFC_WILLING_SHIFT 15
3446#define DCBX_PFC_ENABLED_MASK 0x00010000
3447#define DCBX_PFC_ENABLED_SHIFT 16
3448#define DCBX_PFC_ERROR_MASK 0x00020000
3449#define DCBX_PFC_ERROR_SHIFT 17
3450
3451 /* APP feature */
3452 struct dcbx_app_priority_feature app;
3453};
3454
3455struct dcbx_local_params {
3456 u32 config;
3457#define DCBX_CONFIG_VERSION_MASK 0x00000003
3458#define DCBX_CONFIG_VERSION_SHIFT 0
3459#define DCBX_CONFIG_VERSION_DISABLED 0
3460#define DCBX_CONFIG_VERSION_IEEE 1
3461#define DCBX_CONFIG_VERSION_CEE 2
3462
3463 u32 flags;
3464 struct dcbx_features features;
3465};
3466
3467struct dcbx_mib {
3468 u32 prefix_seq_num;
3469 u32 flags;
3470 struct dcbx_features features;
3471 u32 suffix_seq_num;
3472};
3473
3474struct lldp_system_tlvs_buffer_s {
3475 u16 valid;
3476 u16 length;
3477 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
3478};
3479
3480/**************************************/
3481/* */
3482/* P U B L I C G L O B A L */
3483/* */
3484/**************************************/
3485struct public_global {
3486 u32 max_path;
3487#define MAX_PATH_BIG_BEAR 2
3488#define MAX_PATH_K2 1
3489 u32 max_ports;
3490#define MODE_1P 1
3491#define MODE_2P 2
3492#define MODE_3P 3
3493#define MODE_4P 4
3494 u32 debug_mb_offset;
3495 u32 phymod_dbg_mb_offset;
3496 struct couple_mode_teaming cmt;
3497 s32 internal_temperature;
3498 u32 mfw_ver;
3499 u32 running_bundle_id;
3500};
3501
3502/**************************************/
3503/* */
3504/* P U B L I C P A T H */
3505/* */
3506/**************************************/
3507
3508/****************************************************************************
3509* Shared Memory 2 Region *
3510****************************************************************************/
3511/* The fw_flr_ack is actually built in the following way: */
3512/* 8 bit: PF ack */
3513/* 128 bit: VF ack */
3514/* 8 bit: ios_dis_ack */
3515/* In order to maintain endianity in the mailbox hsi, we want to keep using */
3516/* u32. The fw must have the VF right after the PF since this is how it */
3517/* access arrays(it expects always the VF to reside after the PF, and that */
3518/* makes the calculation much easier for it. ) */
3519/* In order to answer both limitations, and keep the struct small, the code */
3520/* will abuse the structure defined here to achieve the actual partition */
3521/* above */
3522/****************************************************************************/
3523struct fw_flr_mb {
3524 u32 aggint;
3525 u32 opgen_addr;
3526 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
3527#define ACCUM_ACK_PF_BASE 0
3528#define ACCUM_ACK_PF_SHIFT 0
3529
3530#define ACCUM_ACK_VF_BASE 8
3531#define ACCUM_ACK_VF_SHIFT 3
3532
3533#define ACCUM_ACK_IOV_DIS_BASE 256
3534#define ACCUM_ACK_IOV_DIS_SHIFT 8
3535};
3536
3537struct public_path {
3538 struct fw_flr_mb flr_mb;
3539 u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
3540
3541 u32 process_kill;
3542#define PROCESS_KILL_COUNTER_MASK 0x0000ffff
3543#define PROCESS_KILL_COUNTER_SHIFT 0
3544#define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
3545#define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
3546#define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
3547};
3548
3549/**************************************/
3550/* */
3551/* P U B L I C P O R T */
3552/* */
3553/**************************************/
3554
3555/****************************************************************************
3556* Driver <-> FW Mailbox *
3557****************************************************************************/
3558
3559struct public_port {
3560 u32 validity_map; /* 0x0 (4*2 = 0x8) */
3561
3562 /* validity bits */
3563#define MCP_VALIDITY_PCI_CFG 0x00100000
3564#define MCP_VALIDITY_MB 0x00200000
3565#define MCP_VALIDITY_DEV_INFO 0x00400000
3566#define MCP_VALIDITY_RESERVED 0x00000007
3567
3568 /* One licensing bit should be set */
3569#define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
3570#define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
3571#define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
3572#define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
3573
3574 /* Active MFW */
3575#define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
3576#define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
3577#define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040
3578#define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
3579
3580 u32 link_status;
3581#define LINK_STATUS_LINK_UP \
3582 0x00000001
3583#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
3584#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD BIT(1)
3585#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
3586#define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
3587#define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
3588#define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
3589#define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
3590#define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
3591#define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
3592
3593#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
3594
3595#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
3596#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
3597
3598#define LINK_STATUS_PFC_ENABLED \
3599 0x00000100
3600#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
3601#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
3602#define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
3603#define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
3604#define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
3605#define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
3606#define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
3607#define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
3608
3609#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
3610#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
3611#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE BIT(18)
3612#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
3613#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
3614
3615#define LINK_STATUS_SFP_TX_FAULT \
3616 0x00100000
3617#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
3618#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
3619
3620 u32 link_status1;
3621 u32 ext_phy_fw_version;
3622 u32 drv_phy_cfg_addr;
3623
3624 u32 port_stx;
3625
3626 u32 stat_nig_timer;
3627
3628 struct port_mf_cfg port_mf_config;
3629 struct port_stats stats;
3630
3631 u32 media_type;
3632#define MEDIA_UNSPECIFIED 0x0
3633#define MEDIA_SFPP_10G_FIBER 0x1
3634#define MEDIA_XFP_FIBER 0x2
3635#define MEDIA_DA_TWINAX 0x3
3636#define MEDIA_BASE_T 0x4
3637#define MEDIA_SFP_1G_FIBER 0x5
3638#define MEDIA_KR 0xf0
3639#define MEDIA_NOT_PRESENT 0xff
3640
3641 u32 lfa_status;
3642#define LFA_LINK_FLAP_REASON_OFFSET 0
3643#define LFA_LINK_FLAP_REASON_MASK 0x000000ff
3644#define LFA_NO_REASON (0 << 0)
3645#define LFA_LINK_DOWN BIT(0)
3646#define LFA_FORCE_INIT BIT(1)
3647#define LFA_LOOPBACK_MISMATCH BIT(2)
3648#define LFA_SPEED_MISMATCH BIT(3)
3649#define LFA_FLOW_CTRL_MISMATCH BIT(4)
3650#define LFA_ADV_SPEED_MISMATCH BIT(5)
3651#define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
3652#define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
3653#define LINK_FLAP_COUNT_OFFSET 16
3654#define LINK_FLAP_COUNT_MASK 0x00ff0000
3655
3656 u32 link_change_count;
3657
3658 /* LLDP params */
3659 struct lldp_config_params_s lldp_config_params[
3660 LLDP_MAX_LLDP_AGENTS];
3661 struct lldp_status_params_s lldp_status_params[
3662 LLDP_MAX_LLDP_AGENTS];
3663 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
3664
3665 /* DCBX related MIB */
3666 struct dcbx_local_params local_admin_dcbx_mib;
3667 struct dcbx_mib remote_dcbx_mib;
3668 struct dcbx_mib operational_dcbx_mib;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05003669
3670 u32 fc_npiv_nvram_tbl_addr;
3671 u32 fc_npiv_nvram_tbl_size;
3672 u32 transceiver_data;
Zvi Nachmani334c03b2016-03-09 09:16:25 +02003673#define PMM_TRANSCEIVER_STATE_MASK 0x000000FF
3674#define PMM_TRANSCEIVER_STATE_SHIFT 0x00000000
3675#define PMM_TRANSCEIVER_STATE_PRESENT 0x00000001
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003676};
3677
3678/**************************************/
3679/* */
3680/* P U B L I C F U N C */
3681/* */
3682/**************************************/
3683
3684struct public_func {
3685 u32 iscsi_boot_signature;
3686 u32 iscsi_boot_block_offset;
3687
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05003688 u32 mtu_size;
3689 u32 c2s_pcp_map_lower;
3690 u32 c2s_pcp_map_upper;
3691 u32 c2s_pcp_map_default;
3692 u32 reserved[4];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003693
3694 u32 config;
3695
3696 /* E/R/I/D */
3697 /* function 0 of each port cannot be hidden */
3698#define FUNC_MF_CFG_FUNC_HIDE 0x00000001
3699#define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
3700#define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
3701
3702#define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
3703#define FUNC_MF_CFG_PROTOCOL_SHIFT 4
3704#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
3705#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
3706#define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
3707#define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
3708#define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
3709
3710 /* MINBW, MAXBW */
3711 /* value range - 0..100, increments in 1 % */
3712#define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
3713#define FUNC_MF_CFG_MIN_BW_SHIFT 8
3714#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
3715#define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
3716#define FUNC_MF_CFG_MAX_BW_SHIFT 16
3717#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
3718
3719 u32 status;
3720#define FUNC_STATUS_VLINK_DOWN 0x00000001
3721
3722 u32 mac_upper; /* MAC */
3723#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
3724#define FUNC_MF_CFG_UPPERMAC_SHIFT 0
3725#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
3726 u32 mac_lower;
3727#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
3728
3729 u32 fcoe_wwn_port_name_upper;
3730 u32 fcoe_wwn_port_name_lower;
3731
3732 u32 fcoe_wwn_node_name_upper;
3733 u32 fcoe_wwn_node_name_lower;
3734
3735 u32 ovlan_stag; /* tags */
3736#define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
3737#define FUNC_MF_CFG_OV_STAG_SHIFT 0
3738#define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
3739
3740 u32 pf_allocation; /* vf per pf */
3741
3742 u32 preserve_data; /* Will be used bt CCM */
3743
3744 u32 driver_last_activity_ts;
3745
3746 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */
3747
3748 u32 drv_id;
3749#define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
3750#define DRV_ID_PDA_COMP_VER_SHIFT 0
3751
3752#define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
3753#define DRV_ID_MCP_HSI_VER_SHIFT 16
3754#define DRV_ID_MCP_HSI_VER_CURRENT BIT(DRV_ID_MCP_HSI_VER_SHIFT)
3755
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05003756#define DRV_ID_DRV_TYPE_MASK 0x7f000000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003757#define DRV_ID_DRV_TYPE_SHIFT 24
3758#define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05003759#define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003760#define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT)
3761#define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT)
3762#define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT)
3763#define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT)
3764#define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT)
3765#define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT)
3766#define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT)
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05003767
3768#define DRV_ID_DRV_INIT_HW_MASK 0x80000000
3769#define DRV_ID_DRV_INIT_HW_SHIFT 31
3770#define DRV_ID_DRV_INIT_HW_FLAG BIT(DRV_ID_DRV_INIT_HW_SHIFT)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003771};
3772
3773/**************************************/
3774/* */
3775/* P U B L I C M B */
3776/* */
3777/**************************************/
3778/* This is the only section that the driver can write to, and each */
3779/* Basically each driver request to set feature parameters,
3780 * will be done using a different command, which will be linked
3781 * to a specific data structure from the union below.
3782 * For huge strucuture, the common blank structure should be used.
3783 */
3784
3785struct mcp_mac {
3786 u32 mac_upper; /* Upper 16 bits are always zeroes */
3787 u32 mac_lower;
3788};
3789
3790struct mcp_val64 {
3791 u32 lo;
3792 u32 hi;
3793};
3794
3795struct mcp_file_att {
3796 u32 nvm_start_addr;
3797 u32 len;
3798};
3799
3800#define MCP_DRV_VER_STR_SIZE 16
3801#define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
3802#define MCP_DRV_NVM_BUF_LEN 32
3803struct drv_version_stc {
3804 u32 version;
3805 u8 name[MCP_DRV_VER_STR_SIZE - 4];
3806};
3807
3808union drv_union_data {
3809 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
3810 struct mcp_mac wol_mac;
3811
3812 struct pmm_phy_cfg drv_phy_cfg;
3813
3814 struct mcp_val64 val64; /* For PHY / AVS commands */
3815
3816 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
3817
3818 struct mcp_file_att file_att;
3819
3820 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
3821
3822 struct drv_version_stc drv_version;
3823};
3824
3825struct public_drv_mb {
3826 u32 drv_mb_header;
3827#define DRV_MSG_CODE_MASK 0xffff0000
3828#define DRV_MSG_CODE_LOAD_REQ 0x10000000
3829#define DRV_MSG_CODE_LOAD_DONE 0x11000000
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05003830#define DRV_MSG_CODE_INIT_HW 0x12000000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003831#define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
3832#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
3833#define DRV_MSG_CODE_INIT_PHY 0x22000000
3834 /* Params - FORCE - Reinitialize the link regardless of LFA */
3835 /* - DONT_CARE - Don't flap the link if up */
3836#define DRV_MSG_CODE_LINK_RESET 0x23000000
3837
3838#define DRV_MSG_CODE_SET_LLDP 0x24000000
3839#define DRV_MSG_CODE_SET_DCBX 0x25000000
Manish Chopra4b01e512016-04-26 10:56:09 -04003840#define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003841#define DRV_MSG_CODE_NIG_DRAIN 0x30000000
3842
3843#define DRV_MSG_CODE_INITIATE_FLR 0x02000000
3844#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
3845#define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
3846#define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
3847#define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
3848#define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
3849#define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
3850#define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
3851#define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000
3852#define DRV_MSG_CODE_MCP_RESET 0x00090000
3853#define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000
3854#define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000
3855#define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000
3856#define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000
3857#define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000
3858#define DRV_MSG_CODE_SET_VERSION 0x000f0000
3859
Sudarsana Reddy Kalluru03dc76c2016-04-28 20:20:52 -04003860#define DRV_MSG_CODE_BIST_TEST 0x001e0000
Sudarsana Kalluru91420b82015-11-30 12:25:03 +02003861#define DRV_MSG_CODE_SET_LED_MODE 0x00200000
3862
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003863#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
3864
3865 u32 drv_mb_param;
3866
3867 /* UNLOAD_REQ params */
3868#define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
3869#define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
3870#define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
3871#define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
3872
3873 /* UNLOAD_DONE_params */
3874#define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001
3875
3876 /* INIT_PHY params */
3877#define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001
3878#define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002
3879
3880 /* LLDP / DCBX params*/
3881#define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
3882#define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
3883#define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006
3884#define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1
3885#define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008
3886#define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
3887
3888#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
3889#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0
3890
3891#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
3892#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
3893
3894#define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0
3895#define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
3896#define DRV_MB_PARAM_NVM_LEN_SHIFT 24
3897#define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
3898
3899#define DRV_MB_PARAM_PHY_ADDR_SHIFT 0
3900#define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF
3901#define DRV_MB_PARAM_PHY_LANE_SHIFT 16
3902#define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000
3903#define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29
3904#define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000
3905#define DRV_MB_PARAM_PHY_PORT_SHIFT 30
3906#define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000
3907
3908/* configure vf MSIX params*/
3909#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
3910#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
3911#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
3912#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
3913
Sudarsana Kalluru91420b82015-11-30 12:25:03 +02003914#define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
3915#define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
3916#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
3917
Sudarsana Reddy Kalluru03dc76c2016-04-28 20:20:52 -04003918#define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0
3919#define DRV_MB_PARAM_BIST_REGISTER_TEST 1
3920#define DRV_MB_PARAM_BIST_CLOCK_TEST 2
3921
3922#define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
3923#define DRV_MB_PARAM_BIST_RC_PASSED 1
3924#define DRV_MB_PARAM_BIST_RC_FAILED 2
3925#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
3926
3927#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
3928#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
3929
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003930 u32 fw_mb_header;
3931#define FW_MSG_CODE_MASK 0xffff0000
3932#define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
3933#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
3934#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
3935#define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
3936#define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10210000
3937#define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
3938#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
3939#define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
3940#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
3941#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
3942#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
3943#define FW_MSG_CODE_INIT_PHY_DONE 0x21200000
3944#define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000
3945#define FW_MSG_CODE_LINK_RESET_DONE 0x23000000
3946#define FW_MSG_CODE_SET_LLDP_DONE 0x24000000
3947#define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000
3948#define FW_MSG_CODE_SET_DCBX_DONE 0x25000000
3949#define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000
3950#define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
3951#define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
3952#define FW_MSG_CODE_FLR_ACK 0x02000000
3953#define FW_MSG_CODE_FLR_NACK 0x02100000
3954
3955#define FW_MSG_CODE_NVM_OK 0x00010000
3956#define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000
3957#define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000
3958#define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
3959#define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000
3960#define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000
3961#define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
3962#define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
3963#define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000
3964#define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000
3965#define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000
3966#define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000
3967#define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000
3968#define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000
3969#define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000
3970#define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000
3971#define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000
3972#define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000
3973#define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
3974#define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000
3975#define FW_MSG_CODE_PHY_OK 0x00110000
3976#define FW_MSG_CODE_PHY_ERROR 0x00120000
3977#define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000
3978#define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000
3979#define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05003980#define FW_MSG_CODE_OK 0x00160000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003981
3982#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
3983
3984 u32 fw_mb_param;
3985
3986 u32 drv_pulse_mb;
3987#define DRV_PULSE_SEQ_MASK 0x00007fff
3988#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
3989#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
3990 u32 mcp_pulse_mb;
3991#define MCP_PULSE_SEQ_MASK 0x00007fff
3992#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
3993#define MCP_EVENT_MASK 0xffff0000
3994#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
3995
3996 union drv_union_data union_data;
3997};
3998
3999/* MFW - DRV MB */
4000/**********************************************************************
4001* Description
4002* Incremental Aggregative
4003* 8-bit MFW counter per message
4004* 8-bit ack-counter per message
4005* Capabilities
4006* Provides up to 256 aggregative message per type
4007* Provides 4 message types in dword
4008* Message type pointers to byte offset
4009* Backward Compatibility by using sizeof for the counters.
4010* No lock requires for 32bit messages
4011* Limitations:
4012* In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
4013* is required to prevent data corruption.
4014**********************************************************************/
4015enum MFW_DRV_MSG_TYPE {
4016 MFW_DRV_MSG_LINK_CHANGE,
4017 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
4018 MFW_DRV_MSG_VF_DISABLED,
4019 MFW_DRV_MSG_LLDP_DATA_UPDATED,
4020 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
4021 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
4022 MFW_DRV_MSG_ERROR_RECOVERY,
Zvi Nachmani334c03b2016-03-09 09:16:25 +02004023 MFW_DRV_MSG_BW_UPDATE,
4024 MFW_DRV_MSG_S_TAG_UPDATE,
4025 MFW_DRV_MSG_GET_LAN_STATS,
4026 MFW_DRV_MSG_GET_FCOE_STATS,
4027 MFW_DRV_MSG_GET_ISCSI_STATS,
4028 MFW_DRV_MSG_GET_RDMA_STATS,
4029 MFW_DRV_MSG_FAILURE_DETECTED,
4030 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004031 MFW_DRV_MSG_MAX
4032};
4033
4034#define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
4035#define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
4036#define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
4037#define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
4038
4039struct public_mfw_mb {
4040 u32 sup_msgs;
4041 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
4042 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
4043};
4044
4045/**************************************/
4046/* */
4047/* P U B L I C D A T A */
4048/* */
4049/**************************************/
4050enum public_sections {
4051 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */
4052 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */
4053 PUBLIC_GLOBAL,
4054 PUBLIC_PATH,
4055 PUBLIC_PORT,
4056 PUBLIC_FUNC,
4057 PUBLIC_MAX_SECTIONS
4058};
4059
4060struct drv_ver_info_stc {
4061 u32 ver;
4062 u8 name[32];
4063};
4064
4065struct mcp_public_data {
4066 /* The sections fields is an array */
4067 u32 num_sections;
4068 offsize_t sections[PUBLIC_MAX_SECTIONS];
4069 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
4070 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
4071 struct public_global global;
4072 struct public_path path[MCP_GLOB_PATH_MAX];
4073 struct public_port port[MCP_GLOB_PORT_MAX];
4074 struct public_func func[MCP_GLOB_FUNC_MAX];
4075 struct drv_ver_info_stc drv_info;
4076};
4077
4078struct nvm_cfg_mac_address {
4079 u32 mac_addr_hi;
4080#define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
4081#define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
4082
4083 u32 mac_addr_lo;
4084};
4085
4086/******************************************
4087* nvm_cfg1 structs
4088******************************************/
4089
4090struct nvm_cfg1_glob {
4091 u32 generic_cont0; /* 0x0 */
4092#define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
4093#define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
4094#define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
4095#define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
4096#define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
4097#define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
4098#define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
4099#define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
4100#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004101#define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004102#define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
4103#define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
4104#define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
4105#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
4106#define NVM_CFG1_GLOB_MF_MODE_BD 0x6
4107#define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
4108#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000
4109#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12
4110#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0
4111#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1
4112#define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000
4113#define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13
4114#define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000
4115#define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21
4116#define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000
4117#define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29
4118#define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0
4119#define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1
4120#define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000
4121#define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30
4122#define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0
4123#define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1
4124#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000
4125#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31
4126#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0
4127#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1
4128
4129 u32 engineering_change[3]; /* 0x4 */
4130
4131 u32 manufacturing_id; /* 0x10 */
4132
4133 u32 serial_number[4]; /* 0x14 */
4134
4135 u32 pcie_cfg; /* 0x24 */
4136#define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003
4137#define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0
4138#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0
4139#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1
4140#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2
4141#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004
4142#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2
4143#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0
4144#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1
4145#define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
4146#define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
4147#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
4148#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1
4149#define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
4150#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3
4151#define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_MASK 0x00000020
4152#define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_OFFSET 5
4153#define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_DISABLED 0x0
4154#define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_ENABLED 0x1
4155#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
4156#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
4157#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00
4158#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10
4159#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0
4160#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1
4161#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2
4162#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3
4163#define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000
4164#define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13
4165#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000
4166#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
4167#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
4168#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
4169
4170 u32 mgmt_traffic; /* 0x28 */
4171#define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
4172#define NVM_CFG1_GLOB_RESERVED60_OFFSET 0
4173#define NVM_CFG1_GLOB_RESERVED60_100KHZ 0x0
4174#define NVM_CFG1_GLOB_RESERVED60_400KHZ 0x1
4175#define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE
4176#define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1
4177#define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00
4178#define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9
4179#define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000
4180#define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17
4181#define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000
4182#define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25
4183#define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0
4184#define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1
4185#define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2
4186
4187 u32 core_cfg; /* 0x2C */
4188#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
4189#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
4190#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G 0x0
4191#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G 0x1
4192#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G 0x2
4193#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F 0x3
4194#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E 0x4
4195#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G 0x5
4196#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G 0xB
4197#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G 0xC
4198#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G 0xD
4199#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_MASK 0x00000100
4200#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_OFFSET 8
4201#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_DISABLED 0x0
4202#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_ENABLED 0x1
4203#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_MASK 0x00000200
4204#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_OFFSET 9
4205#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_DISABLED 0x0
4206#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_ENABLED 0x1
4207#define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_MASK 0x0003FC00
4208#define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_OFFSET 10
4209#define NVM_CFG1_GLOB_FALCON_CORE_ADDR_MASK 0x03FC0000
4210#define NVM_CFG1_GLOB_FALCON_CORE_ADDR_OFFSET 18
4211#define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
4212#define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
4213#define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
4214#define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP 0x1
4215#define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3
4216#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000
4217#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29
4218#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0
4219#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1
4220
4221 u32 e_lane_cfg1; /* 0x30 */
4222#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
4223#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
4224#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
4225#define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
4226#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
4227#define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
4228#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
4229#define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
4230#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
4231#define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
4232#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
4233#define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
4234#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
4235#define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
4236#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
4237#define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
4238
4239 u32 e_lane_cfg2; /* 0x34 */
4240#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
4241#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
4242#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
4243#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
4244#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
4245#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
4246#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
4247#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
4248#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
4249#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
4250#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
4251#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
4252#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
4253#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
4254#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
4255#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
4256#define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00
4257#define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8
4258#define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0
4259#define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1
4260#define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2
4261#define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000
4262#define NVM_CFG1_GLOB_NCSI_OFFSET 12
4263#define NVM_CFG1_GLOB_NCSI_DISABLED 0x0
4264#define NVM_CFG1_GLOB_NCSI_ENABLED 0x1
4265
4266 u32 f_lane_cfg1; /* 0x38 */
4267#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
4268#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
4269#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
4270#define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
4271#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
4272#define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
4273#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
4274#define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
4275#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
4276#define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
4277#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
4278#define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
4279#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
4280#define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
4281#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
4282#define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
4283
4284 u32 f_lane_cfg2; /* 0x3C */
4285#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
4286#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
4287#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
4288#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
4289#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
4290#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
4291#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
4292#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
4293#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
4294#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
4295#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
4296#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
4297#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
4298#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
4299#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
4300#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
4301
4302 u32 eagle_preemphasis; /* 0x40 */
4303#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
4304#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
4305#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
4306#define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
4307#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
4308#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
4309#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
4310#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
4311
4312 u32 eagle_driver_current; /* 0x44 */
4313#define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
4314#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
4315#define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
4316#define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
4317#define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
4318#define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
4319#define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
4320#define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
4321
4322 u32 falcon_preemphasis; /* 0x48 */
4323#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
4324#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
4325#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
4326#define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
4327#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
4328#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
4329#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
4330#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
4331
4332 u32 falcon_driver_current; /* 0x4C */
4333#define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
4334#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
4335#define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
4336#define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
4337#define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
4338#define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
4339#define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
4340#define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
4341
4342 u32 pci_id; /* 0x50 */
4343#define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF
4344#define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0
4345
4346 u32 pci_subsys_id; /* 0x54 */
4347#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF
4348#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0
4349#define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000
4350#define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16
4351
4352 u32 bar; /* 0x58 */
4353#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F
4354#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0
4355#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0
4356#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1
4357#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2
4358#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3
4359#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4
4360#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5
4361#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6
4362#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7
4363#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8
4364#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9
4365#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA
4366#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB
4367#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC
4368#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD
4369#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE
4370#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF
4371#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0
4372#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4
4373#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0
4374#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1
4375#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2
4376#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3
4377#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4
4378#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5
4379#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6
4380#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7
4381#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8
4382#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9
4383#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA
4384#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB
4385#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC
4386#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD
4387#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE
4388#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF
4389#define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00
4390#define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8
4391#define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0
4392#define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1
4393#define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2
4394#define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3
4395#define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4
4396#define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5
4397#define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6
4398#define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7
4399#define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8
4400#define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9
4401#define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA
4402#define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB
4403#define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC
4404#define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
4405#define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
4406#define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
4407
4408 u32 eagle_txfir_main; /* 0x5C */
4409#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
4410#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
4411#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
4412#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
4413#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
4414#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
4415#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
4416#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
4417
4418 u32 eagle_txfir_post; /* 0x60 */
4419#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
4420#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
4421#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
4422#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
4423#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
4424#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
4425#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
4426#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
4427
4428 u32 falcon_txfir_main; /* 0x64 */
4429#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
4430#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
4431#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
4432#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
4433#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
4434#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
4435#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
4436#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
4437
4438 u32 falcon_txfir_post; /* 0x68 */
4439#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
4440#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
4441#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
4442#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
4443#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
4444#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
4445#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
4446#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
4447
4448 u32 manufacture_ver; /* 0x6C */
4449#define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F
4450#define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0
4451#define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0
4452#define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6
4453#define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000
4454#define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12
4455#define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000
4456#define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18
4457#define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000
4458#define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24
4459
4460 u32 manufacture_time; /* 0x70 */
4461#define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F
4462#define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0
4463#define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0
4464#define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6
4465#define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000
4466#define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12
4467
4468 u32 led_global_settings; /* 0x74 */
4469#define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F
4470#define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0
4471#define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0
4472#define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4
4473#define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00
4474#define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8
4475#define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000
4476#define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12
4477
4478 u32 generic_cont1; /* 0x78 */
4479#define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
4480#define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
4481
4482 u32 mbi_version; /* 0x7C */
4483#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
4484#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
4485#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
4486#define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
4487#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
4488#define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
4489
4490 u32 mbi_date; /* 0x80 */
4491
4492 u32 misc_sig; /* 0x84 */
4493
4494 /* Define the GPIO mapping to switch i2c mux */
4495#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF
4496#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0
4497#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00
4498#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8
4499#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0
4500#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1
4501#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2
4502#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3
4503#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4
4504#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5
4505#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6
4506#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7
4507#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8
4508#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9
4509#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA
4510#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB
4511#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC
4512#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD
4513#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE
4514#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF
4515#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10
4516#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11
4517#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12
4518#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13
4519#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14
4520#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15
4521#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16
4522#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17
4523#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18
4524#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19
4525#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A
4526#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B
4527#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C
4528#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D
4529#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E
4530#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F
4531#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004532 u32 device_capabilities; /* 0x88 */
4533#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
4534 u32 power_dissipated; /* 0x8C */
4535 u32 power_consumed; /* 0x90 */
4536 u32 efi_version; /* 0x94 */
4537 u32 reserved[42]; /* 0x98 */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004538};
4539
4540struct nvm_cfg1_path {
4541 u32 reserved[30]; /* 0x0 */
4542};
4543
4544struct nvm_cfg1_port {
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004545 u32 reserved__m_relocated_to_option_123; /* 0x0 */
4546 u32 reserved__m_relocated_to_option_124; /* 0x4 */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004547 u32 generic_cont0; /* 0x8 */
4548#define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF
4549#define NVM_CFG1_PORT_LED_MODE_OFFSET 0
4550#define NVM_CFG1_PORT_LED_MODE_MAC1 0x0
4551#define NVM_CFG1_PORT_LED_MODE_PHY1 0x1
4552#define NVM_CFG1_PORT_LED_MODE_PHY2 0x2
4553#define NVM_CFG1_PORT_LED_MODE_PHY3 0x3
4554#define NVM_CFG1_PORT_LED_MODE_MAC2 0x4
4555#define NVM_CFG1_PORT_LED_MODE_PHY4 0x5
4556#define NVM_CFG1_PORT_LED_MODE_PHY5 0x6
4557#define NVM_CFG1_PORT_LED_MODE_PHY6 0x7
4558#define NVM_CFG1_PORT_LED_MODE_MAC3 0x8
4559#define NVM_CFG1_PORT_LED_MODE_PHY7 0x9
4560#define NVM_CFG1_PORT_LED_MODE_PHY8 0xA
4561#define NVM_CFG1_PORT_LED_MODE_PHY9 0xB
4562#define NVM_CFG1_PORT_LED_MODE_MAC4 0xC
4563#define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
4564#define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
4565#define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
4566#define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00
4567#define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8
4568#define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
4569#define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
4570#define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
4571#define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
4572#define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
4573#define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004574#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
4575#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
4576#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004577 u32 pcie_cfg; /* 0xC */
4578#define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
4579#define NVM_CFG1_PORT_RESERVED15_OFFSET 0
4580
4581 u32 features; /* 0x10 */
4582#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001
4583#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0
4584#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0
4585#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1
4586#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002
4587#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1
4588#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0
4589#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1
4590
4591 u32 speed_cap_mask; /* 0x14 */
4592#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
4593#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
4594#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
4595#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
4596#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
4597#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
4598#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
4599#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G 0x40
4600#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
4601#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
4602#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
4603#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2
4604#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
4605#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
4606#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
4607#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_100G 0x40
4608
4609 u32 link_settings; /* 0x18 */
4610#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
4611#define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
4612#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
4613#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
4614#define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
4615#define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
4616#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
4617#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
4618#define NVM_CFG1_PORT_DRV_LINK_SPEED_100G 0x7
4619#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
4620#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
4621#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
4622#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
4623#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
4624#define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780
4625#define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7
4626#define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0
4627#define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1
4628#define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2
4629#define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
4630#define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
4631#define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
4632#define NVM_CFG1_PORT_MFW_LINK_SPEED_100G 0x7
4633#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
4634#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
4635#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
4636#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
4637#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
4638#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000
4639#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
4640#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0
4641#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1
4642
4643 u32 phy_cfg; /* 0x1C */
4644#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
4645#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
4646#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1
4647#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2
4648#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4
4649#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8
4650#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10
4651#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000
4652#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16
4653#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0
4654#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2
4655#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3
4656#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4
4657#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8
4658#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9
4659#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB
4660#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004661#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11
4662#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12
4663#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21
4664#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22
4665#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004666#define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000
4667#define NVM_CFG1_PORT_AN_MODE_OFFSET 24
4668#define NVM_CFG1_PORT_AN_MODE_NONE 0x0
4669#define NVM_CFG1_PORT_AN_MODE_CL73 0x1
4670#define NVM_CFG1_PORT_AN_MODE_CL37 0x2
4671#define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
4672#define NVM_CFG1_PORT_AN_MODE_CL37_BAM 0x4
4673#define NVM_CFG1_PORT_AN_MODE_HPAM 0x5
4674#define NVM_CFG1_PORT_AN_MODE_SGMII 0x6
4675
4676 u32 mgmt_traffic; /* 0x20 */
4677#define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
4678#define NVM_CFG1_PORT_RESERVED61_OFFSET 0
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004679
4680 u32 ext_phy; /* 0x24 */
4681#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF
4682#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0
4683#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0
4684#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844 0x1
4685#define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00
4686#define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8
4687
4688 u32 mba_cfg1; /* 0x28 */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004689#define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001
4690#define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0
4691#define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0
4692#define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1
4693#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006
4694#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004695#define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078
4696#define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3
4697#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080
4698#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7
4699#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0
4700#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1
4701#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100
4702#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8
4703#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0
4704#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1
4705#define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00
4706#define NVM_CFG1_PORT_RESERVED5_OFFSET 9
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004707#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000
4708#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17
4709#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0
4710#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1
4711#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2
4712#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4
4713#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
4714#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
4715#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_100G 0x7
4716#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8
4717#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000
4718#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004719
4720 u32 mba_cfg2; /* 0x2C */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004721#define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
4722#define NVM_CFG1_PORT_RESERVED65_OFFSET 0
4723#define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000
4724#define NVM_CFG1_PORT_RESERVED66_OFFSET 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004725
4726 u32 vf_cfg; /* 0x30 */
4727#define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF
4728#define NVM_CFG1_PORT_RESERVED8_OFFSET 0
4729#define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000
4730#define NVM_CFG1_PORT_RESERVED6_OFFSET 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004731
4732 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */
4733
4734 u32 led_port_settings; /* 0x3C */
4735#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF
4736#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0
4737#define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00
4738#define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8
4739#define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000
4740#define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16
4741#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1
4742#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2
4743#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8
4744#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10
4745#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20
4746#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_100G 0x40
4747
4748 u32 transceiver_00; /* 0x40 */
4749
4750 /* Define for mapping of transceiver signal module absent */
4751#define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
4752#define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0
4753#define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0
4754#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1
4755#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2
4756#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3
4757#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4
4758#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5
4759#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6
4760#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7
4761#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8
4762#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9
4763#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA
4764#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB
4765#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC
4766#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD
4767#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE
4768#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF
4769#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10
4770#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11
4771#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12
4772#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13
4773#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14
4774#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15
4775#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16
4776#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17
4777#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18
4778#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19
4779#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A
4780#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B
4781#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C
4782#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D
4783#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E
4784#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F
4785#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20
4786 /* Define the GPIO mux settings to switch i2c mux to this port */
4787#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00
4788#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8
4789#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000
4790#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12
4791
4792 u32 reserved[133]; /* 0x44 */
4793};
4794
4795struct nvm_cfg1_func {
4796 struct nvm_cfg_mac_address mac_address; /* 0x0 */
4797
4798 u32 rsrv1; /* 0x8 */
4799#define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF
4800#define NVM_CFG1_FUNC_RESERVED1_OFFSET 0
4801#define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000
4802#define NVM_CFG1_FUNC_RESERVED2_OFFSET 16
4803
4804 u32 rsrv2; /* 0xC */
4805#define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF
4806#define NVM_CFG1_FUNC_RESERVED3_OFFSET 0
4807#define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000
4808#define NVM_CFG1_FUNC_RESERVED4_OFFSET 16
4809
4810 u32 device_id; /* 0x10 */
4811#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF
4812#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004813#define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000
4814#define NVM_CFG1_FUNC_RESERVED77_OFFSET 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004815
4816 u32 cmn_cfg; /* 0x14 */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004817#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007
4818#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0
4819#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0
4820#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3
4821#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4
4822#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004823#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
4824#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
4825#define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
4826#define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
4827#define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
4828#define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1
4829#define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2
4830#define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3
4831#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
4832#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
4833#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
4834#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31
4835#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0
4836#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1
4837
4838 u32 pci_cfg; /* 0x18 */
4839#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
4840#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
4841#define NVM_CFG1_FUNC_RESERVESD12_MASK 0x00003F80
4842#define NVM_CFG1_FUNC_RESERVESD12_OFFSET 7
4843#define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
4844#define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
4845#define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
4846#define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1
4847#define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2
4848#define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3
4849#define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4
4850#define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5
4851#define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6
4852#define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7
4853#define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8
4854#define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9
4855#define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA
4856#define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB
4857#define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC
4858#define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD
4859#define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE
4860#define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
4861#define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
4862#define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
4863
4864 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */
4865
4866 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004867 u32 preboot_generic_cfg; /* 0x2C */
4868 u32 reserved[8]; /* 0x30 */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004869};
4870
4871struct nvm_cfg1 {
4872 struct nvm_cfg1_glob glob; /* 0x0 */
4873
4874 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x140 */
4875
4876 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */
4877
4878 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */
4879};
4880
4881/******************************************
4882* nvm_cfg structs
4883******************************************/
4884
4885enum nvm_cfg_sections {
4886 NVM_CFG_SECTION_NVM_CFG1,
4887 NVM_CFG_SECTION_MAX
4888};
4889
4890struct nvm_cfg {
4891 u32 num_sections;
4892 u32 sections_offset[NVM_CFG_SECTION_MAX];
4893 struct nvm_cfg1 cfg1;
4894};
4895
4896#define PORT_0 0
4897#define PORT_1 1
4898#define PORT_2 2
4899#define PORT_3 3
4900
4901extern struct spad_layout g_spad;
4902
4903#define MCP_SPAD_SIZE 0x00028000 /* 160 KB */
4904
4905#define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE))
4906
4907#define TO_OFFSIZE(_offset, _size) \
4908 (u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_SHIFT) | \
4909 (((u32)(_size) >> 2) << OFFSIZE_SIZE_SHIFT))
4910
4911enum spad_sections {
4912 SPAD_SECTION_TRACE,
4913 SPAD_SECTION_NVM_CFG,
4914 SPAD_SECTION_PUBLIC,
4915 SPAD_SECTION_PRIVATE,
4916 SPAD_SECTION_MAX
4917};
4918
4919struct spad_layout {
4920 struct nvm_cfg nvm_cfg;
4921 struct mcp_public_data public_data;
4922};
4923
4924#define CRC_MAGIC_VALUE 0xDEBB20E3
4925#define CRC32_POLYNOMIAL 0xEDB88320
4926#define NVM_CRC_SIZE (sizeof(u32))
4927
4928enum nvm_sw_arbitrator {
4929 NVM_SW_ARB_HOST,
4930 NVM_SW_ARB_MCP,
4931 NVM_SW_ARB_UART,
4932 NVM_SW_ARB_RESERVED
4933};
4934
4935/****************************************************************************
4936* Boot Strap Region *
4937****************************************************************************/
4938struct legacy_bootstrap_region {
4939 u32 magic_value;
4940#define NVM_MAGIC_VALUE 0x669955aa
4941 u32 sram_start_addr;
4942 u32 code_len; /* boot code length (in dwords) */
4943 u32 code_start_addr;
4944 u32 crc; /* 32-bit CRC */
4945};
4946
4947/****************************************************************************
4948* Directories Region *
4949****************************************************************************/
4950struct nvm_code_entry {
4951 u32 image_type; /* Image type */
4952 u32 nvm_start_addr; /* NVM address of the image */
4953 u32 len; /* Include CRC */
4954 u32 sram_start_addr;
4955 u32 sram_run_addr; /* Relevant in case of MIM only */
4956};
4957
4958enum nvm_image_type {
4959 NVM_TYPE_TIM1 = 0x01,
4960 NVM_TYPE_TIM2 = 0x02,
4961 NVM_TYPE_MIM1 = 0x03,
4962 NVM_TYPE_MIM2 = 0x04,
4963 NVM_TYPE_MBA = 0x05,
4964 NVM_TYPE_MODULES_PN = 0x06,
4965 NVM_TYPE_VPD = 0x07,
4966 NVM_TYPE_MFW_TRACE1 = 0x08,
4967 NVM_TYPE_MFW_TRACE2 = 0x09,
4968 NVM_TYPE_NVM_CFG1 = 0x0a,
4969 NVM_TYPE_L2B = 0x0b,
4970 NVM_TYPE_DIR1 = 0x0c,
4971 NVM_TYPE_EAGLE_FW1 = 0x0d,
4972 NVM_TYPE_FALCON_FW1 = 0x0e,
4973 NVM_TYPE_PCIE_FW1 = 0x0f,
4974 NVM_TYPE_HW_SET = 0x10,
4975 NVM_TYPE_LIM = 0x11,
4976 NVM_TYPE_AVS_FW1 = 0x12,
4977 NVM_TYPE_DIR2 = 0x13,
4978 NVM_TYPE_CCM = 0x14,
4979 NVM_TYPE_EAGLE_FW2 = 0x15,
4980 NVM_TYPE_FALCON_FW2 = 0x16,
4981 NVM_TYPE_PCIE_FW2 = 0x17,
4982 NVM_TYPE_AVS_FW2 = 0x18,
4983
4984 NVM_TYPE_MAX,
4985};
4986
4987#define MAX_NVM_DIR_ENTRIES 200
4988
4989struct nvm_dir {
4990 s32 seq;
4991#define NVM_DIR_NEXT_MFW_MASK 0x00000001
4992#define NVM_DIR_SEQ_MASK 0xfffffffe
4993#define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK)
4994
4995#define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK)
4996
4997 u32 num_images;
4998 u32 rsrv;
4999 struct nvm_code_entry code[1]; /* Up to MAX_NVM_DIR_ENTRIES */
5000};
5001
5002#define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + \
5003 (_num_images - \
5004 1) * sizeof(struct nvm_code_entry) + \
5005 NVM_CRC_SIZE)
5006
5007struct nvm_vpd_image {
5008 u32 format_revision;
5009#define VPD_IMAGE_VERSION 1
5010
5011 /* This array length depends on the number of VPD fields */
5012 u8 vpd_data[1];
5013};
5014
5015/****************************************************************************
5016* NVRAM FULL MAP *
5017****************************************************************************/
5018#define DIR_ID_1 (0)
5019#define DIR_ID_2 (1)
5020#define MAX_DIR_IDS (2)
5021
5022#define MFW_BUNDLE_1 (0)
5023#define MFW_BUNDLE_2 (1)
5024#define MAX_MFW_BUNDLES (2)
5025
5026#define FLASH_PAGE_SIZE 0x1000
5027#define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE) /* 4Kb */
5028#define ASIC_MIM_MAX_SIZE (300 * FLASH_PAGE_SIZE) /* 1.2Mb */
5029#define FPGA_MIM_MAX_SIZE (25 * FLASH_PAGE_SIZE) /* 60Kb */
5030
5031#define LIM_MAX_SIZE ((2 * \
5032 FLASH_PAGE_SIZE) - \
5033 sizeof(struct legacy_bootstrap_region) - \
5034 NVM_RSV_SIZE)
5035#define LIM_OFFSET (NVM_OFFSET(lim_image))
5036#define NVM_RSV_SIZE (44)
5037#define MIM_MAX_SIZE(is_asic) ((is_asic) ? ASIC_MIM_MAX_SIZE : \
5038 FPGA_MIM_MAX_SIZE)
5039#define MIM_OFFSET(idx, is_asic) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + \
5040 ((idx == \
5041 NVM_TYPE_MIM2) ? MIM_MAX_SIZE(is_asic) : 0))
5042#define NVM_FIXED_AREA_SIZE(is_asic) (sizeof(struct nvm_image) + \
5043 MIM_MAX_SIZE(is_asic) * 2)
5044
5045union nvm_dir_union {
5046 struct nvm_dir dir;
5047 u8 page[FLASH_PAGE_SIZE];
5048};
5049
5050/* Address
5051 * +-------------------+ 0x000000
5052 * | Bootstrap: |
5053 * | magic_number |
5054 * | sram_start_addr |
5055 * | code_len |
5056 * | code_start_addr |
5057 * | crc |
5058 * +-------------------+ 0x000014
5059 * | rsrv |
5060 * +-------------------+ 0x000040
5061 * | LIM |
5062 * +-------------------+ 0x002000
5063 * | Dir1 |
5064 * +-------------------+ 0x003000
5065 * | Dir2 |
5066 * +-------------------+ 0x004000
5067 * | MIM1 |
5068 * +-------------------+ 0x130000
5069 * | MIM2 |
5070 * +-------------------+ 0x25C000
5071 * | Rest Images: |
5072 * | TIM1/2 |
5073 * | MFW_TRACE1/2 |
5074 * | Eagle/Falcon FW |
5075 * | PCIE/AVS FW |
5076 * | MBA/CCM/L2B |
5077 * | VPD |
5078 * | optic_modules |
5079 * | ... |
5080 * +-------------------+ 0x400000
5081 */
5082struct nvm_image {
5083/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/
5084 /* NVM Offset (size) */
5085 struct legacy_bootstrap_region bootstrap;
5086 u8 rsrv[NVM_RSV_SIZE];
5087 u8 lim_image[LIM_MAX_SIZE];
5088 union nvm_dir_union dir[MAX_MFW_BUNDLES];
5089
5090 /* MIM1_IMAGE 0x004000 (0x12c000) */
5091 /* MIM2_IMAGE 0x130000 (0x12c000) */
5092/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/
5093}; /* 0x134 */
5094
5095#define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image *)0)->f))))
5096
5097struct hw_set_info {
5098 u32 reg_type;
5099#define GRC_REG_TYPE 1
5100#define PHY_REG_TYPE 2
5101#define PCI_REG_TYPE 4
5102
5103 u32 bank_num;
5104 u32 pf_num;
5105 u32 operation;
5106#define READ_OP 1
5107#define WRITE_OP 2
5108#define RMW_SET_OP 3
5109#define RMW_CLR_OP 4
5110
5111 u32 reg_addr;
5112 u32 reg_data;
5113
5114 u32 reset_type;
5115#define POR_RESET_TYPE BIT(0)
5116#define HARD_RESET_TYPE BIT(1)
5117#define CORE_RESET_TYPE BIT(2)
5118#define MCP_RESET_TYPE BIT(3)
5119#define PERSET_ASSERT BIT(4)
5120#define PERSET_DEASSERT BIT(5)
5121};
5122
5123struct hw_set_image {
5124 u32 format_version;
5125#define HW_SET_IMAGE_VERSION 1
5126 u32 no_hw_sets;
5127
5128 /* This array length depends on the no_hw_sets */
5129 struct hw_set_info hw_sets[1];
5130};
5131
Manish Chopraa64b02d2016-04-26 10:56:10 -04005132int qed_init_pf_wfq(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
5133 u8 pf_id, u16 pf_wfq);
Manish Choprabcd197c2016-04-26 10:56:08 -04005134int qed_init_vport_wfq(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
5135 u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02005136#endif