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Mikael Petterssone589ed22008-08-20 09:36:07 +01001#ifndef _ASM_ARM_FUTEX_H
2#define _ASM_ARM_FUTEX_H
3
4#ifdef __KERNEL__
5
Will Deaconc1b0db52011-04-28 18:43:01 +01006#include <linux/futex.h>
7#include <linux/uaccess.h>
8#include <asm/errno.h>
9
10#define __futex_atomic_ex_table(err_reg) \
11 "3:\n" \
12 " .pushsection __ex_table,\"a\"\n" \
13 " .align 3\n" \
14 " .long 1b, 4f, 2b, 4f\n" \
15 " .popsection\n" \
Ard Biesheuvelc4a84ae2015-03-24 10:41:09 +010016 " .pushsection .text.fixup,\"ax\"\n" \
Will Deacon667d1b42012-06-15 16:49:58 +010017 " .align 2\n" \
Will Deaconc1b0db52011-04-28 18:43:01 +010018 "4: mov %0, " err_reg "\n" \
19 " b 3b\n" \
20 " .popsection"
21
Mikael Petterssone589ed22008-08-20 09:36:07 +010022#ifdef CONFIG_SMP
Jakub Jelinek4732efb2005-09-06 15:16:25 -070023
Will Deacondf77abc2011-09-23 14:34:12 +010024#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
Will Deaconc1b0db52011-04-28 18:43:01 +010025 smp_mb(); \
Will Deaconc32ffce2014-02-21 17:01:48 +010026 prefetchw(uaddr); \
Will Deaconc1b0db52011-04-28 18:43:01 +010027 __asm__ __volatile__( \
Will Deacondf77abc2011-09-23 14:34:12 +010028 "1: ldrex %1, [%3]\n" \
Will Deaconc1b0db52011-04-28 18:43:01 +010029 " " insn "\n" \
Will Deacondf77abc2011-09-23 14:34:12 +010030 "2: strex %2, %0, [%3]\n" \
31 " teq %2, #0\n" \
Will Deaconc1b0db52011-04-28 18:43:01 +010032 " bne 1b\n" \
33 " mov %0, #0\n" \
Will Deacondf77abc2011-09-23 14:34:12 +010034 __futex_atomic_ex_table("%5") \
35 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
Will Deaconc1b0db52011-04-28 18:43:01 +010036 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
37 : "cc", "memory")
38
39static inline int
40futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
41 u32 oldval, u32 newval)
42{
43 int ret;
44 u32 val;
45
46 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
47 return -EFAULT;
48
49 smp_mb();
Will Deaconc32ffce2014-02-21 17:01:48 +010050 /* Prefetching cannot fault */
51 prefetchw(uaddr);
Will Deaconc1b0db52011-04-28 18:43:01 +010052 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
53 "1: ldrex %1, [%4]\n"
54 " teq %1, %2\n"
55 " ite eq @ explicit IT needed for the 2b label\n"
56 "2: strexeq %0, %3, [%4]\n"
57 " movne %0, #0\n"
58 " teq %0, #0\n"
59 " bne 1b\n"
60 __futex_atomic_ex_table("%5")
61 : "=&r" (ret), "=&r" (val)
62 : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
63 : "cc", "memory");
64 smp_mb();
65
66 *uval = val;
67 return ret;
68}
Jakub Jelinek4732efb2005-09-06 15:16:25 -070069
Mikael Petterssone589ed22008-08-20 09:36:07 +010070#else /* !SMP, we can work around lack of atomic ops by disabling preemption */
71
Mikael Petterssone589ed22008-08-20 09:36:07 +010072#include <linux/preempt.h>
Catalin Marinas247055a2010-09-13 16:03:21 +010073#include <asm/domain.h>
Mikael Petterssone589ed22008-08-20 09:36:07 +010074
Will Deacondf77abc2011-09-23 14:34:12 +010075#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
Mikael Petterssone589ed22008-08-20 09:36:07 +010076 __asm__ __volatile__( \
Catalin Marinas4e7682d2012-01-25 11:38:13 +010077 "1: " TUSER(ldr) " %1, [%3]\n" \
Mikael Petterssone589ed22008-08-20 09:36:07 +010078 " " insn "\n" \
Catalin Marinas4e7682d2012-01-25 11:38:13 +010079 "2: " TUSER(str) " %0, [%3]\n" \
Mikael Petterssone589ed22008-08-20 09:36:07 +010080 " mov %0, #0\n" \
Will Deacondf77abc2011-09-23 14:34:12 +010081 __futex_atomic_ex_table("%5") \
82 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
Mikael Petterssone589ed22008-08-20 09:36:07 +010083 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
84 : "cc", "memory")
85
86static inline int
Will Deaconc1b0db52011-04-28 18:43:01 +010087futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
88 u32 oldval, u32 newval)
89{
90 int ret = 0;
91 u32 val;
92
93 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
94 return -EFAULT;
95
David Hildenbrand39919b02015-05-11 17:52:15 +020096 preempt_disable();
Will Deaconc1b0db52011-04-28 18:43:01 +010097 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
Catalin Marinas4e7682d2012-01-25 11:38:13 +010098 "1: " TUSER(ldr) " %1, [%4]\n"
Will Deaconc1b0db52011-04-28 18:43:01 +010099 " teq %1, %2\n"
100 " it eq @ explicit IT needed for the 2b label\n"
Catalin Marinas4e7682d2012-01-25 11:38:13 +0100101 "2: " TUSER(streq) " %3, [%4]\n"
Will Deaconc1b0db52011-04-28 18:43:01 +0100102 __futex_atomic_ex_table("%5")
103 : "+r" (ret), "=&r" (val)
104 : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
105 : "cc", "memory");
106
107 *uval = val;
David Hildenbrand39919b02015-05-11 17:52:15 +0200108 preempt_enable();
109
Will Deaconc1b0db52011-04-28 18:43:01 +0100110 return ret;
111}
112
113#endif /* !SMP */
114
115static inline int
Michel Lespinasse8d7718a2011-03-10 18:50:58 -0800116futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
Mikael Petterssone589ed22008-08-20 09:36:07 +0100117{
118 int op = (encoded_op >> 28) & 7;
119 int cmp = (encoded_op >> 24) & 15;
120 int oparg = (encoded_op << 8) >> 20;
121 int cmparg = (encoded_op << 20) >> 20;
Will Deacondf77abc2011-09-23 14:34:12 +0100122 int oldval = 0, ret, tmp;
Mikael Petterssone589ed22008-08-20 09:36:07 +0100123
124 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
125 oparg = 1 << oparg;
126
Michel Lespinasse8d7718a2011-03-10 18:50:58 -0800127 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
Mikael Petterssone589ed22008-08-20 09:36:07 +0100128 return -EFAULT;
129
David Hildenbrand388b0e02015-05-11 17:52:16 +0200130#ifndef CONFIG_SMP
131 preempt_disable();
132#endif
133 pagefault_disable();
Mikael Petterssone589ed22008-08-20 09:36:07 +0100134
135 switch (op) {
136 case FUTEX_OP_SET:
Will Deacondf77abc2011-09-23 14:34:12 +0100137 __futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
Mikael Petterssone589ed22008-08-20 09:36:07 +0100138 break;
139 case FUTEX_OP_ADD:
Will Deacondf77abc2011-09-23 14:34:12 +0100140 __futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
Mikael Petterssone589ed22008-08-20 09:36:07 +0100141 break;
142 case FUTEX_OP_OR:
Will Deacondf77abc2011-09-23 14:34:12 +0100143 __futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
Mikael Petterssone589ed22008-08-20 09:36:07 +0100144 break;
145 case FUTEX_OP_ANDN:
Will Deacondf77abc2011-09-23 14:34:12 +0100146 __futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
Mikael Petterssone589ed22008-08-20 09:36:07 +0100147 break;
148 case FUTEX_OP_XOR:
Will Deacondf77abc2011-09-23 14:34:12 +0100149 __futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
Mikael Petterssone589ed22008-08-20 09:36:07 +0100150 break;
151 default:
152 ret = -ENOSYS;
153 }
154
David Hildenbrand388b0e02015-05-11 17:52:16 +0200155 pagefault_enable();
156#ifndef CONFIG_SMP
157 preempt_enable();
158#endif
Mikael Petterssone589ed22008-08-20 09:36:07 +0100159
160 if (!ret) {
161 switch (cmp) {
162 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
163 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
164 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
165 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
166 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
167 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
168 default: ret = -ENOSYS;
169 }
170 }
171 return ret;
172}
173
Mikael Petterssone589ed22008-08-20 09:36:07 +0100174#endif /* __KERNEL__ */
175#endif /* _ASM_ARM_FUTEX_H */