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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Ralf Baechle70342282013-01-22 12:59:30 +01002 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
Ralf Baechlec539ef72012-01-11 15:37:16 +01007 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 2011 Wind River Systems,
9 * written by Ralf Baechle (ralf@linux-mips.org)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 */
Ralf Baechlec539ef72012-01-11 15:37:16 +010011#include <linux/bug.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/kernel.h>
13#include <linux/mm.h>
14#include <linux/bootmem.h>
Paul Gortmakercae39d12011-07-28 18:46:31 -040015#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <linux/init.h>
17#include <linux/types.h>
18#include <linux/pci.h>
John Crispina48cf372012-05-04 10:50:13 +020019#include <linux/of_address.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
Ralf Baechlec539ef72012-01-11 15:37:16 +010021#include <asm/cpu-info.h>
22
Ralf Baechle982f6ff2009-09-17 02:25:07 +020023unsigned long PCIBIOS_MIN_IO;
Paul Burtonf8091a82016-10-05 18:18:11 +010024EXPORT_SYMBOL(PCIBIOS_MIN_IO);
25
Ralf Baechle982f6ff2009-09-17 02:25:07 +020026unsigned long PCIBIOS_MIN_MEM;
Paul Burtonf8091a82016-10-05 18:18:11 +010027EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Paul Burtonf474ba92016-10-05 18:18:09 +010029static int __init pcibios_set_cache_line_size(void)
Ralf Baechlec539ef72012-01-11 15:37:16 +010030{
Ralf Baechlec539ef72012-01-11 15:37:16 +010031 unsigned int lsize;
32
33 /*
34 * Set PCI cacheline size to that of the highest level in the
35 * cache hierarchy.
36 */
Matt Redfearn73530262017-07-26 08:41:09 +010037 lsize = cpu_dcache_line_size();
38 lsize = cpu_scache_line_size() ? : lsize;
39 lsize = cpu_tcache_line_size() ? : lsize;
Ralf Baechlec539ef72012-01-11 15:37:16 +010040
41 BUG_ON(!lsize);
42
43 pci_dfl_cache_line_size = lsize >> 2;
44
45 pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
Paul Burtonf474ba92016-10-05 18:18:09 +010046 return 0;
Ralf Baechlec539ef72012-01-11 15:37:16 +010047}
Paul Burtonf474ba92016-10-05 18:18:09 +010048arch_initcall(pcibios_set_cache_line_size);
Ralf Baechlec539ef72012-01-11 15:37:16 +010049
Bjorn Helgaas8221a012016-06-17 14:43:34 -050050void pci_resource_to_user(const struct pci_dev *dev, int bar,
51 const struct resource *rsrc, resource_size_t *start,
52 resource_size_t *end)
53{
54 phys_addr_t size = resource_size(rsrc);
55
56 *start = fixup_bigphys_addr(rsrc->start, size);
Paul Burton38c0a742018-07-12 09:33:04 -070057 *end = rsrc->start + size - 1;
Bjorn Helgaas8221a012016-06-17 14:43:34 -050058}