blob: daad2bf2cb651eccbb18be727be394a08410e4a1 [file] [log] [blame]
Hariprasad Shenai324429d2016-08-17 12:33:05 +05301/*
2 * This file is part of the Chelsio T6 Crypto driver for Linux.
3 *
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 *
34 * Written and Maintained by:
35 * Manoj Malviya (manojmalviya@chelsio.com)
36 * Atul Gupta (atul.gupta@chelsio.com)
37 * Jitendra Lulla (jlulla@chelsio.com)
38 * Yeshaswi M R Gowda (yeshaswi@chelsio.com)
39 * Harsh Jain (harsh@chelsio.com)
40 */
41
42#define pr_fmt(fmt) "chcr:" fmt
43
44#include <linux/kernel.h>
45#include <linux/module.h>
46#include <linux/crypto.h>
47#include <linux/cryptohash.h>
48#include <linux/skbuff.h>
49#include <linux/rtnetlink.h>
50#include <linux/highmem.h>
51#include <linux/scatterlist.h>
52
53#include <crypto/aes.h>
54#include <crypto/algapi.h>
55#include <crypto/hash.h>
56#include <crypto/sha.h>
57#include <crypto/internal/hash.h>
58
59#include "t4fw_api.h"
60#include "t4_msg.h"
61#include "chcr_core.h"
62#include "chcr_algo.h"
63#include "chcr_crypto.h"
64
65static inline struct ablk_ctx *ABLK_CTX(struct chcr_context *ctx)
66{
67 return ctx->crypto_ctx->ablkctx;
68}
69
70static inline struct hmac_ctx *HMAC_CTX(struct chcr_context *ctx)
71{
72 return ctx->crypto_ctx->hmacctx;
73}
74
75static inline struct uld_ctx *ULD_CTX(struct chcr_context *ctx)
76{
77 return ctx->dev->u_ctx;
78}
79
80static inline int is_ofld_imm(const struct sk_buff *skb)
81{
82 return (skb->len <= CRYPTO_MAX_IMM_TX_PKT_LEN);
83}
84
85/*
86 * sgl_len - calculates the size of an SGL of the given capacity
87 * @n: the number of SGL entries
88 * Calculates the number of flits needed for a scatter/gather list that
89 * can hold the given number of entries.
90 */
91static inline unsigned int sgl_len(unsigned int n)
92{
93 n--;
94 return (3 * n) / 2 + (n & 1) + 2;
95}
96
97/*
98 * chcr_handle_resp - Unmap the DMA buffers associated with the request
99 * @req: crypto request
100 */
101int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
102 int error_status)
103{
104 struct crypto_tfm *tfm = req->tfm;
105 struct chcr_context *ctx = crypto_tfm_ctx(tfm);
106 struct uld_ctx *u_ctx = ULD_CTX(ctx);
107 struct chcr_req_ctx ctx_req;
108 struct cpl_fw6_pld *fw6_pld;
109 unsigned int digestsize, updated_digestsize;
110
111 switch (tfm->__crt_alg->cra_flags & CRYPTO_ALG_TYPE_MASK) {
112 case CRYPTO_ALG_TYPE_BLKCIPHER:
113 ctx_req.req.ablk_req = (struct ablkcipher_request *)req;
114 ctx_req.ctx.ablk_ctx =
115 ablkcipher_request_ctx(ctx_req.req.ablk_req);
116 if (!error_status) {
117 fw6_pld = (struct cpl_fw6_pld *)input;
118 memcpy(ctx_req.req.ablk_req->info, &fw6_pld->data[2],
119 AES_BLOCK_SIZE);
120 }
121 dma_unmap_sg(&u_ctx->lldi.pdev->dev, ctx_req.req.ablk_req->dst,
122 ABLK_CTX(ctx)->dst_nents, DMA_FROM_DEVICE);
123 if (ctx_req.ctx.ablk_ctx->skb) {
124 kfree_skb(ctx_req.ctx.ablk_ctx->skb);
125 ctx_req.ctx.ablk_ctx->skb = NULL;
126 }
127 break;
128
129 case CRYPTO_ALG_TYPE_AHASH:
130 ctx_req.req.ahash_req = (struct ahash_request *)req;
131 ctx_req.ctx.ahash_ctx =
132 ahash_request_ctx(ctx_req.req.ahash_req);
133 digestsize =
134 crypto_ahash_digestsize(crypto_ahash_reqtfm(
135 ctx_req.req.ahash_req));
136 updated_digestsize = digestsize;
137 if (digestsize == SHA224_DIGEST_SIZE)
138 updated_digestsize = SHA256_DIGEST_SIZE;
139 else if (digestsize == SHA384_DIGEST_SIZE)
140 updated_digestsize = SHA512_DIGEST_SIZE;
141 if (ctx_req.ctx.ahash_ctx->skb)
142 ctx_req.ctx.ahash_ctx->skb = NULL;
143 if (ctx_req.ctx.ahash_ctx->result == 1) {
144 ctx_req.ctx.ahash_ctx->result = 0;
145 memcpy(ctx_req.req.ahash_req->result, input +
146 sizeof(struct cpl_fw6_pld),
147 digestsize);
148 } else {
149 memcpy(ctx_req.ctx.ahash_ctx->partial_hash, input +
150 sizeof(struct cpl_fw6_pld),
151 updated_digestsize);
152 }
153 kfree(ctx_req.ctx.ahash_ctx->dummy_payload_ptr);
154 ctx_req.ctx.ahash_ctx->dummy_payload_ptr = NULL;
155 break;
156 }
157 return 0;
158}
159
160/*
161 * calc_tx_flits_ofld - calculate # of flits for an offload packet
162 * @skb: the packet
163 * Returns the number of flits needed for the given offload packet.
164 * These packets are already fully constructed and no additional headers
165 * will be added.
166 */
167static inline unsigned int calc_tx_flits_ofld(const struct sk_buff *skb)
168{
169 unsigned int flits, cnt;
170
171 if (is_ofld_imm(skb))
172 return DIV_ROUND_UP(skb->len, 8);
173
174 flits = skb_transport_offset(skb) / 8; /* headers */
175 cnt = skb_shinfo(skb)->nr_frags;
176 if (skb_tail_pointer(skb) != skb_transport_header(skb))
177 cnt++;
178 return flits + sgl_len(cnt);
179}
180
Harsh Jain39f91a32016-11-29 19:00:35 +0530181static inline void get_aes_decrypt_key(unsigned char *dec_key,
182 const unsigned char *key,
183 unsigned int keylength)
184{
185 u32 temp;
186 u32 w_ring[MAX_NK];
187 int i, j, k;
188 u8 nr, nk;
189
190 switch (keylength) {
191 case AES_KEYLENGTH_128BIT:
192 nk = KEYLENGTH_4BYTES;
193 nr = NUMBER_OF_ROUNDS_10;
194 break;
195 case AES_KEYLENGTH_192BIT:
196 nk = KEYLENGTH_6BYTES;
197 nr = NUMBER_OF_ROUNDS_12;
198 break;
199 case AES_KEYLENGTH_256BIT:
200 nk = KEYLENGTH_8BYTES;
201 nr = NUMBER_OF_ROUNDS_14;
202 break;
203 default:
204 return;
205 }
206 for (i = 0; i < nk; i++)
207 w_ring[i] = be32_to_cpu(*(u32 *)&key[4 * i]);
208
209 i = 0;
210 temp = w_ring[nk - 1];
211 while (i + nk < (nr + 1) * 4) {
212 if (!(i % nk)) {
213 /* RotWord(temp) */
214 temp = (temp << 8) | (temp >> 24);
215 temp = aes_ks_subword(temp);
216 temp ^= round_constant[i / nk];
217 } else if (nk == 8 && (i % 4 == 0)) {
218 temp = aes_ks_subword(temp);
219 }
220 w_ring[i % nk] ^= temp;
221 temp = w_ring[i % nk];
222 i++;
223 }
224 i--;
225 for (k = 0, j = i % nk; k < nk; k++) {
226 *((u32 *)dec_key + k) = htonl(w_ring[j]);
227 j--;
228 if (j < 0)
229 j += nk;
230 }
231}
232
Hariprasad Shenai324429d2016-08-17 12:33:05 +0530233static struct shash_desc *chcr_alloc_shash(unsigned int ds)
234{
235 struct crypto_shash *base_hash = NULL;
236 struct shash_desc *desc;
237
238 switch (ds) {
239 case SHA1_DIGEST_SIZE:
240 base_hash = crypto_alloc_shash("sha1-generic", 0, 0);
241 break;
242 case SHA224_DIGEST_SIZE:
243 base_hash = crypto_alloc_shash("sha224-generic", 0, 0);
244 break;
245 case SHA256_DIGEST_SIZE:
246 base_hash = crypto_alloc_shash("sha256-generic", 0, 0);
247 break;
248 case SHA384_DIGEST_SIZE:
249 base_hash = crypto_alloc_shash("sha384-generic", 0, 0);
250 break;
251 case SHA512_DIGEST_SIZE:
252 base_hash = crypto_alloc_shash("sha512-generic", 0, 0);
253 break;
254 }
255 if (IS_ERR(base_hash)) {
256 pr_err("Can not allocate sha-generic algo.\n");
257 return (void *)base_hash;
258 }
259
260 desc = kmalloc(sizeof(*desc) + crypto_shash_descsize(base_hash),
261 GFP_KERNEL);
262 if (!desc)
263 return ERR_PTR(-ENOMEM);
264 desc->tfm = base_hash;
265 desc->flags = crypto_shash_get_flags(base_hash);
266 return desc;
267}
268
269static int chcr_compute_partial_hash(struct shash_desc *desc,
270 char *iopad, char *result_hash,
271 int digest_size)
272{
273 struct sha1_state sha1_st;
274 struct sha256_state sha256_st;
275 struct sha512_state sha512_st;
276 int error;
277
278 if (digest_size == SHA1_DIGEST_SIZE) {
279 error = crypto_shash_init(desc) ?:
280 crypto_shash_update(desc, iopad, SHA1_BLOCK_SIZE) ?:
281 crypto_shash_export(desc, (void *)&sha1_st);
282 memcpy(result_hash, sha1_st.state, SHA1_DIGEST_SIZE);
283 } else if (digest_size == SHA224_DIGEST_SIZE) {
284 error = crypto_shash_init(desc) ?:
285 crypto_shash_update(desc, iopad, SHA256_BLOCK_SIZE) ?:
286 crypto_shash_export(desc, (void *)&sha256_st);
287 memcpy(result_hash, sha256_st.state, SHA256_DIGEST_SIZE);
288
289 } else if (digest_size == SHA256_DIGEST_SIZE) {
290 error = crypto_shash_init(desc) ?:
291 crypto_shash_update(desc, iopad, SHA256_BLOCK_SIZE) ?:
292 crypto_shash_export(desc, (void *)&sha256_st);
293 memcpy(result_hash, sha256_st.state, SHA256_DIGEST_SIZE);
294
295 } else if (digest_size == SHA384_DIGEST_SIZE) {
296 error = crypto_shash_init(desc) ?:
297 crypto_shash_update(desc, iopad, SHA512_BLOCK_SIZE) ?:
298 crypto_shash_export(desc, (void *)&sha512_st);
299 memcpy(result_hash, sha512_st.state, SHA512_DIGEST_SIZE);
300
301 } else if (digest_size == SHA512_DIGEST_SIZE) {
302 error = crypto_shash_init(desc) ?:
303 crypto_shash_update(desc, iopad, SHA512_BLOCK_SIZE) ?:
304 crypto_shash_export(desc, (void *)&sha512_st);
305 memcpy(result_hash, sha512_st.state, SHA512_DIGEST_SIZE);
306 } else {
307 error = -EINVAL;
308 pr_err("Unknown digest size %d\n", digest_size);
309 }
310 return error;
311}
312
313static void chcr_change_order(char *buf, int ds)
314{
315 int i;
316
317 if (ds == SHA512_DIGEST_SIZE) {
318 for (i = 0; i < (ds / sizeof(u64)); i++)
319 *((__be64 *)buf + i) =
320 cpu_to_be64(*((u64 *)buf + i));
321 } else {
322 for (i = 0; i < (ds / sizeof(u32)); i++)
323 *((__be32 *)buf + i) =
324 cpu_to_be32(*((u32 *)buf + i));
325 }
326}
327
328static inline int is_hmac(struct crypto_tfm *tfm)
329{
330 struct crypto_alg *alg = tfm->__crt_alg;
331 struct chcr_alg_template *chcr_crypto_alg =
332 container_of(__crypto_ahash_alg(alg), struct chcr_alg_template,
333 alg.hash);
334 if ((chcr_crypto_alg->type & CRYPTO_ALG_SUB_TYPE_MASK) ==
335 CRYPTO_ALG_SUB_TYPE_HASH_HMAC)
336 return 1;
337 return 0;
338}
339
340static inline unsigned int ch_nents(struct scatterlist *sg,
341 unsigned int *total_size)
342{
343 unsigned int nents;
344
345 for (nents = 0, *total_size = 0; sg; sg = sg_next(sg)) {
346 nents++;
347 *total_size += sg->length;
348 }
349 return nents;
350}
351
352static void write_phys_cpl(struct cpl_rx_phys_dsgl *phys_cpl,
353 struct scatterlist *sg,
354 struct phys_sge_parm *sg_param)
355{
356 struct phys_sge_pairs *to;
357 unsigned int out_buf_size = sg_param->obsize;
358 unsigned int nents = sg_param->nents, i, j, tot_len = 0;
359
360 phys_cpl->op_to_tid = htonl(CPL_RX_PHYS_DSGL_OPCODE_V(CPL_RX_PHYS_DSGL)
361 | CPL_RX_PHYS_DSGL_ISRDMA_V(0));
362 phys_cpl->pcirlxorder_to_noofsgentr =
363 htonl(CPL_RX_PHYS_DSGL_PCIRLXORDER_V(0) |
364 CPL_RX_PHYS_DSGL_PCINOSNOOP_V(0) |
365 CPL_RX_PHYS_DSGL_PCITPHNTENB_V(0) |
366 CPL_RX_PHYS_DSGL_PCITPHNT_V(0) |
367 CPL_RX_PHYS_DSGL_DCAID_V(0) |
368 CPL_RX_PHYS_DSGL_NOOFSGENTR_V(nents));
369 phys_cpl->rss_hdr_int.opcode = CPL_RX_PHYS_ADDR;
370 phys_cpl->rss_hdr_int.qid = htons(sg_param->qid);
371 phys_cpl->rss_hdr_int.hash_val = 0;
372 to = (struct phys_sge_pairs *)((unsigned char *)phys_cpl +
373 sizeof(struct cpl_rx_phys_dsgl));
374
375 for (i = 0; nents; to++) {
376 for (j = i; (nents && (j < (8 + i))); j++, nents--) {
377 to->len[j] = htons(sg->length);
378 to->addr[j] = cpu_to_be64(sg_dma_address(sg));
379 if (out_buf_size) {
380 if (tot_len + sg_dma_len(sg) >= out_buf_size) {
381 to->len[j] = htons(out_buf_size -
382 tot_len);
383 return;
384 }
385 tot_len += sg_dma_len(sg);
386 }
387 sg = sg_next(sg);
388 }
389 }
390}
391
392static inline unsigned
393int map_writesg_phys_cpl(struct device *dev, struct cpl_rx_phys_dsgl *phys_cpl,
394 struct scatterlist *sg, struct phys_sge_parm *sg_param)
395{
396 if (!sg || !sg_param->nents)
397 return 0;
398
399 sg_param->nents = dma_map_sg(dev, sg, sg_param->nents, DMA_FROM_DEVICE);
400 if (sg_param->nents == 0) {
401 pr_err("CHCR : DMA mapping failed\n");
402 return -EINVAL;
403 }
404 write_phys_cpl(phys_cpl, sg, sg_param);
405 return 0;
406}
407
408static inline int get_cryptoalg_subtype(struct crypto_tfm *tfm)
409{
410 struct crypto_alg *alg = tfm->__crt_alg;
411 struct chcr_alg_template *chcr_crypto_alg =
412 container_of(alg, struct chcr_alg_template, alg.crypto);
413
414 return chcr_crypto_alg->type & CRYPTO_ALG_SUB_TYPE_MASK;
415}
416
417static inline void
418write_sg_data_page_desc(struct sk_buff *skb, unsigned int *frags,
419 struct scatterlist *sg, unsigned int count)
420{
421 struct page *spage;
422 unsigned int page_len;
423
424 skb->len += count;
425 skb->data_len += count;
426 skb->truesize += count;
427 while (count > 0) {
428 if (sg && (!(sg->length)))
429 break;
430 spage = sg_page(sg);
431 get_page(spage);
432 page_len = min(sg->length, count);
433 skb_fill_page_desc(skb, *frags, spage, sg->offset, page_len);
434 (*frags)++;
435 count -= page_len;
436 sg = sg_next(sg);
437 }
438}
439
440static int generate_copy_rrkey(struct ablk_ctx *ablkctx,
441 struct _key_ctx *key_ctx)
442{
443 if (ablkctx->ciph_mode == CHCR_SCMD_CIPHER_MODE_AES_CBC) {
444 get_aes_decrypt_key(key_ctx->key, ablkctx->key,
445 ablkctx->enckey_len << 3);
446 memset(key_ctx->key + ablkctx->enckey_len, 0,
447 CHCR_AES_MAX_KEY_LEN - ablkctx->enckey_len);
448 } else {
449 memcpy(key_ctx->key,
450 ablkctx->key + (ablkctx->enckey_len >> 1),
451 ablkctx->enckey_len >> 1);
452 get_aes_decrypt_key(key_ctx->key + (ablkctx->enckey_len >> 1),
453 ablkctx->key, ablkctx->enckey_len << 2);
454 }
455 return 0;
456}
457
458static inline void create_wreq(struct chcr_context *ctx,
459 struct fw_crypto_lookaside_wr *wreq,
460 void *req, struct sk_buff *skb,
461 int kctx_len, int hash_sz,
462 unsigned int phys_dsgl)
463{
464 struct uld_ctx *u_ctx = ULD_CTX(ctx);
465 struct ulp_txpkt *ulptx = (struct ulp_txpkt *)(wreq + 1);
466 struct ulptx_idata *sc_imm = (struct ulptx_idata *)(ulptx + 1);
467 int iv_loc = IV_DSGL;
468 int qid = u_ctx->lldi.rxq_ids[ctx->tx_channel_id];
469 unsigned int immdatalen = 0, nr_frags = 0;
470
471 if (is_ofld_imm(skb)) {
472 immdatalen = skb->data_len;
473 iv_loc = IV_IMMEDIATE;
474 } else {
475 nr_frags = skb_shinfo(skb)->nr_frags;
476 }
477
478 wreq->op_to_cctx_size = FILL_WR_OP_CCTX_SIZE(immdatalen,
479 (kctx_len >> 4));
480 wreq->pld_size_hash_size =
481 htonl(FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(sgl_lengths[nr_frags]) |
482 FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(hash_sz));
483 wreq->len16_pkd = htonl(FW_CRYPTO_LOOKASIDE_WR_LEN16_V(DIV_ROUND_UP(
484 (calc_tx_flits_ofld(skb) * 8), 16)));
485 wreq->cookie = cpu_to_be64((uintptr_t)req);
486 wreq->rx_chid_to_rx_q_id =
487 FILL_WR_RX_Q_ID(ctx->dev->tx_channel_id, qid,
488 (hash_sz) ? IV_NOP : iv_loc);
489
490 ulptx->cmd_dest = FILL_ULPTX_CMD_DEST(ctx->dev->tx_channel_id);
491 ulptx->len = htonl((DIV_ROUND_UP((calc_tx_flits_ofld(skb) * 8),
492 16) - ((sizeof(*wreq)) >> 4)));
493
494 sc_imm->cmd_more = FILL_CMD_MORE(immdatalen);
495 sc_imm->len = cpu_to_be32(sizeof(struct cpl_tx_sec_pdu) + kctx_len +
496 ((hash_sz) ? DUMMY_BYTES :
497 (sizeof(struct cpl_rx_phys_dsgl) +
498 phys_dsgl)) + immdatalen);
499}
500
501/**
502 * create_cipher_wr - form the WR for cipher operations
503 * @req: cipher req.
504 * @ctx: crypto driver context of the request.
505 * @qid: ingress qid where response of this WR should be received.
506 * @op_type: encryption or decryption
507 */
508static struct sk_buff
509*create_cipher_wr(struct crypto_async_request *req_base,
510 struct chcr_context *ctx, unsigned short qid,
511 unsigned short op_type)
512{
513 struct ablkcipher_request *req = (struct ablkcipher_request *)req_base;
514 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
515 struct uld_ctx *u_ctx = ULD_CTX(ctx);
516 struct ablk_ctx *ablkctx = ABLK_CTX(ctx);
517 struct sk_buff *skb = NULL;
518 struct _key_ctx *key_ctx;
519 struct fw_crypto_lookaside_wr *wreq;
520 struct cpl_tx_sec_pdu *sec_cpl;
521 struct cpl_rx_phys_dsgl *phys_cpl;
522 struct chcr_blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(req);
523 struct phys_sge_parm sg_param;
524 unsigned int frags = 0, transhdr_len, phys_dsgl, dst_bufsize = 0;
525 unsigned int ivsize = crypto_ablkcipher_ivsize(tfm), kctx_len;
526
527 if (!req->info)
528 return ERR_PTR(-EINVAL);
529 ablkctx->dst_nents = ch_nents(req->dst, &dst_bufsize);
530 ablkctx->enc = op_type;
531
532 if ((ablkctx->enckey_len == 0) || (ivsize > AES_BLOCK_SIZE) ||
533 (req->nbytes <= 0) || (req->nbytes % AES_BLOCK_SIZE))
534 return ERR_PTR(-EINVAL);
535
536 phys_dsgl = get_space_for_phys_dsgl(ablkctx->dst_nents);
537
538 kctx_len = sizeof(*key_ctx) +
539 (DIV_ROUND_UP(ablkctx->enckey_len, 16) * 16);
540 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, phys_dsgl);
541 skb = alloc_skb((transhdr_len + sizeof(struct sge_opaque_hdr)),
542 GFP_ATOMIC);
543 if (!skb)
544 return ERR_PTR(-ENOMEM);
545 skb_reserve(skb, sizeof(struct sge_opaque_hdr));
546 wreq = (struct fw_crypto_lookaside_wr *)__skb_put(skb, transhdr_len);
547
548 sec_cpl = (struct cpl_tx_sec_pdu *)((u8 *)wreq + SEC_CPL_OFFSET);
549 sec_cpl->op_ivinsrtofst =
550 FILL_SEC_CPL_OP_IVINSR(ctx->dev->tx_channel_id, 2, 1, 1);
551
552 sec_cpl->pldlen = htonl(ivsize + req->nbytes);
553 sec_cpl->aadstart_cipherstop_hi = FILL_SEC_CPL_CIPHERSTOP_HI(0, 0,
554 ivsize + 1, 0);
555
556 sec_cpl->cipherstop_lo_authinsert = FILL_SEC_CPL_AUTHINSERT(0, 0,
557 0, 0);
558 sec_cpl->seqno_numivs = FILL_SEC_CPL_SCMD0_SEQNO(op_type, 0,
559 ablkctx->ciph_mode,
560 0, 0, ivsize >> 1, 1);
561 sec_cpl->ivgen_hdrlen = FILL_SEC_CPL_IVGEN_HDRLEN(0, 0, 0,
562 0, 1, phys_dsgl);
563
564 key_ctx = (struct _key_ctx *)((u8 *)sec_cpl + sizeof(*sec_cpl));
565 key_ctx->ctx_hdr = ablkctx->key_ctx_hdr;
566 if (op_type == CHCR_DECRYPT_OP) {
567 if (generate_copy_rrkey(ablkctx, key_ctx))
568 goto map_fail1;
569 } else {
570 if (ablkctx->ciph_mode == CHCR_SCMD_CIPHER_MODE_AES_CBC) {
571 memcpy(key_ctx->key, ablkctx->key, ablkctx->enckey_len);
572 } else {
573 memcpy(key_ctx->key, ablkctx->key +
574 (ablkctx->enckey_len >> 1),
575 ablkctx->enckey_len >> 1);
576 memcpy(key_ctx->key +
577 (ablkctx->enckey_len >> 1),
578 ablkctx->key,
579 ablkctx->enckey_len >> 1);
580 }
581 }
582 phys_cpl = (struct cpl_rx_phys_dsgl *)((u8 *)key_ctx + kctx_len);
583
584 memcpy(ablkctx->iv, req->info, ivsize);
585 sg_init_table(&ablkctx->iv_sg, 1);
586 sg_set_buf(&ablkctx->iv_sg, ablkctx->iv, ivsize);
587 sg_param.nents = ablkctx->dst_nents;
588 sg_param.obsize = dst_bufsize;
589 sg_param.qid = qid;
590 sg_param.align = 1;
591 if (map_writesg_phys_cpl(&u_ctx->lldi.pdev->dev, phys_cpl, req->dst,
592 &sg_param))
593 goto map_fail1;
594
595 skb_set_transport_header(skb, transhdr_len);
596 write_sg_data_page_desc(skb, &frags, &ablkctx->iv_sg, ivsize);
597 write_sg_data_page_desc(skb, &frags, req->src, req->nbytes);
598 create_wreq(ctx, wreq, req, skb, kctx_len, 0, phys_dsgl);
599 req_ctx->skb = skb;
600 skb_get(skb);
601 return skb;
602map_fail1:
603 kfree_skb(skb);
604 return ERR_PTR(-ENOMEM);
605}
606
607static int chcr_aes_cbc_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
608 unsigned int keylen)
609{
610 struct chcr_context *ctx = crypto_ablkcipher_ctx(tfm);
611 struct ablk_ctx *ablkctx = ABLK_CTX(ctx);
612 struct ablkcipher_alg *alg = crypto_ablkcipher_alg(tfm);
613 unsigned int ck_size, context_size;
614 u16 alignment = 0;
615
616 if ((keylen < alg->min_keysize) || (keylen > alg->max_keysize))
617 goto badkey_err;
618
619 memcpy(ablkctx->key, key, keylen);
620 ablkctx->enckey_len = keylen;
621 if (keylen == AES_KEYSIZE_128) {
622 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_128;
623 } else if (keylen == AES_KEYSIZE_192) {
624 alignment = 8;
625 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_192;
626 } else if (keylen == AES_KEYSIZE_256) {
627 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_256;
628 } else {
629 goto badkey_err;
630 }
631
632 context_size = (KEY_CONTEXT_HDR_SALT_AND_PAD +
633 keylen + alignment) >> 4;
634
635 ablkctx->key_ctx_hdr = FILL_KEY_CTX_HDR(ck_size, CHCR_KEYCTX_NO_KEY,
636 0, 0, context_size);
637 ablkctx->ciph_mode = CHCR_SCMD_CIPHER_MODE_AES_CBC;
638 return 0;
639badkey_err:
640 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
641 ablkctx->enckey_len = 0;
642 return -EINVAL;
643}
644
Wei Yongjun73b86bb2016-08-26 14:21:08 +0000645static int cxgb4_is_crypto_q_full(struct net_device *dev, unsigned int idx)
Hariprasad Shenai324429d2016-08-17 12:33:05 +0530646{
647 int ret = 0;
648 struct sge_ofld_txq *q;
649 struct adapter *adap = netdev2adap(dev);
650
651 local_bh_disable();
652 q = &adap->sge.ofldtxq[idx];
653 spin_lock(&q->sendq.lock);
654 if (q->full)
655 ret = -1;
656 spin_unlock(&q->sendq.lock);
657 local_bh_enable();
658 return ret;
659}
660
661static int chcr_aes_encrypt(struct ablkcipher_request *req)
662{
663 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
664 struct chcr_context *ctx = crypto_ablkcipher_ctx(tfm);
665 struct crypto_async_request *req_base = &req->base;
666 struct uld_ctx *u_ctx = ULD_CTX(ctx);
667 struct sk_buff *skb;
668
669 if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
670 ctx->tx_channel_id))) {
671 if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
672 return -EBUSY;
673 }
674
675 skb = create_cipher_wr(req_base, ctx,
676 u_ctx->lldi.rxq_ids[ctx->tx_channel_id],
677 CHCR_ENCRYPT_OP);
678 if (IS_ERR(skb)) {
679 pr_err("chcr : %s : Failed to form WR. No memory\n", __func__);
680 return PTR_ERR(skb);
681 }
682 skb->dev = u_ctx->lldi.ports[0];
683 set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_channel_id);
684 chcr_send_wr(skb);
685 return -EINPROGRESS;
686}
687
688static int chcr_aes_decrypt(struct ablkcipher_request *req)
689{
690 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
691 struct chcr_context *ctx = crypto_ablkcipher_ctx(tfm);
692 struct crypto_async_request *req_base = &req->base;
693 struct uld_ctx *u_ctx = ULD_CTX(ctx);
694 struct sk_buff *skb;
695
696 if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
697 ctx->tx_channel_id))) {
698 if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
699 return -EBUSY;
700 }
701
702 skb = create_cipher_wr(req_base, ctx, u_ctx->lldi.rxq_ids[0],
703 CHCR_DECRYPT_OP);
704 if (IS_ERR(skb)) {
705 pr_err("chcr : %s : Failed to form WR. No memory\n", __func__);
706 return PTR_ERR(skb);
707 }
708 skb->dev = u_ctx->lldi.ports[0];
709 set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_channel_id);
710 chcr_send_wr(skb);
711 return -EINPROGRESS;
712}
713
714static int chcr_device_init(struct chcr_context *ctx)
715{
716 struct uld_ctx *u_ctx;
717 unsigned int id;
718 int err = 0, rxq_perchan, rxq_idx;
719
720 id = smp_processor_id();
721 if (!ctx->dev) {
722 err = assign_chcr_device(&ctx->dev);
723 if (err) {
724 pr_err("chcr device assignment fails\n");
725 goto out;
726 }
727 u_ctx = ULD_CTX(ctx);
728 rxq_perchan = u_ctx->lldi.nrxq / u_ctx->lldi.nchan;
729 ctx->dev->tx_channel_id = 0;
730 rxq_idx = ctx->dev->tx_channel_id * rxq_perchan;
731 rxq_idx += id % rxq_perchan;
732 spin_lock(&ctx->dev->lock_chcr_dev);
733 ctx->tx_channel_id = rxq_idx;
734 spin_unlock(&ctx->dev->lock_chcr_dev);
735 }
736out:
737 return err;
738}
739
740static int chcr_cra_init(struct crypto_tfm *tfm)
741{
742 tfm->crt_ablkcipher.reqsize = sizeof(struct chcr_blkcipher_req_ctx);
743 return chcr_device_init(crypto_tfm_ctx(tfm));
744}
745
746static int get_alg_config(struct algo_param *params,
747 unsigned int auth_size)
748{
749 switch (auth_size) {
750 case SHA1_DIGEST_SIZE:
751 params->mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_160;
752 params->auth_mode = CHCR_SCMD_AUTH_MODE_SHA1;
753 params->result_size = SHA1_DIGEST_SIZE;
754 break;
755 case SHA224_DIGEST_SIZE:
756 params->mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_256;
757 params->auth_mode = CHCR_SCMD_AUTH_MODE_SHA224;
758 params->result_size = SHA256_DIGEST_SIZE;
759 break;
760 case SHA256_DIGEST_SIZE:
761 params->mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_256;
762 params->auth_mode = CHCR_SCMD_AUTH_MODE_SHA256;
763 params->result_size = SHA256_DIGEST_SIZE;
764 break;
765 case SHA384_DIGEST_SIZE:
766 params->mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512;
767 params->auth_mode = CHCR_SCMD_AUTH_MODE_SHA512_384;
768 params->result_size = SHA512_DIGEST_SIZE;
769 break;
770 case SHA512_DIGEST_SIZE:
771 params->mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512;
772 params->auth_mode = CHCR_SCMD_AUTH_MODE_SHA512_512;
773 params->result_size = SHA512_DIGEST_SIZE;
774 break;
775 default:
776 pr_err("chcr : ERROR, unsupported digest size\n");
777 return -EINVAL;
778 }
779 return 0;
780}
781
782static inline int
783write_buffer_data_page_desc(struct chcr_ahash_req_ctx *req_ctx,
784 struct sk_buff *skb, unsigned int *frags, char *bfr,
785 u8 bfr_len)
786{
787 void *page_ptr = NULL;
788
789 skb->len += bfr_len;
790 skb->data_len += bfr_len;
791 skb->truesize += bfr_len;
792 page_ptr = kmalloc(CHCR_HASH_MAX_BLOCK_SIZE_128, GFP_ATOMIC | GFP_DMA);
793 if (!page_ptr)
794 return -ENOMEM;
795 get_page(virt_to_page(page_ptr));
796 req_ctx->dummy_payload_ptr = page_ptr;
797 memcpy(page_ptr, bfr, bfr_len);
798 skb_fill_page_desc(skb, *frags, virt_to_page(page_ptr),
799 offset_in_page(page_ptr), bfr_len);
800 (*frags)++;
801 return 0;
802}
803
804/**
805 * create_final_hash_wr - Create hash work request
806 * @req - Cipher req base
807 */
808static struct sk_buff *create_final_hash_wr(struct ahash_request *req,
809 struct hash_wr_param *param)
810{
811 struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(req);
812 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
813 struct chcr_context *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
814 struct hmac_ctx *hmacctx = HMAC_CTX(ctx);
815 struct sk_buff *skb = NULL;
816 struct _key_ctx *key_ctx;
817 struct fw_crypto_lookaside_wr *wreq;
818 struct cpl_tx_sec_pdu *sec_cpl;
819 unsigned int frags = 0, transhdr_len, iopad_alignment = 0;
820 unsigned int digestsize = crypto_ahash_digestsize(tfm);
821 unsigned int kctx_len = sizeof(*key_ctx);
822 u8 hash_size_in_response = 0;
823
824 iopad_alignment = KEYCTX_ALIGN_PAD(digestsize);
825 kctx_len += param->alg_prm.result_size + iopad_alignment;
826 if (param->opad_needed)
827 kctx_len += param->alg_prm.result_size + iopad_alignment;
828
829 if (req_ctx->result)
830 hash_size_in_response = digestsize;
831 else
832 hash_size_in_response = param->alg_prm.result_size;
833 transhdr_len = HASH_TRANSHDR_SIZE(kctx_len);
834 skb = alloc_skb((transhdr_len + sizeof(struct sge_opaque_hdr)),
835 GFP_ATOMIC);
836 if (!skb)
837 return skb;
838
839 skb_reserve(skb, sizeof(struct sge_opaque_hdr));
840 wreq = (struct fw_crypto_lookaside_wr *)__skb_put(skb, transhdr_len);
841 memset(wreq, 0, transhdr_len);
842
843 sec_cpl = (struct cpl_tx_sec_pdu *)((u8 *)wreq + SEC_CPL_OFFSET);
844 sec_cpl->op_ivinsrtofst =
845 FILL_SEC_CPL_OP_IVINSR(ctx->dev->tx_channel_id, 2, 0, 0);
846 sec_cpl->pldlen = htonl(param->bfr_len + param->sg_len);
847
848 sec_cpl->aadstart_cipherstop_hi =
849 FILL_SEC_CPL_CIPHERSTOP_HI(0, 0, 0, 0);
850 sec_cpl->cipherstop_lo_authinsert =
851 FILL_SEC_CPL_AUTHINSERT(0, 1, 0, 0);
852 sec_cpl->seqno_numivs =
853 FILL_SEC_CPL_SCMD0_SEQNO(0, 0, 0, param->alg_prm.auth_mode,
854 param->opad_needed, 0, 0);
855
856 sec_cpl->ivgen_hdrlen =
857 FILL_SEC_CPL_IVGEN_HDRLEN(param->last, param->more, 0, 1, 0, 0);
858
859 key_ctx = (struct _key_ctx *)((u8 *)sec_cpl + sizeof(*sec_cpl));
860 memcpy(key_ctx->key, req_ctx->partial_hash, param->alg_prm.result_size);
861
862 if (param->opad_needed)
863 memcpy(key_ctx->key + ((param->alg_prm.result_size <= 32) ? 32 :
864 CHCR_HASH_MAX_DIGEST_SIZE),
865 hmacctx->opad, param->alg_prm.result_size);
866
867 key_ctx->ctx_hdr = FILL_KEY_CTX_HDR(CHCR_KEYCTX_NO_KEY,
868 param->alg_prm.mk_size, 0,
869 param->opad_needed,
870 (kctx_len >> 4));
871 sec_cpl->scmd1 = cpu_to_be64((u64)param->scmd1);
872
873 skb_set_transport_header(skb, transhdr_len);
874 if (param->bfr_len != 0)
875 write_buffer_data_page_desc(req_ctx, skb, &frags, req_ctx->bfr,
876 param->bfr_len);
877 if (param->sg_len != 0)
878 write_sg_data_page_desc(skb, &frags, req->src, param->sg_len);
879
880 create_wreq(ctx, wreq, req, skb, kctx_len, hash_size_in_response,
881 0);
882 req_ctx->skb = skb;
883 skb_get(skb);
884 return skb;
885}
886
887static int chcr_ahash_update(struct ahash_request *req)
888{
889 struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(req);
890 struct crypto_ahash *rtfm = crypto_ahash_reqtfm(req);
891 struct chcr_context *ctx = crypto_tfm_ctx(crypto_ahash_tfm(rtfm));
892 struct uld_ctx *u_ctx = NULL;
893 struct sk_buff *skb;
894 u8 remainder = 0, bs;
895 unsigned int nbytes = req->nbytes;
896 struct hash_wr_param params;
897
898 bs = crypto_tfm_alg_blocksize(crypto_ahash_tfm(rtfm));
899
900 u_ctx = ULD_CTX(ctx);
901 if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
902 ctx->tx_channel_id))) {
903 if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
904 return -EBUSY;
905 }
906
907 if (nbytes + req_ctx->bfr_len >= bs) {
908 remainder = (nbytes + req_ctx->bfr_len) % bs;
909 nbytes = nbytes + req_ctx->bfr_len - remainder;
910 } else {
911 sg_pcopy_to_buffer(req->src, sg_nents(req->src), req_ctx->bfr +
912 req_ctx->bfr_len, nbytes, 0);
913 req_ctx->bfr_len += nbytes;
914 return 0;
915 }
916
917 params.opad_needed = 0;
918 params.more = 1;
919 params.last = 0;
920 params.sg_len = nbytes - req_ctx->bfr_len;
921 params.bfr_len = req_ctx->bfr_len;
922 params.scmd1 = 0;
923 get_alg_config(&params.alg_prm, crypto_ahash_digestsize(rtfm));
924 req_ctx->result = 0;
925 req_ctx->data_len += params.sg_len + params.bfr_len;
926 skb = create_final_hash_wr(req, &params);
927 if (!skb)
928 return -ENOMEM;
929
930 req_ctx->bfr_len = remainder;
931 if (remainder)
932 sg_pcopy_to_buffer(req->src, sg_nents(req->src),
933 req_ctx->bfr, remainder, req->nbytes -
934 remainder);
935 skb->dev = u_ctx->lldi.ports[0];
936 set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_channel_id);
937 chcr_send_wr(skb);
938
939 return -EINPROGRESS;
940}
941
942static void create_last_hash_block(char *bfr_ptr, unsigned int bs, u64 scmd1)
943{
944 memset(bfr_ptr, 0, bs);
945 *bfr_ptr = 0x80;
946 if (bs == 64)
947 *(__be64 *)(bfr_ptr + 56) = cpu_to_be64(scmd1 << 3);
948 else
949 *(__be64 *)(bfr_ptr + 120) = cpu_to_be64(scmd1 << 3);
950}
951
952static int chcr_ahash_final(struct ahash_request *req)
953{
954 struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(req);
955 struct crypto_ahash *rtfm = crypto_ahash_reqtfm(req);
956 struct chcr_context *ctx = crypto_tfm_ctx(crypto_ahash_tfm(rtfm));
957 struct hash_wr_param params;
958 struct sk_buff *skb;
959 struct uld_ctx *u_ctx = NULL;
960 u8 bs = crypto_tfm_alg_blocksize(crypto_ahash_tfm(rtfm));
961
962 u_ctx = ULD_CTX(ctx);
963 if (is_hmac(crypto_ahash_tfm(rtfm)))
964 params.opad_needed = 1;
965 else
966 params.opad_needed = 0;
967 params.sg_len = 0;
968 get_alg_config(&params.alg_prm, crypto_ahash_digestsize(rtfm));
969 req_ctx->result = 1;
970 params.bfr_len = req_ctx->bfr_len;
971 req_ctx->data_len += params.bfr_len + params.sg_len;
972 if (req_ctx->bfr && (req_ctx->bfr_len == 0)) {
973 create_last_hash_block(req_ctx->bfr, bs, req_ctx->data_len);
974 params.last = 0;
975 params.more = 1;
976 params.scmd1 = 0;
977 params.bfr_len = bs;
978
979 } else {
980 params.scmd1 = req_ctx->data_len;
981 params.last = 1;
982 params.more = 0;
983 }
984 skb = create_final_hash_wr(req, &params);
985 skb->dev = u_ctx->lldi.ports[0];
986 set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_channel_id);
987 chcr_send_wr(skb);
988 return -EINPROGRESS;
989}
990
991static int chcr_ahash_finup(struct ahash_request *req)
992{
993 struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(req);
994 struct crypto_ahash *rtfm = crypto_ahash_reqtfm(req);
995 struct chcr_context *ctx = crypto_tfm_ctx(crypto_ahash_tfm(rtfm));
996 struct uld_ctx *u_ctx = NULL;
997 struct sk_buff *skb;
998 struct hash_wr_param params;
999 u8 bs;
1000
1001 bs = crypto_tfm_alg_blocksize(crypto_ahash_tfm(rtfm));
1002 u_ctx = ULD_CTX(ctx);
1003
1004 if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
1005 ctx->tx_channel_id))) {
1006 if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
1007 return -EBUSY;
1008 }
1009
1010 if (is_hmac(crypto_ahash_tfm(rtfm)))
1011 params.opad_needed = 1;
1012 else
1013 params.opad_needed = 0;
1014
1015 params.sg_len = req->nbytes;
1016 params.bfr_len = req_ctx->bfr_len;
1017 get_alg_config(&params.alg_prm, crypto_ahash_digestsize(rtfm));
1018 req_ctx->data_len += params.bfr_len + params.sg_len;
1019 req_ctx->result = 1;
1020 if (req_ctx->bfr && (req_ctx->bfr_len + req->nbytes) == 0) {
1021 create_last_hash_block(req_ctx->bfr, bs, req_ctx->data_len);
1022 params.last = 0;
1023 params.more = 1;
1024 params.scmd1 = 0;
1025 params.bfr_len = bs;
1026 } else {
1027 params.scmd1 = req_ctx->data_len;
1028 params.last = 1;
1029 params.more = 0;
1030 }
1031
1032 skb = create_final_hash_wr(req, &params);
1033 if (!skb)
1034 return -ENOMEM;
1035 skb->dev = u_ctx->lldi.ports[0];
1036 set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_channel_id);
1037 chcr_send_wr(skb);
1038
1039 return -EINPROGRESS;
1040}
1041
1042static int chcr_ahash_digest(struct ahash_request *req)
1043{
1044 struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(req);
1045 struct crypto_ahash *rtfm = crypto_ahash_reqtfm(req);
1046 struct chcr_context *ctx = crypto_tfm_ctx(crypto_ahash_tfm(rtfm));
1047 struct uld_ctx *u_ctx = NULL;
1048 struct sk_buff *skb;
1049 struct hash_wr_param params;
1050 u8 bs;
1051
1052 rtfm->init(req);
1053 bs = crypto_tfm_alg_blocksize(crypto_ahash_tfm(rtfm));
1054
1055 u_ctx = ULD_CTX(ctx);
1056 if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
1057 ctx->tx_channel_id))) {
1058 if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
1059 return -EBUSY;
1060 }
1061
1062 if (is_hmac(crypto_ahash_tfm(rtfm)))
1063 params.opad_needed = 1;
1064 else
1065 params.opad_needed = 0;
1066
1067 params.last = 0;
1068 params.more = 0;
1069 params.sg_len = req->nbytes;
1070 params.bfr_len = 0;
1071 params.scmd1 = 0;
1072 get_alg_config(&params.alg_prm, crypto_ahash_digestsize(rtfm));
1073 req_ctx->result = 1;
1074 req_ctx->data_len += params.bfr_len + params.sg_len;
1075
1076 if (req_ctx->bfr && req->nbytes == 0) {
1077 create_last_hash_block(req_ctx->bfr, bs, 0);
1078 params.more = 1;
1079 params.bfr_len = bs;
1080 }
1081
1082 skb = create_final_hash_wr(req, &params);
1083 if (!skb)
1084 return -ENOMEM;
1085
1086 skb->dev = u_ctx->lldi.ports[0];
1087 set_wr_txq(skb, CPL_PRIORITY_DATA, ctx->tx_channel_id);
1088 chcr_send_wr(skb);
1089 return -EINPROGRESS;
1090}
1091
1092static int chcr_ahash_export(struct ahash_request *areq, void *out)
1093{
1094 struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1095 struct chcr_ahash_req_ctx *state = out;
1096
1097 state->bfr_len = req_ctx->bfr_len;
1098 state->data_len = req_ctx->data_len;
1099 memcpy(state->bfr, req_ctx->bfr, CHCR_HASH_MAX_BLOCK_SIZE_128);
1100 memcpy(state->partial_hash, req_ctx->partial_hash,
1101 CHCR_HASH_MAX_DIGEST_SIZE);
1102 return 0;
1103}
1104
1105static int chcr_ahash_import(struct ahash_request *areq, const void *in)
1106{
1107 struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1108 struct chcr_ahash_req_ctx *state = (struct chcr_ahash_req_ctx *)in;
1109
1110 req_ctx->bfr_len = state->bfr_len;
1111 req_ctx->data_len = state->data_len;
1112 req_ctx->dummy_payload_ptr = NULL;
1113 memcpy(req_ctx->bfr, state->bfr, CHCR_HASH_MAX_BLOCK_SIZE_128);
1114 memcpy(req_ctx->partial_hash, state->partial_hash,
1115 CHCR_HASH_MAX_DIGEST_SIZE);
1116 return 0;
1117}
1118
1119static int chcr_ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1120 unsigned int keylen)
1121{
1122 struct chcr_context *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1123 struct hmac_ctx *hmacctx = HMAC_CTX(ctx);
1124 unsigned int digestsize = crypto_ahash_digestsize(tfm);
1125 unsigned int bs = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1126 unsigned int i, err = 0, updated_digestsize;
1127
1128 /*
1129 * use the key to calculate the ipad and opad. ipad will sent with the
1130 * first request's data. opad will be sent with the final hash result
1131 * ipad in hmacctx->ipad and opad in hmacctx->opad location
1132 */
1133 if (!hmacctx->desc)
1134 return -EINVAL;
1135 if (keylen > bs) {
1136 err = crypto_shash_digest(hmacctx->desc, key, keylen,
1137 hmacctx->ipad);
1138 if (err)
1139 goto out;
1140 keylen = digestsize;
1141 } else {
1142 memcpy(hmacctx->ipad, key, keylen);
1143 }
1144 memset(hmacctx->ipad + keylen, 0, bs - keylen);
1145 memcpy(hmacctx->opad, hmacctx->ipad, bs);
1146
1147 for (i = 0; i < bs / sizeof(int); i++) {
1148 *((unsigned int *)(&hmacctx->ipad) + i) ^= IPAD_DATA;
1149 *((unsigned int *)(&hmacctx->opad) + i) ^= OPAD_DATA;
1150 }
1151
1152 updated_digestsize = digestsize;
1153 if (digestsize == SHA224_DIGEST_SIZE)
1154 updated_digestsize = SHA256_DIGEST_SIZE;
1155 else if (digestsize == SHA384_DIGEST_SIZE)
1156 updated_digestsize = SHA512_DIGEST_SIZE;
1157 err = chcr_compute_partial_hash(hmacctx->desc, hmacctx->ipad,
1158 hmacctx->ipad, digestsize);
1159 if (err)
1160 goto out;
1161 chcr_change_order(hmacctx->ipad, updated_digestsize);
1162
1163 err = chcr_compute_partial_hash(hmacctx->desc, hmacctx->opad,
1164 hmacctx->opad, digestsize);
1165 if (err)
1166 goto out;
1167 chcr_change_order(hmacctx->opad, updated_digestsize);
1168out:
1169 return err;
1170}
1171
1172static int chcr_aes_xts_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1173 unsigned int key_len)
1174{
1175 struct chcr_context *ctx = crypto_ablkcipher_ctx(tfm);
1176 struct ablk_ctx *ablkctx = ABLK_CTX(ctx);
1177 int status = 0;
1178 unsigned short context_size = 0;
1179
1180 if ((key_len == (AES_KEYSIZE_128 << 1)) ||
1181 (key_len == (AES_KEYSIZE_256 << 1))) {
1182 memcpy(ablkctx->key, key, key_len);
1183 ablkctx->enckey_len = key_len;
1184 context_size = (KEY_CONTEXT_HDR_SALT_AND_PAD + key_len) >> 4;
1185 ablkctx->key_ctx_hdr =
1186 FILL_KEY_CTX_HDR((key_len == AES_KEYSIZE_256) ?
1187 CHCR_KEYCTX_CIPHER_KEY_SIZE_128 :
1188 CHCR_KEYCTX_CIPHER_KEY_SIZE_256,
1189 CHCR_KEYCTX_NO_KEY, 1,
1190 0, context_size);
1191 ablkctx->ciph_mode = CHCR_SCMD_CIPHER_MODE_AES_XTS;
1192 } else {
1193 crypto_tfm_set_flags((struct crypto_tfm *)tfm,
1194 CRYPTO_TFM_RES_BAD_KEY_LEN);
1195 ablkctx->enckey_len = 0;
1196 status = -EINVAL;
1197 }
1198 return status;
1199}
1200
1201static int chcr_sha_init(struct ahash_request *areq)
1202{
1203 struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1204 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1205 int digestsize = crypto_ahash_digestsize(tfm);
1206
1207 req_ctx->data_len = 0;
1208 req_ctx->dummy_payload_ptr = NULL;
1209 req_ctx->bfr_len = 0;
1210 req_ctx->skb = NULL;
1211 req_ctx->result = 0;
1212 copy_hash_init_values(req_ctx->partial_hash, digestsize);
1213 return 0;
1214}
1215
1216static int chcr_sha_cra_init(struct crypto_tfm *tfm)
1217{
1218 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1219 sizeof(struct chcr_ahash_req_ctx));
1220 return chcr_device_init(crypto_tfm_ctx(tfm));
1221}
1222
1223static int chcr_hmac_init(struct ahash_request *areq)
1224{
1225 struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1226 struct crypto_ahash *rtfm = crypto_ahash_reqtfm(areq);
1227 struct chcr_context *ctx = crypto_tfm_ctx(crypto_ahash_tfm(rtfm));
1228 struct hmac_ctx *hmacctx = HMAC_CTX(ctx);
1229 unsigned int digestsize = crypto_ahash_digestsize(rtfm);
1230 unsigned int bs = crypto_tfm_alg_blocksize(crypto_ahash_tfm(rtfm));
1231
1232 chcr_sha_init(areq);
1233 req_ctx->data_len = bs;
1234 if (is_hmac(crypto_ahash_tfm(rtfm))) {
1235 if (digestsize == SHA224_DIGEST_SIZE)
1236 memcpy(req_ctx->partial_hash, hmacctx->ipad,
1237 SHA256_DIGEST_SIZE);
1238 else if (digestsize == SHA384_DIGEST_SIZE)
1239 memcpy(req_ctx->partial_hash, hmacctx->ipad,
1240 SHA512_DIGEST_SIZE);
1241 else
1242 memcpy(req_ctx->partial_hash, hmacctx->ipad,
1243 digestsize);
1244 }
1245 return 0;
1246}
1247
1248static int chcr_hmac_cra_init(struct crypto_tfm *tfm)
1249{
1250 struct chcr_context *ctx = crypto_tfm_ctx(tfm);
1251 struct hmac_ctx *hmacctx = HMAC_CTX(ctx);
1252 unsigned int digestsize =
1253 crypto_ahash_digestsize(__crypto_ahash_cast(tfm));
1254
1255 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1256 sizeof(struct chcr_ahash_req_ctx));
1257 hmacctx->desc = chcr_alloc_shash(digestsize);
1258 if (IS_ERR(hmacctx->desc))
1259 return PTR_ERR(hmacctx->desc);
1260 return chcr_device_init(crypto_tfm_ctx(tfm));
1261}
1262
1263static void chcr_free_shash(struct shash_desc *desc)
1264{
1265 crypto_free_shash(desc->tfm);
1266 kfree(desc);
1267}
1268
1269static void chcr_hmac_cra_exit(struct crypto_tfm *tfm)
1270{
1271 struct chcr_context *ctx = crypto_tfm_ctx(tfm);
1272 struct hmac_ctx *hmacctx = HMAC_CTX(ctx);
1273
1274 if (hmacctx->desc) {
1275 chcr_free_shash(hmacctx->desc);
1276 hmacctx->desc = NULL;
1277 }
1278}
1279
1280static struct chcr_alg_template driver_algs[] = {
1281 /* AES-CBC */
1282 {
1283 .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
1284 .is_registered = 0,
1285 .alg.crypto = {
1286 .cra_name = "cbc(aes)",
1287 .cra_driver_name = "cbc(aes-chcr)",
1288 .cra_priority = CHCR_CRA_PRIORITY,
1289 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
1290 CRYPTO_ALG_ASYNC,
1291 .cra_blocksize = AES_BLOCK_SIZE,
1292 .cra_ctxsize = sizeof(struct chcr_context)
1293 + sizeof(struct ablk_ctx),
1294 .cra_alignmask = 0,
1295 .cra_type = &crypto_ablkcipher_type,
1296 .cra_module = THIS_MODULE,
1297 .cra_init = chcr_cra_init,
1298 .cra_exit = NULL,
1299 .cra_u.ablkcipher = {
1300 .min_keysize = AES_MIN_KEY_SIZE,
1301 .max_keysize = AES_MAX_KEY_SIZE,
1302 .ivsize = AES_BLOCK_SIZE,
1303 .setkey = chcr_aes_cbc_setkey,
1304 .encrypt = chcr_aes_encrypt,
1305 .decrypt = chcr_aes_decrypt,
1306 }
1307 }
1308 },
1309 {
1310 .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
1311 .is_registered = 0,
1312 .alg.crypto = {
1313 .cra_name = "xts(aes)",
1314 .cra_driver_name = "xts(aes-chcr)",
1315 .cra_priority = CHCR_CRA_PRIORITY,
1316 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
1317 CRYPTO_ALG_ASYNC,
1318 .cra_blocksize = AES_BLOCK_SIZE,
1319 .cra_ctxsize = sizeof(struct chcr_context) +
1320 sizeof(struct ablk_ctx),
1321 .cra_alignmask = 0,
1322 .cra_type = &crypto_ablkcipher_type,
1323 .cra_module = THIS_MODULE,
1324 .cra_init = chcr_cra_init,
1325 .cra_exit = NULL,
1326 .cra_u = {
1327 .ablkcipher = {
1328 .min_keysize = 2 * AES_MIN_KEY_SIZE,
1329 .max_keysize = 2 * AES_MAX_KEY_SIZE,
1330 .ivsize = AES_BLOCK_SIZE,
1331 .setkey = chcr_aes_xts_setkey,
1332 .encrypt = chcr_aes_encrypt,
1333 .decrypt = chcr_aes_decrypt,
1334 }
1335 }
1336 }
1337 },
1338 /* SHA */
1339 {
1340 .type = CRYPTO_ALG_TYPE_AHASH,
1341 .is_registered = 0,
1342 .alg.hash = {
1343 .halg.digestsize = SHA1_DIGEST_SIZE,
1344 .halg.base = {
1345 .cra_name = "sha1",
1346 .cra_driver_name = "sha1-chcr",
1347 .cra_blocksize = SHA1_BLOCK_SIZE,
1348 }
1349 }
1350 },
1351 {
1352 .type = CRYPTO_ALG_TYPE_AHASH,
1353 .is_registered = 0,
1354 .alg.hash = {
1355 .halg.digestsize = SHA256_DIGEST_SIZE,
1356 .halg.base = {
1357 .cra_name = "sha256",
1358 .cra_driver_name = "sha256-chcr",
1359 .cra_blocksize = SHA256_BLOCK_SIZE,
1360 }
1361 }
1362 },
1363 {
1364 .type = CRYPTO_ALG_TYPE_AHASH,
1365 .is_registered = 0,
1366 .alg.hash = {
1367 .halg.digestsize = SHA224_DIGEST_SIZE,
1368 .halg.base = {
1369 .cra_name = "sha224",
1370 .cra_driver_name = "sha224-chcr",
1371 .cra_blocksize = SHA224_BLOCK_SIZE,
1372 }
1373 }
1374 },
1375 {
1376 .type = CRYPTO_ALG_TYPE_AHASH,
1377 .is_registered = 0,
1378 .alg.hash = {
1379 .halg.digestsize = SHA384_DIGEST_SIZE,
1380 .halg.base = {
1381 .cra_name = "sha384",
1382 .cra_driver_name = "sha384-chcr",
1383 .cra_blocksize = SHA384_BLOCK_SIZE,
1384 }
1385 }
1386 },
1387 {
1388 .type = CRYPTO_ALG_TYPE_AHASH,
1389 .is_registered = 0,
1390 .alg.hash = {
1391 .halg.digestsize = SHA512_DIGEST_SIZE,
1392 .halg.base = {
1393 .cra_name = "sha512",
1394 .cra_driver_name = "sha512-chcr",
1395 .cra_blocksize = SHA512_BLOCK_SIZE,
1396 }
1397 }
1398 },
1399 /* HMAC */
1400 {
1401 .type = CRYPTO_ALG_TYPE_HMAC,
1402 .is_registered = 0,
1403 .alg.hash = {
1404 .halg.digestsize = SHA1_DIGEST_SIZE,
1405 .halg.base = {
1406 .cra_name = "hmac(sha1)",
1407 .cra_driver_name = "hmac(sha1-chcr)",
1408 .cra_blocksize = SHA1_BLOCK_SIZE,
1409 }
1410 }
1411 },
1412 {
1413 .type = CRYPTO_ALG_TYPE_HMAC,
1414 .is_registered = 0,
1415 .alg.hash = {
1416 .halg.digestsize = SHA224_DIGEST_SIZE,
1417 .halg.base = {
1418 .cra_name = "hmac(sha224)",
1419 .cra_driver_name = "hmac(sha224-chcr)",
1420 .cra_blocksize = SHA224_BLOCK_SIZE,
1421 }
1422 }
1423 },
1424 {
1425 .type = CRYPTO_ALG_TYPE_HMAC,
1426 .is_registered = 0,
1427 .alg.hash = {
1428 .halg.digestsize = SHA256_DIGEST_SIZE,
1429 .halg.base = {
1430 .cra_name = "hmac(sha256)",
1431 .cra_driver_name = "hmac(sha256-chcr)",
1432 .cra_blocksize = SHA256_BLOCK_SIZE,
1433 }
1434 }
1435 },
1436 {
1437 .type = CRYPTO_ALG_TYPE_HMAC,
1438 .is_registered = 0,
1439 .alg.hash = {
1440 .halg.digestsize = SHA384_DIGEST_SIZE,
1441 .halg.base = {
1442 .cra_name = "hmac(sha384)",
1443 .cra_driver_name = "hmac(sha384-chcr)",
1444 .cra_blocksize = SHA384_BLOCK_SIZE,
1445 }
1446 }
1447 },
1448 {
1449 .type = CRYPTO_ALG_TYPE_HMAC,
1450 .is_registered = 0,
1451 .alg.hash = {
1452 .halg.digestsize = SHA512_DIGEST_SIZE,
1453 .halg.base = {
1454 .cra_name = "hmac(sha512)",
1455 .cra_driver_name = "hmac(sha512-chcr)",
1456 .cra_blocksize = SHA512_BLOCK_SIZE,
1457 }
1458 }
1459 },
1460};
1461
1462/*
1463 * chcr_unregister_alg - Deregister crypto algorithms with
1464 * kernel framework.
1465 */
1466static int chcr_unregister_alg(void)
1467{
1468 int i;
1469
1470 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
1471 switch (driver_algs[i].type & CRYPTO_ALG_TYPE_MASK) {
1472 case CRYPTO_ALG_TYPE_ABLKCIPHER:
1473 if (driver_algs[i].is_registered)
1474 crypto_unregister_alg(
1475 &driver_algs[i].alg.crypto);
1476 break;
1477 case CRYPTO_ALG_TYPE_AHASH:
1478 if (driver_algs[i].is_registered)
1479 crypto_unregister_ahash(
1480 &driver_algs[i].alg.hash);
1481 break;
1482 }
1483 driver_algs[i].is_registered = 0;
1484 }
1485 return 0;
1486}
1487
1488#define SZ_AHASH_CTX sizeof(struct chcr_context)
1489#define SZ_AHASH_H_CTX (sizeof(struct chcr_context) + sizeof(struct hmac_ctx))
1490#define SZ_AHASH_REQ_CTX sizeof(struct chcr_ahash_req_ctx)
1491#define AHASH_CRA_FLAGS (CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC)
1492
1493/*
1494 * chcr_register_alg - Register crypto algorithms with kernel framework.
1495 */
1496static int chcr_register_alg(void)
1497{
1498 struct crypto_alg ai;
1499 struct ahash_alg *a_hash;
1500 int err = 0, i;
1501 char *name = NULL;
1502
1503 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
1504 if (driver_algs[i].is_registered)
1505 continue;
1506 switch (driver_algs[i].type & CRYPTO_ALG_TYPE_MASK) {
1507 case CRYPTO_ALG_TYPE_ABLKCIPHER:
1508 err = crypto_register_alg(&driver_algs[i].alg.crypto);
1509 name = driver_algs[i].alg.crypto.cra_driver_name;
1510 break;
1511 case CRYPTO_ALG_TYPE_AHASH:
1512 a_hash = &driver_algs[i].alg.hash;
1513 a_hash->update = chcr_ahash_update;
1514 a_hash->final = chcr_ahash_final;
1515 a_hash->finup = chcr_ahash_finup;
1516 a_hash->digest = chcr_ahash_digest;
1517 a_hash->export = chcr_ahash_export;
1518 a_hash->import = chcr_ahash_import;
1519 a_hash->halg.statesize = SZ_AHASH_REQ_CTX;
1520 a_hash->halg.base.cra_priority = CHCR_CRA_PRIORITY;
1521 a_hash->halg.base.cra_module = THIS_MODULE;
1522 a_hash->halg.base.cra_flags = AHASH_CRA_FLAGS;
1523 a_hash->halg.base.cra_alignmask = 0;
1524 a_hash->halg.base.cra_exit = NULL;
1525 a_hash->halg.base.cra_type = &crypto_ahash_type;
1526
1527 if (driver_algs[i].type == CRYPTO_ALG_TYPE_HMAC) {
1528 a_hash->halg.base.cra_init = chcr_hmac_cra_init;
1529 a_hash->halg.base.cra_exit = chcr_hmac_cra_exit;
1530 a_hash->init = chcr_hmac_init;
1531 a_hash->setkey = chcr_ahash_setkey;
1532 a_hash->halg.base.cra_ctxsize = SZ_AHASH_H_CTX;
1533 } else {
1534 a_hash->init = chcr_sha_init;
1535 a_hash->halg.base.cra_ctxsize = SZ_AHASH_CTX;
1536 a_hash->halg.base.cra_init = chcr_sha_cra_init;
1537 }
1538 err = crypto_register_ahash(&driver_algs[i].alg.hash);
1539 ai = driver_algs[i].alg.hash.halg.base;
1540 name = ai.cra_driver_name;
1541 break;
1542 }
1543 if (err) {
1544 pr_err("chcr : %s : Algorithm registration failed\n",
1545 name);
1546 goto register_err;
1547 } else {
1548 driver_algs[i].is_registered = 1;
1549 }
1550 }
1551 return 0;
1552
1553register_err:
1554 chcr_unregister_alg();
1555 return err;
1556}
1557
1558/*
1559 * start_crypto - Register the crypto algorithms.
1560 * This should called once when the first device comesup. After this
1561 * kernel will start calling driver APIs for crypto operations.
1562 */
1563int start_crypto(void)
1564{
1565 return chcr_register_alg();
1566}
1567
1568/*
1569 * stop_crypto - Deregister all the crypto algorithms with kernel.
1570 * This should be called once when the last device goes down. After this
1571 * kernel will not call the driver API for crypto operations.
1572 */
1573int stop_crypto(void)
1574{
1575 chcr_unregister_alg();
1576 return 0;
1577}