| Kumar Gala | cc60a1a | 2014-01-23 14:09:54 -0600 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
| 3 | /include/ "skeleton.dtsi" |
| 4 | |
| 5 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> |
| 6 | |
| 7 | / { |
| 8 | model = "Qualcomm MSM8960"; |
| 9 | compatible = "qcom,msm8960"; |
| 10 | interrupt-parent = <&intc>; |
| 11 | |
| Stephen Boyd | 3bff547 | 2014-02-21 11:09:50 +0000 | [diff] [blame^] | 12 | cpu-pmu { |
| 13 | compatible = "qcom,krait-pmu"; |
| 14 | interrupts = <1 10 0x304>; |
| 15 | qcom,no-pc-write; |
| 16 | }; |
| 17 | |
| Kumar Gala | cc60a1a | 2014-01-23 14:09:54 -0600 | [diff] [blame] | 18 | intc: interrupt-controller@2000000 { |
| 19 | compatible = "qcom,msm-qgic2"; |
| 20 | interrupt-controller; |
| 21 | #interrupt-cells = <3>; |
| 22 | reg = < 0x02000000 0x1000 >, |
| 23 | < 0x02002000 0x1000 >; |
| 24 | }; |
| 25 | |
| 26 | timer@200a000 { |
| 27 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; |
| 28 | interrupts = <1 1 0x301>, |
| 29 | <1 2 0x301>, |
| 30 | <1 3 0x301>; |
| 31 | reg = <0x0200a000 0x100>; |
| 32 | clock-frequency = <27000000>, |
| 33 | <32768>; |
| 34 | cpu-offset = <0x80000>; |
| 35 | }; |
| 36 | |
| 37 | msmgpio: gpio@800000 { |
| 38 | compatible = "qcom,msm-gpio"; |
| 39 | gpio-controller; |
| 40 | #gpio-cells = <2>; |
| 41 | ngpio = <150>; |
| 42 | interrupts = <0 16 0x4>; |
| 43 | interrupt-controller; |
| 44 | #interrupt-cells = <2>; |
| 45 | reg = <0x800000 0x4000>; |
| 46 | }; |
| 47 | |
| 48 | gcc: clock-controller@900000 { |
| 49 | compatible = "qcom,gcc-msm8960"; |
| 50 | #clock-cells = <1>; |
| 51 | #reset-cells = <1>; |
| 52 | reg = <0x900000 0x4000>; |
| 53 | }; |
| 54 | |
| 55 | clock-controller@4000000 { |
| 56 | compatible = "qcom,mmcc-msm8960"; |
| 57 | reg = <0x4000000 0x1000>; |
| 58 | #clock-cells = <1>; |
| 59 | #reset-cells = <1>; |
| 60 | }; |
| 61 | |
| 62 | serial@16440000 { |
| 63 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
| 64 | reg = <0x16440000 0x1000>, |
| 65 | <0x16400000 0x1000>; |
| 66 | interrupts = <0 154 0x0>; |
| 67 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; |
| 68 | clock-names = "core", "iface"; |
| 69 | }; |
| 70 | |
| 71 | qcom,ssbi@500000 { |
| 72 | compatible = "qcom,ssbi"; |
| 73 | reg = <0x500000 0x1000>; |
| 74 | qcom,controller-type = "pmic-arbiter"; |
| 75 | }; |
| 76 | }; |