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gerrit-public.fairphone.software / kernel / msm-5.4 / 3cd4e067a3e548a56a8b5e202552dcd18a2783a9 / . / include / asm-mips / mach-rc32434 / gpio.h
blob: 4fe18dbacaf70282716b7e939bddc049a5cfa888 [file] [log] [blame]
Ralf Baechle73b43902008-07-16 16:12:25 +0100[diff] [blame]1/*
2 * Copyright 2002 Integrated Device Technology, Inc.
3 * All rights reserved.
4 *
5 * GPIO register definition.
6 *
7 * Author : ryan.holmQVist@idt.com
8 * Date : 20011005
9 * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
10 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
11 */
12
13#ifndef _RC32434_GPIO_H_
14#define _RC32434_GPIO_H_
15
16#include <linux/types.h>
17
18struct rb532_gpio_reg {
19 u32 gpiofunc; /* GPIO Function Register
20 * gpiofunc[x]==0 bit = gpio
21 * func[x]==1 bit = altfunc
22 */
23 u32 gpiocfg; /* GPIO Configuration Register
24 * gpiocfg[x]==0 bit = input
25 * gpiocfg[x]==1 bit = output
26 */
27 u32 gpiod; /* GPIO Data Register
28 * gpiod[x] read/write gpio pinX status
29 */
30 u32 gpioilevel; /* GPIO Interrupt Status Register
31 * interrupt level (see gpioistat)
32 */
33 u32 gpioistat; /* Gpio Interrupt Status Register
34 * istat[x] = (gpiod[x] == level[x])
35 * cleared in ISR (STICKY bits)
36 */
37 u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
38};
39
40/* UART GPIO signals */
41#define RC32434_UART0_SOUT (1 << 0)
42#define RC32434_UART0_SIN (1 << 1)
43#define RC32434_UART0_RTS (1 << 2)
44#define RC32434_UART0_CTS (1 << 3)
45
46/* M & P bus GPIO signals */
47#define RC32434_MP_BIT_22 (1 << 4)
48#define RC32434_MP_BIT_23 (1 << 5)
49#define RC32434_MP_BIT_24 (1 << 6)
50#define RC32434_MP_BIT_25 (1 << 7)
51
52/* CPU GPIO signals */
53#define RC32434_CPU_GPIO (1 << 8)
54
55/* Reserved GPIO signals */
56#define RC32434_AF_SPARE_6 (1 << 9)
57#define RC32434_AF_SPARE_4 (1 << 10)
58#define RC32434_AF_SPARE_3 (1 << 11)
59#define RC32434_AF_SPARE_2 (1 << 12)
60
61/* PCI messaging unit */
62#define RC32434_PCI_MSU_GPIO (1 << 13)
63
Florian Fainelli3cd4e062008-08-22 17:00:22 +0200[diff] [blame^]64/* NAND GPIO signals */
65#define GPIO_RDY (1 << 0x08)
66#define GPIO_WPX (1 << 0x09)
67#define GPIO_ALE (1 << 0x0a)
68#define GPIO_CLE (1 << 0x0b)
69
70/* Compact Flash GPIO pin */
71#define CF_GPIO_NUM 13
72
Ralf Baechle73b43902008-07-16 16:12:25 +0100[diff] [blame]73
74extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
75extern unsigned get_434_reg(unsigned reg_offs);
76extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
77extern unsigned char get_latch_u5(void);
78
79extern int rb532_gpio_get_value(unsigned gpio);
80extern void rb532_gpio_set_value(unsigned gpio, int value);
81extern int rb532_gpio_direction_input(unsigned gpio);
82extern int rb532_gpio_direction_output(unsigned gpio, int value);
83extern void rb532_gpio_set_int_level(unsigned gpio, int value);
84extern int rb532_gpio_get_int_level(unsigned gpio);
85extern void rb532_gpio_set_int_status(unsigned gpio, int value);
86extern int rb532_gpio_get_int_status(unsigned gpio);
87
88
89/* Wrappers for the arch-neutral GPIO API */
90
91static inline int gpio_request(unsigned gpio, const char *label)
92{
93 /* Not yet implemented */
94 return 0;
95}
96
97static inline void gpio_free(unsigned gpio)
98{
99 /* Not yet implemented */
100}
101
102static inline int gpio_direction_input(unsigned gpio)
103{
104 return rb532_gpio_direction_input(gpio);
105}
106
107static inline int gpio_direction_output(unsigned gpio, int value)
108{
109 return rb532_gpio_direction_output(gpio, value);
110}
111
112static inline int gpio_get_value(unsigned gpio)
113{
114 return rb532_gpio_get_value(gpio);
115}
116
117static inline void gpio_set_value(unsigned gpio, int value)
118{
119 rb532_gpio_set_value(gpio, value);
120}
121
122static inline int gpio_to_irq(unsigned gpio)
123{
124 return gpio;
125}
126
127static inline int irq_to_gpio(unsigned irq)
128{
129 return irq;
130}
131
132/* For cansleep */
133#include <asm-generic/gpio.h>
134
135#endif /* _RC32434_GPIO_H_ */