| Mark Rutland | fa8ad78 | 2015-07-06 12:23:53 +0100 | [diff] [blame] | 1 | # |
| 2 | # Performance Monitor Drivers |
| 3 | # |
| 4 | |
| 5 | menu "Performance monitor support" |
| Mark Rutland | bddb9b6 | 2017-06-13 13:45:51 +0100 | [diff] [blame] | 6 | depends on PERF_EVENTS |
| Mark Rutland | fa8ad78 | 2015-07-06 12:23:53 +0100 | [diff] [blame] | 7 | |
| Robin Murphy | 3de6be7 | 2018-02-15 18:51:42 +0000 | [diff] [blame^] | 8 | config ARM_CCI_PMU |
| 9 | bool |
| 10 | select ARM_CCI |
| 11 | |
| 12 | config ARM_CCI400_PMU |
| 13 | bool "ARM CCI400 PMU support" |
| 14 | depends on (ARM && CPU_V7) || ARM64 |
| 15 | select ARM_CCI400_COMMON |
| 16 | select ARM_CCI_PMU |
| 17 | help |
| 18 | Support for PMU events monitoring on the ARM CCI-400 (cache coherent |
| 19 | interconnect). CCI-400 supports counting events related to the |
| 20 | connected slave/master interfaces. |
| 21 | |
| 22 | config ARM_CCI5xx_PMU |
| 23 | bool "ARM CCI-500/CCI-550 PMU support" |
| 24 | depends on (ARM && CPU_V7) || ARM64 |
| 25 | select ARM_CCI_PMU |
| 26 | help |
| 27 | Support for PMU events monitoring on the ARM CCI-500/CCI-550 cache |
| 28 | coherent interconnects. Both of them provide 8 independent event counters, |
| 29 | which can count events pertaining to the slave/master interfaces as well |
| 30 | as the internal events to the CCI. |
| 31 | |
| 32 | If unsure, say Y |
| 33 | |
| Robin Murphy | 1888d3d | 2018-02-15 18:51:41 +0000 | [diff] [blame] | 34 | config ARM_CCN |
| 35 | tristate "ARM CCN driver support" |
| 36 | depends on ARM || ARM64 |
| 37 | help |
| 38 | PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) |
| 39 | interconnect. |
| 40 | |
| Mark Rutland | fa8ad78 | 2015-07-06 12:23:53 +0100 | [diff] [blame] | 41 | config ARM_PMU |
| Mark Rutland | bddb9b6 | 2017-06-13 13:45:51 +0100 | [diff] [blame] | 42 | depends on ARM || ARM64 |
| Mark Rutland | fa8ad78 | 2015-07-06 12:23:53 +0100 | [diff] [blame] | 43 | bool "ARM PMU framework" |
| 44 | default y |
| 45 | help |
| 46 | Say y if you want to use CPU performance monitors on ARM-based |
| 47 | systems. |
| 48 | |
| Mark Rutland | 45736a7 | 2017-04-11 09:39:55 +0100 | [diff] [blame] | 49 | config ARM_PMU_ACPI |
| 50 | depends on ARM_PMU && ACPI |
| 51 | def_bool y |
| 52 | |
| Suzuki K Poulose | 7520fa9 | 2018-01-02 11:25:33 +0000 | [diff] [blame] | 53 | config ARM_DSU_PMU |
| 54 | tristate "ARM DynamIQ Shared Unit (DSU) PMU" |
| 55 | depends on ARM64 |
| 56 | help |
| 57 | Provides support for performance monitor unit in ARM DynamIQ Shared |
| 58 | Unit (DSU). The DSU integrates one or more cores with an L3 memory |
| 59 | system, control logic. The PMU allows counting various events related |
| 60 | to DSU. |
| 61 | |
| Shaokun Zhang | 6ce4ef9 | 2017-10-19 19:05:17 +0800 | [diff] [blame] | 62 | config HISI_PMU |
| 63 | bool "HiSilicon SoC PMU" |
| 64 | depends on ARM64 && ACPI |
| 65 | help |
| 66 | Support for HiSilicon SoC uncore performance monitoring |
| 67 | unit (PMU), such as: L3C, HHA and DDRC. |
| 68 | |
| Neil Leeder | 21bdbb7 | 2017-02-07 13:14:04 -0500 | [diff] [blame] | 69 | config QCOM_L2_PMU |
| 70 | bool "Qualcomm Technologies L2-cache PMU" |
| Mark Rutland | bddb9b6 | 2017-06-13 13:45:51 +0100 | [diff] [blame] | 71 | depends on ARCH_QCOM && ARM64 && ACPI |
| Neil Leeder | 21bdbb7 | 2017-02-07 13:14:04 -0500 | [diff] [blame] | 72 | help |
| 73 | Provides support for the L2 cache performance monitor unit (PMU) |
| 74 | in Qualcomm Technologies processors. |
| 75 | Adds the L2 cache PMU into the perf events subsystem for |
| 76 | monitoring L2 cache events. |
| 77 | |
| Agustin Vega-Frias | 3071f13 | 2017-03-31 14:13:43 -0400 | [diff] [blame] | 78 | config QCOM_L3_PMU |
| 79 | bool "Qualcomm Technologies L3-cache PMU" |
| Mark Rutland | bddb9b6 | 2017-06-13 13:45:51 +0100 | [diff] [blame] | 80 | depends on ARCH_QCOM && ARM64 && ACPI |
| Agustin Vega-Frias | 3071f13 | 2017-03-31 14:13:43 -0400 | [diff] [blame] | 81 | select QCOM_IRQ_COMBINER |
| 82 | help |
| 83 | Provides support for the L3 cache performance monitor unit (PMU) |
| 84 | in Qualcomm Technologies processors. |
| 85 | Adds the L3 cache PMU into the perf events subsystem for |
| 86 | monitoring L3 cache events. |
| 87 | |
| Tai Nguyen | 832c927 | 2016-07-15 10:38:04 -0700 | [diff] [blame] | 88 | config XGENE_PMU |
| Mark Rutland | bddb9b6 | 2017-06-13 13:45:51 +0100 | [diff] [blame] | 89 | depends on ARCH_XGENE |
| Tai Nguyen | 832c927 | 2016-07-15 10:38:04 -0700 | [diff] [blame] | 90 | bool "APM X-Gene SoC PMU" |
| 91 | default n |
| 92 | help |
| 93 | Say y if you want to use APM X-Gene SoC performance monitors. |
| 94 | |
| Will Deacon | d5d9696 | 2016-09-22 11:36:32 +0100 | [diff] [blame] | 95 | config ARM_SPE_PMU |
| 96 | tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" |
| 97 | depends on PERF_EVENTS && ARM64 |
| 98 | help |
| 99 | Enable perf support for the ARMv8.2 Statistical Profiling |
| 100 | Extension, which provides periodic sampling of operations in |
| 101 | the CPU pipeline and reports this via the perf AUX interface. |
| 102 | |
| Mark Rutland | fa8ad78 | 2015-07-06 12:23:53 +0100 | [diff] [blame] | 103 | endmenu |