blob: 40406bc2f8af73756d6750bcc3998115dd78b57c [file] [log] [blame]
Jon Loeligeref82a302006-06-17 17:52:55 -05001/*
2 * Driver for Vitesse PHYs
3 *
4 * Author: Kriston Carson
5 *
Andy Flemingfddf86f2011-10-13 04:33:55 +00006 * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc.
Jon Loeligeref82a302006-06-17 17:52:55 -05007 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
Jon Loeligeref82a302006-06-17 17:52:55 -050015#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/mii.h>
18#include <linux/ethtool.h>
19#include <linux/phy.h>
20
21/* Vitesse Extended Control Register 1 */
22#define MII_VSC8244_EXT_CON1 0x17
23#define MII_VSC8244_EXTCON1_INIT 0x0000
Andy Flemingaf2d9402007-07-11 11:42:35 -050024#define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
25#define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
26#define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
27#define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
Jon Loeligeref82a302006-06-17 17:52:55 -050028
29/* Vitesse Interrupt Mask Register */
30#define MII_VSC8244_IMASK 0x19
31#define MII_VSC8244_IMASK_IEN 0x8000
32#define MII_VSC8244_IMASK_SPEED 0x4000
33#define MII_VSC8244_IMASK_LINK 0x2000
34#define MII_VSC8244_IMASK_DUPLEX 0x1000
35#define MII_VSC8244_IMASK_MASK 0xf000
36
Trent Piepho11c6dd22008-11-25 01:00:47 -080037#define MII_VSC8221_IMASK_MASK 0xa000
38
Jon Loeligeref82a302006-06-17 17:52:55 -050039/* Vitesse Interrupt Status Register */
40#define MII_VSC8244_ISTAT 0x1a
41#define MII_VSC8244_ISTAT_STATUS 0x8000
42#define MII_VSC8244_ISTAT_SPEED 0x4000
43#define MII_VSC8244_ISTAT_LINK 0x2000
44#define MII_VSC8244_ISTAT_DUPLEX 0x1000
45
46/* Vitesse Auxiliary Control/Status Register */
Michal Simek2a8626d2013-05-30 20:08:23 +000047#define MII_VSC8244_AUX_CONSTAT 0x1c
48#define MII_VSC8244_AUXCONSTAT_INIT 0x0000
49#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
50#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
51#define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
52#define MII_VSC8244_AUXCONSTAT_100 0x0008
Jon Loeligeref82a302006-06-17 17:52:55 -050053
Trent Piepho11c6dd22008-11-25 01:00:47 -080054#define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */
55#define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
56
Andy Fleming05080192013-11-20 16:38:16 -060057#define PHY_ID_VSC8234 0x000fc620
Trent Piepho11c6dd22008-11-25 01:00:47 -080058#define PHY_ID_VSC8244 0x000fc6c0
shaohui xiec2efef72013-11-20 16:38:17 -060059#define PHY_ID_VSC8574 0x000704a0
Sandeep Singh06ae4f82013-11-20 16:38:18 -060060#define PHY_ID_VSC8662 0x00070660
Trent Piepho11c6dd22008-11-25 01:00:47 -080061#define PHY_ID_VSC8221 0x000fc550
Michal Simek5a1cebd2013-05-30 20:08:24 +000062#define PHY_ID_VSC8211 0x000fc4b0
Trent Piepho11c6dd22008-11-25 01:00:47 -080063
Jon Loeligeref82a302006-06-17 17:52:55 -050064MODULE_DESCRIPTION("Vitesse PHY driver");
65MODULE_AUTHOR("Kriston Carson");
66MODULE_LICENSE("GPL");
67
stephen hemmingerbaec1262013-03-08 09:07:42 +000068static int vsc824x_add_skew(struct phy_device *phydev)
Andy Flemingfddf86f2011-10-13 04:33:55 +000069{
70 int err;
71 int extcon;
72
73 extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
74
75 if (extcon < 0)
76 return extcon;
77
78 extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
79 MII_VSC8244_EXTCON1_RX_SKEW_MASK);
80
81 extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
82 MII_VSC8244_EXTCON1_RX_SKEW);
83
84 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
85
86 return err;
87}
Andy Flemingfddf86f2011-10-13 04:33:55 +000088
Jon Loeligeref82a302006-06-17 17:52:55 -050089static int vsc824x_config_init(struct phy_device *phydev)
90{
91 int err;
92
93 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
94 MII_VSC8244_AUXCONSTAT_INIT);
95 if (err < 0)
96 return err;
97
Andy Flemingaf2d9402007-07-11 11:42:35 -050098 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
Andy Flemingfddf86f2011-10-13 04:33:55 +000099 err = vsc824x_add_skew(phydev);
Andy Flemingaf2d9402007-07-11 11:42:35 -0500100
Jon Loeligeref82a302006-06-17 17:52:55 -0500101 return err;
102}
103
104static int vsc824x_ack_interrupt(struct phy_device *phydev)
105{
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500106 int err = 0;
Michal Simek2a8626d2013-05-30 20:08:23 +0000107
108 /* Don't bother to ACK the interrupts if interrupts
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500109 * are disabled. The 824x cannot clear the interrupts
110 * if they are disabled.
111 */
112 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
113 err = phy_read(phydev, MII_VSC8244_ISTAT);
Jon Loeligeref82a302006-06-17 17:52:55 -0500114
115 return (err < 0) ? err : 0;
116}
117
Trent Piepho11c6dd22008-11-25 01:00:47 -0800118static int vsc82xx_config_intr(struct phy_device *phydev)
Jon Loeligeref82a302006-06-17 17:52:55 -0500119{
120 int err;
121
122 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
123 err = phy_write(phydev, MII_VSC8244_IMASK,
Andy Fleming05080192013-11-20 16:38:16 -0600124 (phydev->drv->phy_id == PHY_ID_VSC8234 ||
shaohui xiec2efef72013-11-20 16:38:17 -0600125 phydev->drv->phy_id == PHY_ID_VSC8244 ||
126 phydev->drv->phy_id == PHY_ID_VSC8574) ?
Trent Piepho11c6dd22008-11-25 01:00:47 -0800127 MII_VSC8244_IMASK_MASK :
128 MII_VSC8221_IMASK_MASK);
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500129 else {
Michal Simek2a8626d2013-05-30 20:08:23 +0000130 /* The Vitesse PHY cannot clear the interrupt
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500131 * once it has disabled them, so we clear them first
132 */
133 err = phy_read(phydev, MII_VSC8244_ISTAT);
134
Andy Fleming52cb1c22007-07-18 01:06:28 -0500135 if (err < 0)
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500136 return err;
137
Jon Loeligeref82a302006-06-17 17:52:55 -0500138 err = phy_write(phydev, MII_VSC8244_IMASK, 0);
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500139 }
140
Jon Loeligeref82a302006-06-17 17:52:55 -0500141 return err;
142}
143
Trent Piepho11c6dd22008-11-25 01:00:47 -0800144static int vsc8221_config_init(struct phy_device *phydev)
Jon Loeligeref82a302006-06-17 17:52:55 -0500145{
Trent Piepho11c6dd22008-11-25 01:00:47 -0800146 int err;
147
148 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
149 MII_VSC8221_AUXCONSTAT_INIT);
150 return err;
151
152 /* Perhaps we should set EXT_CON1 based on the interface?
Michal Simek2a8626d2013-05-30 20:08:23 +0000153 * Options are 802.3Z SerDes or SGMII
154 */
Jon Loeligeref82a302006-06-17 17:52:55 -0500155}
156
Andy Fleming05080192013-11-20 16:38:16 -0600157/* Vitesse 82xx */
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000158static struct phy_driver vsc82xx_driver[] = {
159{
Andy Fleming05080192013-11-20 16:38:16 -0600160 .phy_id = PHY_ID_VSC8234,
161 .name = "Vitesse VSC8234",
162 .phy_id_mask = 0x000ffff0,
163 .features = PHY_GBIT_FEATURES,
164 .flags = PHY_HAS_INTERRUPT,
165 .config_init = &vsc824x_config_init,
166 .config_aneg = &genphy_config_aneg,
167 .read_status = &genphy_read_status,
168 .ack_interrupt = &vsc824x_ack_interrupt,
169 .config_intr = &vsc82xx_config_intr,
170 .driver = { .owner = THIS_MODULE,},
171}, {
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000172 .phy_id = PHY_ID_VSC8244,
173 .name = "Vitesse VSC8244",
174 .phy_id_mask = 0x000fffc0,
175 .features = PHY_GBIT_FEATURES,
176 .flags = PHY_HAS_INTERRUPT,
177 .config_init = &vsc824x_config_init,
178 .config_aneg = &genphy_config_aneg,
179 .read_status = &genphy_read_status,
180 .ack_interrupt = &vsc824x_ack_interrupt,
181 .config_intr = &vsc82xx_config_intr,
182 .driver = { .owner = THIS_MODULE,},
183}, {
shaohui xiec2efef72013-11-20 16:38:17 -0600184 .phy_id = PHY_ID_VSC8574,
185 .name = "Vitesse VSC8574",
186 .phy_id_mask = 0x000ffff0,
187 .features = PHY_GBIT_FEATURES,
188 .flags = PHY_HAS_INTERRUPT,
189 .config_init = &vsc824x_config_init,
190 .config_aneg = &genphy_config_aneg,
191 .read_status = &genphy_read_status,
192 .ack_interrupt = &vsc824x_ack_interrupt,
193 .config_intr = &vsc82xx_config_intr,
194 .driver = { .owner = THIS_MODULE,},
195}, {
Sandeep Singh06ae4f82013-11-20 16:38:18 -0600196 .phy_id = PHY_ID_VSC8662,
197 .name = "Vitesse VSC8662",
198 .phy_id_mask = 0x000ffff0,
199 .features = PHY_GBIT_FEATURES,
200 .flags = PHY_HAS_INTERRUPT,
201 .config_init = &vsc824x_config_init,
202 .config_aneg = &genphy_config_aneg,
203 .read_status = &genphy_read_status,
204 .ack_interrupt = &vsc824x_ack_interrupt,
205 .config_intr = &vsc82xx_config_intr,
206 .driver = { .owner = THIS_MODULE,},
207}, {
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000208 /* Vitesse 8221 */
Trent Piepho11c6dd22008-11-25 01:00:47 -0800209 .phy_id = PHY_ID_VSC8221,
210 .phy_id_mask = 0x000ffff0,
211 .name = "Vitesse VSC8221",
212 .features = PHY_GBIT_FEATURES,
213 .flags = PHY_HAS_INTERRUPT,
214 .config_init = &vsc8221_config_init,
215 .config_aneg = &genphy_config_aneg,
216 .read_status = &genphy_read_status,
217 .ack_interrupt = &vsc824x_ack_interrupt,
218 .config_intr = &vsc82xx_config_intr,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000219 .driver = { .owner = THIS_MODULE,},
Michal Simek5a1cebd2013-05-30 20:08:24 +0000220}, {
221 /* Vitesse 8211 */
222 .phy_id = PHY_ID_VSC8211,
223 .phy_id_mask = 0x000ffff0,
224 .name = "Vitesse VSC8211",
225 .features = PHY_GBIT_FEATURES,
226 .flags = PHY_HAS_INTERRUPT,
227 .config_init = &vsc8221_config_init,
228 .config_aneg = &genphy_config_aneg,
229 .read_status = &genphy_read_status,
230 .ack_interrupt = &vsc824x_ack_interrupt,
231 .config_intr = &vsc82xx_config_intr,
232 .driver = { .owner = THIS_MODULE,},
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000233} };
Trent Piepho11c6dd22008-11-25 01:00:47 -0800234
235static int __init vsc82xx_init(void)
236{
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000237 return phy_drivers_register(vsc82xx_driver,
238 ARRAY_SIZE(vsc82xx_driver));
Trent Piepho11c6dd22008-11-25 01:00:47 -0800239}
240
241static void __exit vsc82xx_exit(void)
Jon Loeligeref82a302006-06-17 17:52:55 -0500242{
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000243 return phy_drivers_unregister(vsc82xx_driver,
244 ARRAY_SIZE(vsc82xx_driver));
Jon Loeligeref82a302006-06-17 17:52:55 -0500245}
246
Trent Piepho11c6dd22008-11-25 01:00:47 -0800247module_init(vsc82xx_init);
248module_exit(vsc82xx_exit);
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000249
Uwe Kleine-Königcf93c942010-10-03 23:43:32 +0000250static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
Andy Fleming05080192013-11-20 16:38:16 -0600251 { PHY_ID_VSC8234, 0x000ffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000252 { PHY_ID_VSC8244, 0x000fffc0 },
shaohui xiec2efef72013-11-20 16:38:17 -0600253 { PHY_ID_VSC8574, 0x000ffff0 },
Sandeep Singh06ae4f82013-11-20 16:38:18 -0600254 { PHY_ID_VSC8662, 0x000ffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000255 { PHY_ID_VSC8221, 0x000ffff0 },
Michal Simek5a1cebd2013-05-30 20:08:24 +0000256 { PHY_ID_VSC8211, 0x000ffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000257 { }
258};
259
260MODULE_DEVICE_TABLE(mdio, vitesse_tbl);