blob: 3492b53912731eae9407fe6dbb15468d35429263 [file] [log] [blame]
Jon Loeligeref82a302006-06-17 17:52:55 -05001/*
2 * Driver for Vitesse PHYs
3 *
4 * Author: Kriston Carson
5 *
Andy Flemingfddf86f2011-10-13 04:33:55 +00006 * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc.
Jon Loeligeref82a302006-06-17 17:52:55 -05007 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
Jon Loeligeref82a302006-06-17 17:52:55 -050015#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/mii.h>
18#include <linux/ethtool.h>
19#include <linux/phy.h>
20
21/* Vitesse Extended Control Register 1 */
22#define MII_VSC8244_EXT_CON1 0x17
23#define MII_VSC8244_EXTCON1_INIT 0x0000
Andy Flemingaf2d9402007-07-11 11:42:35 -050024#define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
25#define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
26#define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
27#define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
Jon Loeligeref82a302006-06-17 17:52:55 -050028
29/* Vitesse Interrupt Mask Register */
30#define MII_VSC8244_IMASK 0x19
31#define MII_VSC8244_IMASK_IEN 0x8000
32#define MII_VSC8244_IMASK_SPEED 0x4000
33#define MII_VSC8244_IMASK_LINK 0x2000
34#define MII_VSC8244_IMASK_DUPLEX 0x1000
35#define MII_VSC8244_IMASK_MASK 0xf000
36
Trent Piepho11c6dd22008-11-25 01:00:47 -080037#define MII_VSC8221_IMASK_MASK 0xa000
38
Jon Loeligeref82a302006-06-17 17:52:55 -050039/* Vitesse Interrupt Status Register */
40#define MII_VSC8244_ISTAT 0x1a
41#define MII_VSC8244_ISTAT_STATUS 0x8000
42#define MII_VSC8244_ISTAT_SPEED 0x4000
43#define MII_VSC8244_ISTAT_LINK 0x2000
44#define MII_VSC8244_ISTAT_DUPLEX 0x1000
45
46/* Vitesse Auxiliary Control/Status Register */
47#define MII_VSC8244_AUX_CONSTAT 0x1c
Andy Flemingaf2d9402007-07-11 11:42:35 -050048#define MII_VSC8244_AUXCONSTAT_INIT 0x0000
Jon Loeligeref82a302006-06-17 17:52:55 -050049#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
50#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
51#define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
52#define MII_VSC8244_AUXCONSTAT_100 0x0008
53
Trent Piepho11c6dd22008-11-25 01:00:47 -080054#define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */
55#define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
56
57#define PHY_ID_VSC8244 0x000fc6c0
58#define PHY_ID_VSC8221 0x000fc550
59
Jon Loeligeref82a302006-06-17 17:52:55 -050060MODULE_DESCRIPTION("Vitesse PHY driver");
61MODULE_AUTHOR("Kriston Carson");
62MODULE_LICENSE("GPL");
63
stephen hemmingerbaec1262013-03-08 09:07:42 +000064static int vsc824x_add_skew(struct phy_device *phydev)
Andy Flemingfddf86f2011-10-13 04:33:55 +000065{
66 int err;
67 int extcon;
68
69 extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
70
71 if (extcon < 0)
72 return extcon;
73
74 extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
75 MII_VSC8244_EXTCON1_RX_SKEW_MASK);
76
77 extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
78 MII_VSC8244_EXTCON1_RX_SKEW);
79
80 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
81
82 return err;
83}
Andy Flemingfddf86f2011-10-13 04:33:55 +000084
Jon Loeligeref82a302006-06-17 17:52:55 -050085static int vsc824x_config_init(struct phy_device *phydev)
86{
87 int err;
88
89 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
90 MII_VSC8244_AUXCONSTAT_INIT);
91 if (err < 0)
92 return err;
93
Andy Flemingaf2d9402007-07-11 11:42:35 -050094 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
Andy Flemingfddf86f2011-10-13 04:33:55 +000095 err = vsc824x_add_skew(phydev);
Andy Flemingaf2d9402007-07-11 11:42:35 -050096
Jon Loeligeref82a302006-06-17 17:52:55 -050097 return err;
98}
99
100static int vsc824x_ack_interrupt(struct phy_device *phydev)
101{
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500102 int err = 0;
103
104 /*
105 * Don't bother to ACK the interrupts if interrupts
106 * are disabled. The 824x cannot clear the interrupts
107 * if they are disabled.
108 */
109 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
110 err = phy_read(phydev, MII_VSC8244_ISTAT);
Jon Loeligeref82a302006-06-17 17:52:55 -0500111
112 return (err < 0) ? err : 0;
113}
114
Trent Piepho11c6dd22008-11-25 01:00:47 -0800115static int vsc82xx_config_intr(struct phy_device *phydev)
Jon Loeligeref82a302006-06-17 17:52:55 -0500116{
117 int err;
118
119 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
120 err = phy_write(phydev, MII_VSC8244_IMASK,
Trent Piepho11c6dd22008-11-25 01:00:47 -0800121 phydev->drv->phy_id == PHY_ID_VSC8244 ?
122 MII_VSC8244_IMASK_MASK :
123 MII_VSC8221_IMASK_MASK);
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500124 else {
125 /*
126 * The Vitesse PHY cannot clear the interrupt
127 * once it has disabled them, so we clear them first
128 */
129 err = phy_read(phydev, MII_VSC8244_ISTAT);
130
Andy Fleming52cb1c22007-07-18 01:06:28 -0500131 if (err < 0)
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500132 return err;
133
Jon Loeligeref82a302006-06-17 17:52:55 -0500134 err = phy_write(phydev, MII_VSC8244_IMASK, 0);
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500135 }
136
Jon Loeligeref82a302006-06-17 17:52:55 -0500137 return err;
138}
139
Trent Piepho11c6dd22008-11-25 01:00:47 -0800140static int vsc8221_config_init(struct phy_device *phydev)
Jon Loeligeref82a302006-06-17 17:52:55 -0500141{
Trent Piepho11c6dd22008-11-25 01:00:47 -0800142 int err;
143
144 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
145 MII_VSC8221_AUXCONSTAT_INIT);
146 return err;
147
148 /* Perhaps we should set EXT_CON1 based on the interface?
149 Options are 802.3Z SerDes or SGMII */
Jon Loeligeref82a302006-06-17 17:52:55 -0500150}
151
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000152/* Vitesse 824x */
153static struct phy_driver vsc82xx_driver[] = {
154{
155 .phy_id = PHY_ID_VSC8244,
156 .name = "Vitesse VSC8244",
157 .phy_id_mask = 0x000fffc0,
158 .features = PHY_GBIT_FEATURES,
159 .flags = PHY_HAS_INTERRUPT,
160 .config_init = &vsc824x_config_init,
161 .config_aneg = &genphy_config_aneg,
162 .read_status = &genphy_read_status,
163 .ack_interrupt = &vsc824x_ack_interrupt,
164 .config_intr = &vsc82xx_config_intr,
165 .driver = { .owner = THIS_MODULE,},
166}, {
167 /* Vitesse 8221 */
Trent Piepho11c6dd22008-11-25 01:00:47 -0800168 .phy_id = PHY_ID_VSC8221,
169 .phy_id_mask = 0x000ffff0,
170 .name = "Vitesse VSC8221",
171 .features = PHY_GBIT_FEATURES,
172 .flags = PHY_HAS_INTERRUPT,
173 .config_init = &vsc8221_config_init,
174 .config_aneg = &genphy_config_aneg,
175 .read_status = &genphy_read_status,
176 .ack_interrupt = &vsc824x_ack_interrupt,
177 .config_intr = &vsc82xx_config_intr,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000178 .driver = { .owner = THIS_MODULE,},
179} };
Trent Piepho11c6dd22008-11-25 01:00:47 -0800180
181static int __init vsc82xx_init(void)
182{
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000183 return phy_drivers_register(vsc82xx_driver,
184 ARRAY_SIZE(vsc82xx_driver));
Trent Piepho11c6dd22008-11-25 01:00:47 -0800185}
186
187static void __exit vsc82xx_exit(void)
Jon Loeligeref82a302006-06-17 17:52:55 -0500188{
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000189 return phy_drivers_unregister(vsc82xx_driver,
190 ARRAY_SIZE(vsc82xx_driver));
Jon Loeligeref82a302006-06-17 17:52:55 -0500191}
192
Trent Piepho11c6dd22008-11-25 01:00:47 -0800193module_init(vsc82xx_init);
194module_exit(vsc82xx_exit);
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000195
Uwe Kleine-Königcf93c942010-10-03 23:43:32 +0000196static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000197 { PHY_ID_VSC8244, 0x000fffc0 },
198 { PHY_ID_VSC8221, 0x000ffff0 },
199 { }
200};
201
202MODULE_DEVICE_TABLE(mdio, vitesse_tbl);