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gerrit-public.fairphone.software / kernel / msm-5.4 / 4127d5d59f8135e3c187b8daa2540691761938ce / . / sound / soc / codecs / max98088.c
blob: 31912d59702c886ebb48a3dcbde96a34d064427f [file] [log] [blame]
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1/*
2 * max98088.c -- MAX98088 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]18#include <linux/regmap.h>
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]19#include <sound/core.h>
20#include <sound/pcm.h>
21#include <sound/pcm_params.h>
22#include <sound/soc.h>
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]23#include <sound/initval.h>
24#include <sound/tlv.h>
25#include <linux/slab.h>
26#include <asm/div64.h>
27#include <sound/max98088.h>
28#include "max98088.h"
29
Jesse Marroquinfb762a52010-11-17 14:26:40 -0600[diff] [blame]30enum max98088_type {
31 MAX98088,
32 MAX98089,
33};
34
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]35struct max98088_cdata {
36 unsigned int rate;
37 unsigned int fmt;
38 int eq_sel;
39};
40
41struct max98088_priv {
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]42 struct regmap *regmap;
Mark Brown356d86e2013-09-23 17:22:17 +0100[diff] [blame]43 enum max98088_type devtype;
44 struct max98088_pdata *pdata;
45 unsigned int sysclk;
46 struct max98088_cdata dai[2];
47 int eq_textcnt;
48 const char **eq_texts;
49 struct soc_enum eq_enum;
50 u8 ina_state;
51 u8 inb_state;
52 unsigned int ex_mode;
53 unsigned int digmic;
54 unsigned int mic1pre;
55 unsigned int mic2pre;
56 unsigned int extmic_mode;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]57};
58
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]59static const struct reg_default max98088_reg[] = {
60 { 0xf, 0x00 }, /* 0F interrupt enable */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]61
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]62 { 0x10, 0x00 }, /* 10 master clock */
63 { 0x11, 0x00 }, /* 11 DAI1 clock mode */
64 { 0x12, 0x00 }, /* 12 DAI1 clock control */
65 { 0x13, 0x00 }, /* 13 DAI1 clock control */
66 { 0x14, 0x00 }, /* 14 DAI1 format */
67 { 0x15, 0x00 }, /* 15 DAI1 clock */
68 { 0x16, 0x00 }, /* 16 DAI1 config */
69 { 0x17, 0x00 }, /* 17 DAI1 TDM */
70 { 0x18, 0x00 }, /* 18 DAI1 filters */
71 { 0x19, 0x00 }, /* 19 DAI2 clock mode */
72 { 0x1a, 0x00 }, /* 1A DAI2 clock control */
73 { 0x1b, 0x00 }, /* 1B DAI2 clock control */
74 { 0x1c, 0x00 }, /* 1C DAI2 format */
75 { 0x1d, 0x00 }, /* 1D DAI2 clock */
76 { 0x1e, 0x00 }, /* 1E DAI2 config */
77 { 0x1f, 0x00 }, /* 1F DAI2 TDM */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]78
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]79 { 0x20, 0x00 }, /* 20 DAI2 filters */
80 { 0x21, 0x00 }, /* 21 data config */
81 { 0x22, 0x00 }, /* 22 DAC mixer */
82 { 0x23, 0x00 }, /* 23 left ADC mixer */
83 { 0x24, 0x00 }, /* 24 right ADC mixer */
84 { 0x25, 0x00 }, /* 25 left HP mixer */
85 { 0x26, 0x00 }, /* 26 right HP mixer */
86 { 0x27, 0x00 }, /* 27 HP control */
87 { 0x28, 0x00 }, /* 28 left REC mixer */
88 { 0x29, 0x00 }, /* 29 right REC mixer */
89 { 0x2a, 0x00 }, /* 2A REC control */
90 { 0x2b, 0x00 }, /* 2B left SPK mixer */
91 { 0x2c, 0x00 }, /* 2C right SPK mixer */
92 { 0x2d, 0x00 }, /* 2D SPK control */
93 { 0x2e, 0x00 }, /* 2E sidetone */
94 { 0x2f, 0x00 }, /* 2F DAI1 playback level */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]95
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]96 { 0x30, 0x00 }, /* 30 DAI1 playback level */
97 { 0x31, 0x00 }, /* 31 DAI2 playback level */
98 { 0x32, 0x00 }, /* 32 DAI2 playbakc level */
99 { 0x33, 0x00 }, /* 33 left ADC level */
100 { 0x34, 0x00 }, /* 34 right ADC level */
101 { 0x35, 0x00 }, /* 35 MIC1 level */
102 { 0x36, 0x00 }, /* 36 MIC2 level */
103 { 0x37, 0x00 }, /* 37 INA level */
104 { 0x38, 0x00 }, /* 38 INB level */
105 { 0x39, 0x00 }, /* 39 left HP volume */
106 { 0x3a, 0x00 }, /* 3A right HP volume */
107 { 0x3b, 0x00 }, /* 3B left REC volume */
108 { 0x3c, 0x00 }, /* 3C right REC volume */
109 { 0x3d, 0x00 }, /* 3D left SPK volume */
110 { 0x3e, 0x00 }, /* 3E right SPK volume */
111 { 0x3f, 0x00 }, /* 3F MIC config */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]112
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]113 { 0x40, 0x00 }, /* 40 MIC threshold */
114 { 0x41, 0x00 }, /* 41 excursion limiter filter */
115 { 0x42, 0x00 }, /* 42 excursion limiter threshold */
116 { 0x43, 0x00 }, /* 43 ALC */
117 { 0x44, 0x00 }, /* 44 power limiter threshold */
118 { 0x45, 0x00 }, /* 45 power limiter config */
119 { 0x46, 0x00 }, /* 46 distortion limiter config */
120 { 0x47, 0x00 }, /* 47 audio input */
121 { 0x48, 0x00 }, /* 48 microphone */
122 { 0x49, 0x00 }, /* 49 level control */
123 { 0x4a, 0x00 }, /* 4A bypass switches */
124 { 0x4b, 0x00 }, /* 4B jack detect */
125 { 0x4c, 0x00 }, /* 4C input enable */
126 { 0x4d, 0x00 }, /* 4D output enable */
127 { 0x4e, 0xF0 }, /* 4E bias control */
128 { 0x4f, 0x00 }, /* 4F DAC power */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]129
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]130 { 0x50, 0x0F }, /* 50 DAC power */
131 { 0x51, 0x00 }, /* 51 system */
132 { 0x52, 0x00 }, /* 52 DAI1 EQ1 */
133 { 0x53, 0x00 }, /* 53 DAI1 EQ1 */
134 { 0x54, 0x00 }, /* 54 DAI1 EQ1 */
135 { 0x55, 0x00 }, /* 55 DAI1 EQ1 */
136 { 0x56, 0x00 }, /* 56 DAI1 EQ1 */
137 { 0x57, 0x00 }, /* 57 DAI1 EQ1 */
138 { 0x58, 0x00 }, /* 58 DAI1 EQ1 */
139 { 0x59, 0x00 }, /* 59 DAI1 EQ1 */
140 { 0x5a, 0x00 }, /* 5A DAI1 EQ1 */
141 { 0x5b, 0x00 }, /* 5B DAI1 EQ1 */
142 { 0x5c, 0x00 }, /* 5C DAI1 EQ2 */
143 { 0x5d, 0x00 }, /* 5D DAI1 EQ2 */
144 { 0x5e, 0x00 }, /* 5E DAI1 EQ2 */
145 { 0x5f, 0x00 }, /* 5F DAI1 EQ2 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]146
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]147 { 0x60, 0x00 }, /* 60 DAI1 EQ2 */
148 { 0x61, 0x00 }, /* 61 DAI1 EQ2 */
149 { 0x62, 0x00 }, /* 62 DAI1 EQ2 */
150 { 0x63, 0x00 }, /* 63 DAI1 EQ2 */
151 { 0x64, 0x00 }, /* 64 DAI1 EQ2 */
152 { 0x65, 0x00 }, /* 65 DAI1 EQ2 */
153 { 0x66, 0x00 }, /* 66 DAI1 EQ3 */
154 { 0x67, 0x00 }, /* 67 DAI1 EQ3 */
155 { 0x68, 0x00 }, /* 68 DAI1 EQ3 */
156 { 0x69, 0x00 }, /* 69 DAI1 EQ3 */
157 { 0x6a, 0x00 }, /* 6A DAI1 EQ3 */
158 { 0x6b, 0x00 }, /* 6B DAI1 EQ3 */
159 { 0x6c, 0x00 }, /* 6C DAI1 EQ3 */
160 { 0x6d, 0x00 }, /* 6D DAI1 EQ3 */
161 { 0x6e, 0x00 }, /* 6E DAI1 EQ3 */
162 { 0x6f, 0x00 }, /* 6F DAI1 EQ3 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]163
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]164 { 0x70, 0x00 }, /* 70 DAI1 EQ4 */
165 { 0x71, 0x00 }, /* 71 DAI1 EQ4 */
166 { 0x72, 0x00 }, /* 72 DAI1 EQ4 */
167 { 0x73, 0x00 }, /* 73 DAI1 EQ4 */
168 { 0x74, 0x00 }, /* 74 DAI1 EQ4 */
169 { 0x75, 0x00 }, /* 75 DAI1 EQ4 */
170 { 0x76, 0x00 }, /* 76 DAI1 EQ4 */
171 { 0x77, 0x00 }, /* 77 DAI1 EQ4 */
172 { 0x78, 0x00 }, /* 78 DAI1 EQ4 */
173 { 0x79, 0x00 }, /* 79 DAI1 EQ4 */
174 { 0x7a, 0x00 }, /* 7A DAI1 EQ5 */
175 { 0x7b, 0x00 }, /* 7B DAI1 EQ5 */
176 { 0x7c, 0x00 }, /* 7C DAI1 EQ5 */
177 { 0x7d, 0x00 }, /* 7D DAI1 EQ5 */
178 { 0x7e, 0x00 }, /* 7E DAI1 EQ5 */
179 { 0x7f, 0x00 }, /* 7F DAI1 EQ5 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]180
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]181 { 0x80, 0x00 }, /* 80 DAI1 EQ5 */
182 { 0x81, 0x00 }, /* 81 DAI1 EQ5 */
183 { 0x82, 0x00 }, /* 82 DAI1 EQ5 */
184 { 0x83, 0x00 }, /* 83 DAI1 EQ5 */
185 { 0x84, 0x00 }, /* 84 DAI2 EQ1 */
186 { 0x85, 0x00 }, /* 85 DAI2 EQ1 */
187 { 0x86, 0x00 }, /* 86 DAI2 EQ1 */
188 { 0x87, 0x00 }, /* 87 DAI2 EQ1 */
189 { 0x88, 0x00 }, /* 88 DAI2 EQ1 */
190 { 0x89, 0x00 }, /* 89 DAI2 EQ1 */
191 { 0x8a, 0x00 }, /* 8A DAI2 EQ1 */
192 { 0x8b, 0x00 }, /* 8B DAI2 EQ1 */
193 { 0x8c, 0x00 }, /* 8C DAI2 EQ1 */
194 { 0x8d, 0x00 }, /* 8D DAI2 EQ1 */
195 { 0x8e, 0x00 }, /* 8E DAI2 EQ2 */
196 { 0x8f, 0x00 }, /* 8F DAI2 EQ2 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]197
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]198 { 0x90, 0x00 }, /* 90 DAI2 EQ2 */
199 { 0x91, 0x00 }, /* 91 DAI2 EQ2 */
200 { 0x92, 0x00 }, /* 92 DAI2 EQ2 */
201 { 0x93, 0x00 }, /* 93 DAI2 EQ2 */
202 { 0x94, 0x00 }, /* 94 DAI2 EQ2 */
203 { 0x95, 0x00 }, /* 95 DAI2 EQ2 */
204 { 0x96, 0x00 }, /* 96 DAI2 EQ2 */
205 { 0x97, 0x00 }, /* 97 DAI2 EQ2 */
206 { 0x98, 0x00 }, /* 98 DAI2 EQ3 */
207 { 0x99, 0x00 }, /* 99 DAI2 EQ3 */
208 { 0x9a, 0x00 }, /* 9A DAI2 EQ3 */
209 { 0x9b, 0x00 }, /* 9B DAI2 EQ3 */
210 { 0x9c, 0x00 }, /* 9C DAI2 EQ3 */
211 { 0x9d, 0x00 }, /* 9D DAI2 EQ3 */
212 { 0x9e, 0x00 }, /* 9E DAI2 EQ3 */
213 { 0x9f, 0x00 }, /* 9F DAI2 EQ3 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]214
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]215 { 0xa0, 0x00 }, /* A0 DAI2 EQ3 */
216 { 0xa1, 0x00 }, /* A1 DAI2 EQ3 */
217 { 0xa2, 0x00 }, /* A2 DAI2 EQ4 */
218 { 0xa3, 0x00 }, /* A3 DAI2 EQ4 */
219 { 0xa4, 0x00 }, /* A4 DAI2 EQ4 */
220 { 0xa5, 0x00 }, /* A5 DAI2 EQ4 */
221 { 0xa6, 0x00 }, /* A6 DAI2 EQ4 */
222 { 0xa7, 0x00 }, /* A7 DAI2 EQ4 */
223 { 0xa8, 0x00 }, /* A8 DAI2 EQ4 */
224 { 0xa9, 0x00 }, /* A9 DAI2 EQ4 */
225 { 0xaa, 0x00 }, /* AA DAI2 EQ4 */
226 { 0xab, 0x00 }, /* AB DAI2 EQ4 */
227 { 0xac, 0x00 }, /* AC DAI2 EQ5 */
228 { 0xad, 0x00 }, /* AD DAI2 EQ5 */
229 { 0xae, 0x00 }, /* AE DAI2 EQ5 */
230 { 0xaf, 0x00 }, /* AF DAI2 EQ5 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]231
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]232 { 0xb0, 0x00 }, /* B0 DAI2 EQ5 */
233 { 0xb1, 0x00 }, /* B1 DAI2 EQ5 */
234 { 0xb2, 0x00 }, /* B2 DAI2 EQ5 */
235 { 0xb3, 0x00 }, /* B3 DAI2 EQ5 */
236 { 0xb4, 0x00 }, /* B4 DAI2 EQ5 */
237 { 0xb5, 0x00 }, /* B5 DAI2 EQ5 */
238 { 0xb6, 0x00 }, /* B6 DAI1 biquad */
239 { 0xb7, 0x00 }, /* B7 DAI1 biquad */
240 { 0xb8 ,0x00 }, /* B8 DAI1 biquad */
241 { 0xb9, 0x00 }, /* B9 DAI1 biquad */
242 { 0xba, 0x00 }, /* BA DAI1 biquad */
243 { 0xbb, 0x00 }, /* BB DAI1 biquad */
244 { 0xbc, 0x00 }, /* BC DAI1 biquad */
245 { 0xbd, 0x00 }, /* BD DAI1 biquad */
246 { 0xbe, 0x00 }, /* BE DAI1 biquad */
247 { 0xbf, 0x00 }, /* BF DAI1 biquad */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]248
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]249 { 0xc0, 0x00 }, /* C0 DAI2 biquad */
250 { 0xc1, 0x00 }, /* C1 DAI2 biquad */
251 { 0xc2, 0x00 }, /* C2 DAI2 biquad */
252 { 0xc3, 0x00 }, /* C3 DAI2 biquad */
253 { 0xc4, 0x00 }, /* C4 DAI2 biquad */
254 { 0xc5, 0x00 }, /* C5 DAI2 biquad */
255 { 0xc6, 0x00 }, /* C6 DAI2 biquad */
256 { 0xc7, 0x00 }, /* C7 DAI2 biquad */
257 { 0xc8, 0x00 }, /* C8 DAI2 biquad */
258 { 0xc9, 0x00 }, /* C9 DAI2 biquad */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]259};
260
261static struct {
262 int readable;
263 int writable;
264 int vol;
265} max98088_access[M98088_REG_CNT] = {
266 { 0xFF, 0xFF, 1 }, /* 00 IRQ status */
267 { 0xFF, 0x00, 1 }, /* 01 MIC status */
268 { 0xFF, 0x00, 1 }, /* 02 jack status */
269 { 0x1F, 0x1F, 1 }, /* 03 battery voltage */
270 { 0xFF, 0xFF, 0 }, /* 04 */
271 { 0xFF, 0xFF, 0 }, /* 05 */
272 { 0xFF, 0xFF, 0 }, /* 06 */
273 { 0xFF, 0xFF, 0 }, /* 07 */
274 { 0xFF, 0xFF, 0 }, /* 08 */
275 { 0xFF, 0xFF, 0 }, /* 09 */
276 { 0xFF, 0xFF, 0 }, /* 0A */
277 { 0xFF, 0xFF, 0 }, /* 0B */
278 { 0xFF, 0xFF, 0 }, /* 0C */
279 { 0xFF, 0xFF, 0 }, /* 0D */
280 { 0xFF, 0xFF, 0 }, /* 0E */
281 { 0xFF, 0xFF, 0 }, /* 0F interrupt enable */
282
283 { 0xFF, 0xFF, 0 }, /* 10 master clock */
284 { 0xFF, 0xFF, 0 }, /* 11 DAI1 clock mode */
285 { 0xFF, 0xFF, 0 }, /* 12 DAI1 clock control */
286 { 0xFF, 0xFF, 0 }, /* 13 DAI1 clock control */
287 { 0xFF, 0xFF, 0 }, /* 14 DAI1 format */
288 { 0xFF, 0xFF, 0 }, /* 15 DAI1 clock */
289 { 0xFF, 0xFF, 0 }, /* 16 DAI1 config */
290 { 0xFF, 0xFF, 0 }, /* 17 DAI1 TDM */
291 { 0xFF, 0xFF, 0 }, /* 18 DAI1 filters */
292 { 0xFF, 0xFF, 0 }, /* 19 DAI2 clock mode */
293 { 0xFF, 0xFF, 0 }, /* 1A DAI2 clock control */
294 { 0xFF, 0xFF, 0 }, /* 1B DAI2 clock control */
295 { 0xFF, 0xFF, 0 }, /* 1C DAI2 format */
296 { 0xFF, 0xFF, 0 }, /* 1D DAI2 clock */
297 { 0xFF, 0xFF, 0 }, /* 1E DAI2 config */
298 { 0xFF, 0xFF, 0 }, /* 1F DAI2 TDM */
299
300 { 0xFF, 0xFF, 0 }, /* 20 DAI2 filters */
301 { 0xFF, 0xFF, 0 }, /* 21 data config */
302 { 0xFF, 0xFF, 0 }, /* 22 DAC mixer */
303 { 0xFF, 0xFF, 0 }, /* 23 left ADC mixer */
304 { 0xFF, 0xFF, 0 }, /* 24 right ADC mixer */
305 { 0xFF, 0xFF, 0 }, /* 25 left HP mixer */
306 { 0xFF, 0xFF, 0 }, /* 26 right HP mixer */
307 { 0xFF, 0xFF, 0 }, /* 27 HP control */
308 { 0xFF, 0xFF, 0 }, /* 28 left REC mixer */
309 { 0xFF, 0xFF, 0 }, /* 29 right REC mixer */
310 { 0xFF, 0xFF, 0 }, /* 2A REC control */
311 { 0xFF, 0xFF, 0 }, /* 2B left SPK mixer */
312 { 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */
313 { 0xFF, 0xFF, 0 }, /* 2D SPK control */
314 { 0xFF, 0xFF, 0 }, /* 2E sidetone */
315 { 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */
316
317 { 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */
318 { 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */
319 { 0xFF, 0xFF, 0 }, /* 32 DAI2 playbakc level */
320 { 0xFF, 0xFF, 0 }, /* 33 left ADC level */
321 { 0xFF, 0xFF, 0 }, /* 34 right ADC level */
322 { 0xFF, 0xFF, 0 }, /* 35 MIC1 level */
323 { 0xFF, 0xFF, 0 }, /* 36 MIC2 level */
324 { 0xFF, 0xFF, 0 }, /* 37 INA level */
325 { 0xFF, 0xFF, 0 }, /* 38 INB level */
326 { 0xFF, 0xFF, 0 }, /* 39 left HP volume */
327 { 0xFF, 0xFF, 0 }, /* 3A right HP volume */
328 { 0xFF, 0xFF, 0 }, /* 3B left REC volume */
329 { 0xFF, 0xFF, 0 }, /* 3C right REC volume */
330 { 0xFF, 0xFF, 0 }, /* 3D left SPK volume */
331 { 0xFF, 0xFF, 0 }, /* 3E right SPK volume */
332 { 0xFF, 0xFF, 0 }, /* 3F MIC config */
333
334 { 0xFF, 0xFF, 0 }, /* 40 MIC threshold */
335 { 0xFF, 0xFF, 0 }, /* 41 excursion limiter filter */
336 { 0xFF, 0xFF, 0 }, /* 42 excursion limiter threshold */
337 { 0xFF, 0xFF, 0 }, /* 43 ALC */
338 { 0xFF, 0xFF, 0 }, /* 44 power limiter threshold */
339 { 0xFF, 0xFF, 0 }, /* 45 power limiter config */
340 { 0xFF, 0xFF, 0 }, /* 46 distortion limiter config */
341 { 0xFF, 0xFF, 0 }, /* 47 audio input */
342 { 0xFF, 0xFF, 0 }, /* 48 microphone */
343 { 0xFF, 0xFF, 0 }, /* 49 level control */
344 { 0xFF, 0xFF, 0 }, /* 4A bypass switches */
345 { 0xFF, 0xFF, 0 }, /* 4B jack detect */
346 { 0xFF, 0xFF, 0 }, /* 4C input enable */
347 { 0xFF, 0xFF, 0 }, /* 4D output enable */
348 { 0xFF, 0xFF, 0 }, /* 4E bias control */
349 { 0xFF, 0xFF, 0 }, /* 4F DAC power */
350
351 { 0xFF, 0xFF, 0 }, /* 50 DAC power */
352 { 0xFF, 0xFF, 0 }, /* 51 system */
353 { 0xFF, 0xFF, 0 }, /* 52 DAI1 EQ1 */
354 { 0xFF, 0xFF, 0 }, /* 53 DAI1 EQ1 */
355 { 0xFF, 0xFF, 0 }, /* 54 DAI1 EQ1 */
356 { 0xFF, 0xFF, 0 }, /* 55 DAI1 EQ1 */
357 { 0xFF, 0xFF, 0 }, /* 56 DAI1 EQ1 */
358 { 0xFF, 0xFF, 0 }, /* 57 DAI1 EQ1 */
359 { 0xFF, 0xFF, 0 }, /* 58 DAI1 EQ1 */
360 { 0xFF, 0xFF, 0 }, /* 59 DAI1 EQ1 */
361 { 0xFF, 0xFF, 0 }, /* 5A DAI1 EQ1 */
362 { 0xFF, 0xFF, 0 }, /* 5B DAI1 EQ1 */
363 { 0xFF, 0xFF, 0 }, /* 5C DAI1 EQ2 */
364 { 0xFF, 0xFF, 0 }, /* 5D DAI1 EQ2 */
365 { 0xFF, 0xFF, 0 }, /* 5E DAI1 EQ2 */
366 { 0xFF, 0xFF, 0 }, /* 5F DAI1 EQ2 */
367
368 { 0xFF, 0xFF, 0 }, /* 60 DAI1 EQ2 */
369 { 0xFF, 0xFF, 0 }, /* 61 DAI1 EQ2 */
370 { 0xFF, 0xFF, 0 }, /* 62 DAI1 EQ2 */
371 { 0xFF, 0xFF, 0 }, /* 63 DAI1 EQ2 */
372 { 0xFF, 0xFF, 0 }, /* 64 DAI1 EQ2 */
373 { 0xFF, 0xFF, 0 }, /* 65 DAI1 EQ2 */
374 { 0xFF, 0xFF, 0 }, /* 66 DAI1 EQ3 */
375 { 0xFF, 0xFF, 0 }, /* 67 DAI1 EQ3 */
376 { 0xFF, 0xFF, 0 }, /* 68 DAI1 EQ3 */
377 { 0xFF, 0xFF, 0 }, /* 69 DAI1 EQ3 */
378 { 0xFF, 0xFF, 0 }, /* 6A DAI1 EQ3 */
379 { 0xFF, 0xFF, 0 }, /* 6B DAI1 EQ3 */
380 { 0xFF, 0xFF, 0 }, /* 6C DAI1 EQ3 */
381 { 0xFF, 0xFF, 0 }, /* 6D DAI1 EQ3 */
382 { 0xFF, 0xFF, 0 }, /* 6E DAI1 EQ3 */
383 { 0xFF, 0xFF, 0 }, /* 6F DAI1 EQ3 */
384
385 { 0xFF, 0xFF, 0 }, /* 70 DAI1 EQ4 */
386 { 0xFF, 0xFF, 0 }, /* 71 DAI1 EQ4 */
387 { 0xFF, 0xFF, 0 }, /* 72 DAI1 EQ4 */
388 { 0xFF, 0xFF, 0 }, /* 73 DAI1 EQ4 */
389 { 0xFF, 0xFF, 0 }, /* 74 DAI1 EQ4 */
390 { 0xFF, 0xFF, 0 }, /* 75 DAI1 EQ4 */
391 { 0xFF, 0xFF, 0 }, /* 76 DAI1 EQ4 */
392 { 0xFF, 0xFF, 0 }, /* 77 DAI1 EQ4 */
393 { 0xFF, 0xFF, 0 }, /* 78 DAI1 EQ4 */
394 { 0xFF, 0xFF, 0 }, /* 79 DAI1 EQ4 */
395 { 0xFF, 0xFF, 0 }, /* 7A DAI1 EQ5 */
396 { 0xFF, 0xFF, 0 }, /* 7B DAI1 EQ5 */
397 { 0xFF, 0xFF, 0 }, /* 7C DAI1 EQ5 */
398 { 0xFF, 0xFF, 0 }, /* 7D DAI1 EQ5 */
399 { 0xFF, 0xFF, 0 }, /* 7E DAI1 EQ5 */
400 { 0xFF, 0xFF, 0 }, /* 7F DAI1 EQ5 */
401
402 { 0xFF, 0xFF, 0 }, /* 80 DAI1 EQ5 */
403 { 0xFF, 0xFF, 0 }, /* 81 DAI1 EQ5 */
404 { 0xFF, 0xFF, 0 }, /* 82 DAI1 EQ5 */
405 { 0xFF, 0xFF, 0 }, /* 83 DAI1 EQ5 */
406 { 0xFF, 0xFF, 0 }, /* 84 DAI2 EQ1 */
407 { 0xFF, 0xFF, 0 }, /* 85 DAI2 EQ1 */
408 { 0xFF, 0xFF, 0 }, /* 86 DAI2 EQ1 */
409 { 0xFF, 0xFF, 0 }, /* 87 DAI2 EQ1 */
410 { 0xFF, 0xFF, 0 }, /* 88 DAI2 EQ1 */
411 { 0xFF, 0xFF, 0 }, /* 89 DAI2 EQ1 */
412 { 0xFF, 0xFF, 0 }, /* 8A DAI2 EQ1 */
413 { 0xFF, 0xFF, 0 }, /* 8B DAI2 EQ1 */
414 { 0xFF, 0xFF, 0 }, /* 8C DAI2 EQ1 */
415 { 0xFF, 0xFF, 0 }, /* 8D DAI2 EQ1 */
416 { 0xFF, 0xFF, 0 }, /* 8E DAI2 EQ2 */
417 { 0xFF, 0xFF, 0 }, /* 8F DAI2 EQ2 */
418
419 { 0xFF, 0xFF, 0 }, /* 90 DAI2 EQ2 */
420 { 0xFF, 0xFF, 0 }, /* 91 DAI2 EQ2 */
421 { 0xFF, 0xFF, 0 }, /* 92 DAI2 EQ2 */
422 { 0xFF, 0xFF, 0 }, /* 93 DAI2 EQ2 */
423 { 0xFF, 0xFF, 0 }, /* 94 DAI2 EQ2 */
424 { 0xFF, 0xFF, 0 }, /* 95 DAI2 EQ2 */
425 { 0xFF, 0xFF, 0 }, /* 96 DAI2 EQ2 */
426 { 0xFF, 0xFF, 0 }, /* 97 DAI2 EQ2 */
427 { 0xFF, 0xFF, 0 }, /* 98 DAI2 EQ3 */
428 { 0xFF, 0xFF, 0 }, /* 99 DAI2 EQ3 */
429 { 0xFF, 0xFF, 0 }, /* 9A DAI2 EQ3 */
430 { 0xFF, 0xFF, 0 }, /* 9B DAI2 EQ3 */
431 { 0xFF, 0xFF, 0 }, /* 9C DAI2 EQ3 */
432 { 0xFF, 0xFF, 0 }, /* 9D DAI2 EQ3 */
433 { 0xFF, 0xFF, 0 }, /* 9E DAI2 EQ3 */
434 { 0xFF, 0xFF, 0 }, /* 9F DAI2 EQ3 */
435
436 { 0xFF, 0xFF, 0 }, /* A0 DAI2 EQ3 */
437 { 0xFF, 0xFF, 0 }, /* A1 DAI2 EQ3 */
438 { 0xFF, 0xFF, 0 }, /* A2 DAI2 EQ4 */
439 { 0xFF, 0xFF, 0 }, /* A3 DAI2 EQ4 */
440 { 0xFF, 0xFF, 0 }, /* A4 DAI2 EQ4 */
441 { 0xFF, 0xFF, 0 }, /* A5 DAI2 EQ4 */
442 { 0xFF, 0xFF, 0 }, /* A6 DAI2 EQ4 */
443 { 0xFF, 0xFF, 0 }, /* A7 DAI2 EQ4 */
444 { 0xFF, 0xFF, 0 }, /* A8 DAI2 EQ4 */
445 { 0xFF, 0xFF, 0 }, /* A9 DAI2 EQ4 */
446 { 0xFF, 0xFF, 0 }, /* AA DAI2 EQ4 */
447 { 0xFF, 0xFF, 0 }, /* AB DAI2 EQ4 */
448 { 0xFF, 0xFF, 0 }, /* AC DAI2 EQ5 */
449 { 0xFF, 0xFF, 0 }, /* AD DAI2 EQ5 */
450 { 0xFF, 0xFF, 0 }, /* AE DAI2 EQ5 */
451 { 0xFF, 0xFF, 0 }, /* AF DAI2 EQ5 */
452
453 { 0xFF, 0xFF, 0 }, /* B0 DAI2 EQ5 */
454 { 0xFF, 0xFF, 0 }, /* B1 DAI2 EQ5 */
455 { 0xFF, 0xFF, 0 }, /* B2 DAI2 EQ5 */
456 { 0xFF, 0xFF, 0 }, /* B3 DAI2 EQ5 */
457 { 0xFF, 0xFF, 0 }, /* B4 DAI2 EQ5 */
458 { 0xFF, 0xFF, 0 }, /* B5 DAI2 EQ5 */
459 { 0xFF, 0xFF, 0 }, /* B6 DAI1 biquad */
460 { 0xFF, 0xFF, 0 }, /* B7 DAI1 biquad */
461 { 0xFF, 0xFF, 0 }, /* B8 DAI1 biquad */
462 { 0xFF, 0xFF, 0 }, /* B9 DAI1 biquad */
463 { 0xFF, 0xFF, 0 }, /* BA DAI1 biquad */
464 { 0xFF, 0xFF, 0 }, /* BB DAI1 biquad */
465 { 0xFF, 0xFF, 0 }, /* BC DAI1 biquad */
466 { 0xFF, 0xFF, 0 }, /* BD DAI1 biquad */
467 { 0xFF, 0xFF, 0 }, /* BE DAI1 biquad */
468 { 0xFF, 0xFF, 0 }, /* BF DAI1 biquad */
469
470 { 0xFF, 0xFF, 0 }, /* C0 DAI2 biquad */
471 { 0xFF, 0xFF, 0 }, /* C1 DAI2 biquad */
472 { 0xFF, 0xFF, 0 }, /* C2 DAI2 biquad */
473 { 0xFF, 0xFF, 0 }, /* C3 DAI2 biquad */
474 { 0xFF, 0xFF, 0 }, /* C4 DAI2 biquad */
475 { 0xFF, 0xFF, 0 }, /* C5 DAI2 biquad */
476 { 0xFF, 0xFF, 0 }, /* C6 DAI2 biquad */
477 { 0xFF, 0xFF, 0 }, /* C7 DAI2 biquad */
478 { 0xFF, 0xFF, 0 }, /* C8 DAI2 biquad */
479 { 0xFF, 0xFF, 0 }, /* C9 DAI2 biquad */
480 { 0x00, 0x00, 0 }, /* CA */
481 { 0x00, 0x00, 0 }, /* CB */
482 { 0x00, 0x00, 0 }, /* CC */
483 { 0x00, 0x00, 0 }, /* CD */
484 { 0x00, 0x00, 0 }, /* CE */
485 { 0x00, 0x00, 0 }, /* CF */
486
487 { 0x00, 0x00, 0 }, /* D0 */
488 { 0x00, 0x00, 0 }, /* D1 */
489 { 0x00, 0x00, 0 }, /* D2 */
490 { 0x00, 0x00, 0 }, /* D3 */
491 { 0x00, 0x00, 0 }, /* D4 */
492 { 0x00, 0x00, 0 }, /* D5 */
493 { 0x00, 0x00, 0 }, /* D6 */
494 { 0x00, 0x00, 0 }, /* D7 */
495 { 0x00, 0x00, 0 }, /* D8 */
496 { 0x00, 0x00, 0 }, /* D9 */
497 { 0x00, 0x00, 0 }, /* DA */
498 { 0x00, 0x00, 0 }, /* DB */
499 { 0x00, 0x00, 0 }, /* DC */
500 { 0x00, 0x00, 0 }, /* DD */
501 { 0x00, 0x00, 0 }, /* DE */
502 { 0x00, 0x00, 0 }, /* DF */
503
504 { 0x00, 0x00, 0 }, /* E0 */
505 { 0x00, 0x00, 0 }, /* E1 */
506 { 0x00, 0x00, 0 }, /* E2 */
507 { 0x00, 0x00, 0 }, /* E3 */
508 { 0x00, 0x00, 0 }, /* E4 */
509 { 0x00, 0x00, 0 }, /* E5 */
510 { 0x00, 0x00, 0 }, /* E6 */
511 { 0x00, 0x00, 0 }, /* E7 */
512 { 0x00, 0x00, 0 }, /* E8 */
513 { 0x00, 0x00, 0 }, /* E9 */
514 { 0x00, 0x00, 0 }, /* EA */
515 { 0x00, 0x00, 0 }, /* EB */
516 { 0x00, 0x00, 0 }, /* EC */
517 { 0x00, 0x00, 0 }, /* ED */
518 { 0x00, 0x00, 0 }, /* EE */
519 { 0x00, 0x00, 0 }, /* EF */
520
521 { 0x00, 0x00, 0 }, /* F0 */
522 { 0x00, 0x00, 0 }, /* F1 */
523 { 0x00, 0x00, 0 }, /* F2 */
524 { 0x00, 0x00, 0 }, /* F3 */
525 { 0x00, 0x00, 0 }, /* F4 */
526 { 0x00, 0x00, 0 }, /* F5 */
527 { 0x00, 0x00, 0 }, /* F6 */
528 { 0x00, 0x00, 0 }, /* F7 */
529 { 0x00, 0x00, 0 }, /* F8 */
530 { 0x00, 0x00, 0 }, /* F9 */
531 { 0x00, 0x00, 0 }, /* FA */
532 { 0x00, 0x00, 0 }, /* FB */
533 { 0x00, 0x00, 0 }, /* FC */
534 { 0x00, 0x00, 0 }, /* FD */
535 { 0x00, 0x00, 0 }, /* FE */
536 { 0xFF, 0x00, 1 }, /* FF */
537};
538
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]539static bool max98088_readable_register(struct device *dev, unsigned int reg)
540{
541 return max98088_access[reg].readable;
542}
543
544static bool max98088_volatile_register(struct device *dev, unsigned int reg)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]545{
546 return max98088_access[reg].vol;
547}
548
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]549static const struct regmap_config max98088_regmap = {
550 .reg_bits = 8,
551 .val_bits = 8,
552
553 .readable_reg = max98088_readable_register,
554 .volatile_reg = max98088_volatile_register,
555
556 .reg_defaults = max98088_reg,
557 .num_reg_defaults = ARRAY_SIZE(max98088_reg),
558 .cache_type = REGCACHE_RBTREE,
559};
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]560
561/*
562 * Load equalizer DSP coefficient configurations registers
563 */
Dimitris Papastamos4428bc02010-10-21 12:15:56 +0100[diff] [blame]564static void m98088_eq_band(struct snd_soc_codec *codec, unsigned int dai,
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]565 unsigned int band, u16 *coefs)
566{
567 unsigned int eq_reg;
568 unsigned int i;
569
570 BUG_ON(band > 4);
571 BUG_ON(dai > 1);
572
573 /* Load the base register address */
574 eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE;
575
576 /* Add the band address offset, note adjustment for word address */
577 eq_reg += band * (M98088_COEFS_PER_BAND << 1);
578
579 /* Step through the registers and coefs */
580 for (i = 0; i < M98088_COEFS_PER_BAND; i++) {
581 snd_soc_write(codec, eq_reg++, M98088_BYTE1(coefs[i]));
582 snd_soc_write(codec, eq_reg++, M98088_BYTE0(coefs[i]));
583 }
584}
585
586/*
587 * Excursion limiter modes
588 */
589static const char *max98088_exmode_texts[] = {
590 "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz",
591 "400-600Hz", "400-800Hz",
592};
593
594static const unsigned int max98088_exmode_values[] = {
595 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32
596};
597
598static const struct soc_enum max98088_exmode_enum =
599 SOC_VALUE_ENUM_SINGLE(M98088_REG_41_SPKDHP, 0, 127,
600 ARRAY_SIZE(max98088_exmode_texts),
601 max98088_exmode_texts,
602 max98088_exmode_values);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]603
604static const char *max98088_ex_thresh[] = { /* volts PP */
605 "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"};
606static const struct soc_enum max98088_ex_thresh_enum[] = {
607 SOC_ENUM_SINGLE(M98088_REG_42_SPKDHP_THRESH, 0, 8,
608 max98088_ex_thresh),
609};
610
611static const char *max98088_fltr_mode[] = {"Voice", "Music" };
612static const struct soc_enum max98088_filter_mode_enum[] = {
613 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 7, 2, max98088_fltr_mode),
614};
615
616static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" };
617
618static const struct soc_enum max98088_extmic_enum =
619 SOC_ENUM_SINGLE(M98088_REG_48_CFG_MIC, 0, 3, max98088_extmic_text);
620
621static const struct snd_kcontrol_new max98088_extmic_mux =
622 SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum);
623
624static const char *max98088_dai1_fltr[] = {
625 "Off", "fc=258/fs=16k", "fc=500/fs=16k",
626 "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"};
627static const struct soc_enum max98088_dai1_dac_filter_enum[] = {
628 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 0, 6, max98088_dai1_fltr),
629};
630static const struct soc_enum max98088_dai1_adc_filter_enum[] = {
631 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 4, 6, max98088_dai1_fltr),
632};
633
634static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
635 struct snd_ctl_elem_value *ucontrol)
636{
637 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
638 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
639 unsigned int sel = ucontrol->value.integer.value[0];
640
641 max98088->mic1pre = sel;
642 snd_soc_update_bits(codec, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK,
643 (1+sel)<<M98088_MICPRE_SHIFT);
644
645 return 0;
646}
647
648static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
649 struct snd_ctl_elem_value *ucontrol)
650{
651 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
652 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
653
654 ucontrol->value.integer.value[0] = max98088->mic1pre;
655 return 0;
656}
657
658static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
659 struct snd_ctl_elem_value *ucontrol)
660{
661 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
662 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
663 unsigned int sel = ucontrol->value.integer.value[0];
664
665 max98088->mic2pre = sel;
666 snd_soc_update_bits(codec, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK,
667 (1+sel)<<M98088_MICPRE_SHIFT);
668
669 return 0;
670}
671
672static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol,
673 struct snd_ctl_elem_value *ucontrol)
674{
675 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
676 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
677
678 ucontrol->value.integer.value[0] = max98088->mic2pre;
679 return 0;
680}
681
682static const unsigned int max98088_micboost_tlv[] = {
683 TLV_DB_RANGE_HEAD(2),
684 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
685 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
686};
687
Dylan Reidc751a1f2013-02-15 08:55:10 -0800[diff] [blame]688static const unsigned int max98088_hp_tlv[] = {
689 TLV_DB_RANGE_HEAD(5),
690 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
691 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
692 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
693 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
694 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
695};
696
697static const unsigned int max98088_spk_tlv[] = {
698 TLV_DB_RANGE_HEAD(5),
699 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
700 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
701 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
702 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
703 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
704};
705
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]706static const struct snd_kcontrol_new max98088_snd_controls[] = {
707
Dylan Reidc751a1f2013-02-15 08:55:10 -0800[diff] [blame]708 SOC_DOUBLE_R_TLV("Headphone Volume", M98088_REG_39_LVL_HP_L,
709 M98088_REG_3A_LVL_HP_R, 0, 31, 0, max98088_hp_tlv),
710 SOC_DOUBLE_R_TLV("Speaker Volume", M98088_REG_3D_LVL_SPK_L,
711 M98088_REG_3E_LVL_SPK_R, 0, 31, 0, max98088_spk_tlv),
712 SOC_DOUBLE_R_TLV("Receiver Volume", M98088_REG_3B_LVL_REC_L,
713 M98088_REG_3C_LVL_REC_R, 0, 31, 0, max98088_spk_tlv),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]714
715 SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L,
716 M98088_REG_3A_LVL_HP_R, 7, 1, 1),
717 SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L,
718 M98088_REG_3E_LVL_SPK_R, 7, 1, 1),
719 SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L,
720 M98088_REG_3C_LVL_REC_R, 7, 1, 1),
721
722 SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1),
723 SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1),
724
725 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
726 M98088_REG_35_LVL_MIC1, 5, 2, 0,
727 max98088_mic1pre_get, max98088_mic1pre_set,
728 max98088_micboost_tlv),
729 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
730 M98088_REG_36_LVL_MIC2, 5, 2, 0,
731 max98088_mic2pre_get, max98088_mic2pre_set,
732 max98088_micboost_tlv),
733
734 SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1),
735 SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1),
736
737 SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0),
738 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0),
739
740 SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0),
741 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0),
742
743 SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0),
744 SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0),
745
Jin Park938b4fb2011-05-12 14:58:37 +0900[diff] [blame]746 SOC_ENUM("EX Limiter Mode", max98088_exmode_enum),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]747 SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum),
748
749 SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum),
750 SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum),
751 SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum),
752 SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS,
753 0, 1, 0),
754
755 SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0),
756 SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0),
757 SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0),
758 SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0),
759
760 SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG,
761 4, 15, 0),
762 SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0),
763 SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0),
764 SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0),
765
766 SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0),
767 SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0),
768};
769
770/* Left speaker mixer switch */
771static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = {
Jin Park770939c2011-05-12 14:58:36 +0900[diff] [blame]772 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
773 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
774 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
775 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]776 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0),
777 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0),
778 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0),
779 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0),
780 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0),
781 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0),
782};
783
784/* Right speaker mixer switch */
785static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = {
786 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
787 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
788 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
789 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
790 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0),
791 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0),
792 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0),
793 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0),
794 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0),
795 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0),
796};
797
798/* Left headphone mixer switch */
799static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = {
Jin Park770939c2011-05-12 14:58:36 +0900[diff] [blame]800 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
801 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
802 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
803 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]804 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0),
805 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0),
806 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0),
807 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0),
808 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0),
809 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0),
810};
811
812/* Right headphone mixer switch */
813static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = {
814 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
815 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
816 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
817 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
818 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0),
819 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0),
820 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0),
821 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0),
822 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0),
823 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0),
824};
825
826/* Left earpiece/receiver mixer switch */
827static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = {
Jin Park770939c2011-05-12 14:58:36 +0900[diff] [blame]828 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
829 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
830 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
831 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]832 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0),
833 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0),
834 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0),
835 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0),
836 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0),
837 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0),
838};
839
840/* Right earpiece/receiver mixer switch */
841static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = {
842 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
843 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
844 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
845 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
846 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0),
847 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0),
848 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0),
849 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0),
850 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0),
851 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0),
852};
853
854/* Left ADC mixer switch */
855static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = {
856 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0),
857 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0),
858 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0),
859 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0),
860 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0),
861 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0),
862};
863
864/* Right ADC mixer switch */
865static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = {
866 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0),
867 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0),
868 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0),
869 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0),
870 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0),
871 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0),
872};
873
874static int max98088_mic_event(struct snd_soc_dapm_widget *w,
875 struct snd_kcontrol *kcontrol, int event)
876{
877 struct snd_soc_codec *codec = w->codec;
878 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
879
880 switch (event) {
881 case SND_SOC_DAPM_POST_PMU:
882 if (w->reg == M98088_REG_35_LVL_MIC1) {
883 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
884 (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT);
885 } else {
886 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
887 (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT);
888 }
889 break;
890 case SND_SOC_DAPM_POST_PMD:
891 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 0);
892 break;
893 default:
894 return -EINVAL;
895 }
896
897 return 0;
898}
899
900/*
901 * The line inputs are 2-channel stereo inputs with the left
902 * and right channels sharing a common PGA power control signal.
903 */
904static int max98088_line_pga(struct snd_soc_dapm_widget *w,
905 int event, int line, u8 channel)
906{
907 struct snd_soc_codec *codec = w->codec;
908 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
909 u8 *state;
910
911 BUG_ON(!((channel == 1) || (channel == 2)));
912
913 switch (line) {
914 case LINE_INA:
915 state = &max98088->ina_state;
916 break;
917 case LINE_INB:
918 state = &max98088->inb_state;
919 break;
920 default:
921 return -EINVAL;
922 }
923
924 switch (event) {
925 case SND_SOC_DAPM_POST_PMU:
926 *state |= channel;
927 snd_soc_update_bits(codec, w->reg,
928 (1 << w->shift), (1 << w->shift));
929 break;
930 case SND_SOC_DAPM_POST_PMD:
931 *state &= ~channel;
932 if (*state == 0) {
933 snd_soc_update_bits(codec, w->reg,
934 (1 << w->shift), 0);
935 }
936 break;
937 default:
938 return -EINVAL;
939 }
940
941 return 0;
942}
943
944static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w,
945 struct snd_kcontrol *k, int event)
946{
947 return max98088_line_pga(w, event, LINE_INA, 1);
948}
949
950static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w,
951 struct snd_kcontrol *k, int event)
952{
953 return max98088_line_pga(w, event, LINE_INA, 2);
954}
955
956static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w,
957 struct snd_kcontrol *k, int event)
958{
959 return max98088_line_pga(w, event, LINE_INB, 1);
960}
961
962static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w,
963 struct snd_kcontrol *k, int event)
964{
965 return max98088_line_pga(w, event, LINE_INB, 2);
966}
967
968static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = {
969
970 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0),
971 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0),
972
973 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
974 M98088_REG_4D_PWR_EN_OUT, 1, 0),
975 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
976 M98088_REG_4D_PWR_EN_OUT, 0, 0),
977 SND_SOC_DAPM_DAC("DACL2", "Aux Playback",
978 M98088_REG_4D_PWR_EN_OUT, 1, 0),
979 SND_SOC_DAPM_DAC("DACR2", "Aux Playback",
980 M98088_REG_4D_PWR_EN_OUT, 0, 0),
981
982 SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT,
983 7, 0, NULL, 0),
984 SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT,
985 6, 0, NULL, 0),
986
987 SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT,
988 5, 0, NULL, 0),
989 SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT,
990 4, 0, NULL, 0),
991
992 SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT,
993 3, 0, NULL, 0),
994 SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT,
995 2, 0, NULL, 0),
996
997 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
998 &max98088_extmic_mux),
999
1000 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
1001 &max98088_left_hp_mixer_controls[0],
1002 ARRAY_SIZE(max98088_left_hp_mixer_controls)),
1003
1004 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
1005 &max98088_right_hp_mixer_controls[0],
1006 ARRAY_SIZE(max98088_right_hp_mixer_controls)),
1007
1008 SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0,
1009 &max98088_left_speaker_mixer_controls[0],
1010 ARRAY_SIZE(max98088_left_speaker_mixer_controls)),
1011
1012 SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0,
1013 &max98088_right_speaker_mixer_controls[0],
1014 ARRAY_SIZE(max98088_right_speaker_mixer_controls)),
1015
1016 SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0,
1017 &max98088_left_rec_mixer_controls[0],
1018 ARRAY_SIZE(max98088_left_rec_mixer_controls)),
1019
1020 SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0,
1021 &max98088_right_rec_mixer_controls[0],
1022 ARRAY_SIZE(max98088_right_rec_mixer_controls)),
1023
1024 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1025 &max98088_left_ADC_mixer_controls[0],
1026 ARRAY_SIZE(max98088_left_ADC_mixer_controls)),
1027
1028 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1029 &max98088_right_ADC_mixer_controls[0],
1030 ARRAY_SIZE(max98088_right_ADC_mixer_controls)),
1031
1032 SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1,
1033 5, 0, NULL, 0, max98088_mic_event,
1034 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1035
1036 SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2,
1037 5, 0, NULL, 0, max98088_mic_event,
1038 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1039
1040 SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN,
1041 7, 0, NULL, 0, max98088_pga_ina1_event,
1042 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1043
1044 SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN,
1045 7, 0, NULL, 0, max98088_pga_ina2_event,
1046 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1047
1048 SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN,
1049 6, 0, NULL, 0, max98088_pga_inb1_event,
1050 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1051
1052 SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN,
1053 6, 0, NULL, 0, max98088_pga_inb2_event,
1054 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1055
1056 SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0),
1057
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1058 SND_SOC_DAPM_OUTPUT("HPL"),
1059 SND_SOC_DAPM_OUTPUT("HPR"),
1060 SND_SOC_DAPM_OUTPUT("SPKL"),
1061 SND_SOC_DAPM_OUTPUT("SPKR"),
1062 SND_SOC_DAPM_OUTPUT("RECL"),
1063 SND_SOC_DAPM_OUTPUT("RECR"),
1064
1065 SND_SOC_DAPM_INPUT("MIC1"),
1066 SND_SOC_DAPM_INPUT("MIC2"),
1067 SND_SOC_DAPM_INPUT("INA1"),
1068 SND_SOC_DAPM_INPUT("INA2"),
1069 SND_SOC_DAPM_INPUT("INB1"),
1070 SND_SOC_DAPM_INPUT("INB2"),
1071};
1072
Lu Guanqundc6fc492011-03-30 21:53:10 +0800[diff] [blame]1073static const struct snd_soc_dapm_route max98088_audio_map[] = {
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1074 /* Left headphone output mixer */
1075 {"Left HP Mixer", "Left DAC1 Switch", "DACL1"},
1076 {"Left HP Mixer", "Left DAC2 Switch", "DACL2"},
1077 {"Left HP Mixer", "Right DAC1 Switch", "DACR1"},
1078 {"Left HP Mixer", "Right DAC2 Switch", "DACR2"},
1079 {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"},
1080 {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"},
1081 {"Left HP Mixer", "INA1 Switch", "INA1 Input"},
1082 {"Left HP Mixer", "INA2 Switch", "INA2 Input"},
1083 {"Left HP Mixer", "INB1 Switch", "INB1 Input"},
1084 {"Left HP Mixer", "INB2 Switch", "INB2 Input"},
1085
1086 /* Right headphone output mixer */
1087 {"Right HP Mixer", "Left DAC1 Switch", "DACL1"},
1088 {"Right HP Mixer", "Left DAC2 Switch", "DACL2" },
1089 {"Right HP Mixer", "Right DAC1 Switch", "DACR1"},
1090 {"Right HP Mixer", "Right DAC2 Switch", "DACR2"},
1091 {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"},
1092 {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"},
1093 {"Right HP Mixer", "INA1 Switch", "INA1 Input"},
1094 {"Right HP Mixer", "INA2 Switch", "INA2 Input"},
1095 {"Right HP Mixer", "INB1 Switch", "INB1 Input"},
1096 {"Right HP Mixer", "INB2 Switch", "INB2 Input"},
1097
1098 /* Left speaker output mixer */
1099 {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"},
1100 {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"},
1101 {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"},
1102 {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"},
1103 {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"},
1104 {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"},
1105 {"Left SPK Mixer", "INA1 Switch", "INA1 Input"},
1106 {"Left SPK Mixer", "INA2 Switch", "INA2 Input"},
1107 {"Left SPK Mixer", "INB1 Switch", "INB1 Input"},
1108 {"Left SPK Mixer", "INB2 Switch", "INB2 Input"},
1109
1110 /* Right speaker output mixer */
1111 {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"},
1112 {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"},
1113 {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"},
1114 {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"},
1115 {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"},
1116 {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"},
1117 {"Right SPK Mixer", "INA1 Switch", "INA1 Input"},
1118 {"Right SPK Mixer", "INA2 Switch", "INA2 Input"},
1119 {"Right SPK Mixer", "INB1 Switch", "INB1 Input"},
1120 {"Right SPK Mixer", "INB2 Switch", "INB2 Input"},
1121
1122 /* Earpiece/Receiver output mixer */
1123 {"Left REC Mixer", "Left DAC1 Switch", "DACL1"},
1124 {"Left REC Mixer", "Left DAC2 Switch", "DACL2"},
1125 {"Left REC Mixer", "Right DAC1 Switch", "DACR1"},
1126 {"Left REC Mixer", "Right DAC2 Switch", "DACR2"},
1127 {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"},
1128 {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"},
1129 {"Left REC Mixer", "INA1 Switch", "INA1 Input"},
1130 {"Left REC Mixer", "INA2 Switch", "INA2 Input"},
1131 {"Left REC Mixer", "INB1 Switch", "INB1 Input"},
1132 {"Left REC Mixer", "INB2 Switch", "INB2 Input"},
1133
1134 /* Earpiece/Receiver output mixer */
1135 {"Right REC Mixer", "Left DAC1 Switch", "DACL1"},
1136 {"Right REC Mixer", "Left DAC2 Switch", "DACL2"},
1137 {"Right REC Mixer", "Right DAC1 Switch", "DACR1"},
1138 {"Right REC Mixer", "Right DAC2 Switch", "DACR2"},
1139 {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"},
1140 {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"},
1141 {"Right REC Mixer", "INA1 Switch", "INA1 Input"},
1142 {"Right REC Mixer", "INA2 Switch", "INA2 Input"},
1143 {"Right REC Mixer", "INB1 Switch", "INB1 Input"},
1144 {"Right REC Mixer", "INB2 Switch", "INB2 Input"},
1145
1146 {"HP Left Out", NULL, "Left HP Mixer"},
1147 {"HP Right Out", NULL, "Right HP Mixer"},
1148 {"SPK Left Out", NULL, "Left SPK Mixer"},
1149 {"SPK Right Out", NULL, "Right SPK Mixer"},
1150 {"REC Left Out", NULL, "Left REC Mixer"},
1151 {"REC Right Out", NULL, "Right REC Mixer"},
1152
1153 {"HPL", NULL, "HP Left Out"},
1154 {"HPR", NULL, "HP Right Out"},
1155 {"SPKL", NULL, "SPK Left Out"},
1156 {"SPKR", NULL, "SPK Right Out"},
1157 {"RECL", NULL, "REC Left Out"},
1158 {"RECR", NULL, "REC Right Out"},
1159
1160 /* Left ADC input mixer */
1161 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1162 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1163 {"Left ADC Mixer", "INA1 Switch", "INA1 Input"},
1164 {"Left ADC Mixer", "INA2 Switch", "INA2 Input"},
1165 {"Left ADC Mixer", "INB1 Switch", "INB1 Input"},
1166 {"Left ADC Mixer", "INB2 Switch", "INB2 Input"},
1167
1168 /* Right ADC input mixer */
1169 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1170 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1171 {"Right ADC Mixer", "INA1 Switch", "INA1 Input"},
1172 {"Right ADC Mixer", "INA2 Switch", "INA2 Input"},
1173 {"Right ADC Mixer", "INB1 Switch", "INB1 Input"},
1174 {"Right ADC Mixer", "INB2 Switch", "INB2 Input"},
1175
1176 /* Inputs */
1177 {"ADCL", NULL, "Left ADC Mixer"},
1178 {"ADCR", NULL, "Right ADC Mixer"},
1179 {"INA1 Input", NULL, "INA1"},
1180 {"INA2 Input", NULL, "INA2"},
1181 {"INB1 Input", NULL, "INB1"},
1182 {"INB2 Input", NULL, "INB2"},
1183 {"MIC1 Input", NULL, "MIC1"},
1184 {"MIC2 Input", NULL, "MIC2"},
1185};
1186
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1187/* codec mclk clock divider coefficients */
1188static const struct {
1189 u32 rate;
1190 u8 sr;
1191} rate_table[] = {
1192 {8000, 0x10},
1193 {11025, 0x20},
1194 {16000, 0x30},
1195 {22050, 0x40},
1196 {24000, 0x50},
1197 {32000, 0x60},
1198 {44100, 0x70},
1199 {48000, 0x80},
1200 {88200, 0x90},
1201 {96000, 0xA0},
1202};
1203
1204static inline int rate_value(int rate, u8 *value)
1205{
1206 int i;
1207
1208 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
1209 if (rate_table[i].rate >= rate) {
1210 *value = rate_table[i].sr;
1211 return 0;
1212 }
1213 }
1214 *value = rate_table[0].sr;
1215 return -EINVAL;
1216}
1217
1218static int max98088_dai1_hw_params(struct snd_pcm_substream *substream,
1219 struct snd_pcm_hw_params *params,
1220 struct snd_soc_dai *dai)
1221{
1222 struct snd_soc_codec *codec = dai->codec;
1223 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1224 struct max98088_cdata *cdata;
1225 unsigned long long ni;
1226 unsigned int rate;
1227 u8 regval;
1228
1229 cdata = &max98088->dai[0];
1230
1231 rate = params_rate(params);
1232
1233 switch (params_format(params)) {
1234 case SNDRV_PCM_FORMAT_S16_LE:
1235 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1236 M98088_DAI_WS, 0);
1237 break;
1238 case SNDRV_PCM_FORMAT_S24_LE:
1239 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1240 M98088_DAI_WS, M98088_DAI_WS);
1241 break;
1242 default:
1243 return -EINVAL;
1244 }
1245
1246 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1247
1248 if (rate_value(rate, &regval))
1249 return -EINVAL;
1250
1251 snd_soc_update_bits(codec, M98088_REG_11_DAI1_CLKMODE,
1252 M98088_CLKMODE_MASK, regval);
1253 cdata->rate = rate;
1254
1255 /* Configure NI when operating as master */
1256 if (snd_soc_read(codec, M98088_REG_14_DAI1_FORMAT)
1257 & M98088_DAI_MAS) {
1258 if (max98088->sysclk == 0) {
1259 dev_err(codec->dev, "Invalid system clock frequency\n");
1260 return -EINVAL;
1261 }
1262 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1263 * (unsigned long long int)rate;
1264 do_div(ni, (unsigned long long int)max98088->sysclk);
1265 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
1266 (ni >> 8) & 0x7F);
1267 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
1268 ni & 0xFF);
1269 }
1270
1271 /* Update sample rate mode */
1272 if (rate < 50000)
1273 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
1274 M98088_DAI_DHF, 0);
1275 else
1276 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
1277 M98088_DAI_DHF, M98088_DAI_DHF);
1278
1279 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1280 M98088_SHDNRUN);
1281
1282 return 0;
1283}
1284
1285static int max98088_dai2_hw_params(struct snd_pcm_substream *substream,
1286 struct snd_pcm_hw_params *params,
1287 struct snd_soc_dai *dai)
1288{
1289 struct snd_soc_codec *codec = dai->codec;
1290 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1291 struct max98088_cdata *cdata;
1292 unsigned long long ni;
1293 unsigned int rate;
1294 u8 regval;
1295
1296 cdata = &max98088->dai[1];
1297
1298 rate = params_rate(params);
1299
1300 switch (params_format(params)) {
1301 case SNDRV_PCM_FORMAT_S16_LE:
1302 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1303 M98088_DAI_WS, 0);
1304 break;
1305 case SNDRV_PCM_FORMAT_S24_LE:
1306 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1307 M98088_DAI_WS, M98088_DAI_WS);
1308 break;
1309 default:
1310 return -EINVAL;
1311 }
1312
1313 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1314
1315 if (rate_value(rate, &regval))
1316 return -EINVAL;
1317
1318 snd_soc_update_bits(codec, M98088_REG_19_DAI2_CLKMODE,
1319 M98088_CLKMODE_MASK, regval);
1320 cdata->rate = rate;
1321
1322 /* Configure NI when operating as master */
1323 if (snd_soc_read(codec, M98088_REG_1C_DAI2_FORMAT)
1324 & M98088_DAI_MAS) {
1325 if (max98088->sysclk == 0) {
1326 dev_err(codec->dev, "Invalid system clock frequency\n");
1327 return -EINVAL;
1328 }
1329 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1330 * (unsigned long long int)rate;
1331 do_div(ni, (unsigned long long int)max98088->sysclk);
1332 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
1333 (ni >> 8) & 0x7F);
1334 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
1335 ni & 0xFF);
1336 }
1337
1338 /* Update sample rate mode */
1339 if (rate < 50000)
1340 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
1341 M98088_DAI_DHF, 0);
1342 else
1343 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
1344 M98088_DAI_DHF, M98088_DAI_DHF);
1345
1346 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1347 M98088_SHDNRUN);
1348
1349 return 0;
1350}
1351
1352static int max98088_dai_set_sysclk(struct snd_soc_dai *dai,
1353 int clk_id, unsigned int freq, int dir)
1354{
1355 struct snd_soc_codec *codec = dai->codec;
1356 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1357
1358 /* Requested clock frequency is already setup */
1359 if (freq == max98088->sysclk)
1360 return 0;
1361
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1362 /* Setup clocks for slave mode, and using the PLL
1363 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1364 * 0x02 (when master clk is 20MHz to 30MHz)..
1365 */
1366 if ((freq >= 10000000) && (freq < 20000000)) {
1367 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x10);
1368 } else if ((freq >= 20000000) && (freq < 30000000)) {
1369 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x20);
1370 } else {
1371 dev_err(codec->dev, "Invalid master clock frequency\n");
1372 return -EINVAL;
1373 }
1374
1375 if (snd_soc_read(codec, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) {
1376 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
1377 M98088_SHDNRUN, 0);
1378 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
1379 M98088_SHDNRUN, M98088_SHDNRUN);
1380 }
1381
1382 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1383
1384 max98088->sysclk = freq;
1385 return 0;
1386}
1387
1388static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1389 unsigned int fmt)
1390{
1391 struct snd_soc_codec *codec = codec_dai->codec;
1392 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1393 struct max98088_cdata *cdata;
1394 u8 reg15val;
1395 u8 reg14val = 0;
1396
1397 cdata = &max98088->dai[0];
1398
1399 if (fmt != cdata->fmt) {
1400 cdata->fmt = fmt;
1401
1402 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1403 case SND_SOC_DAIFMT_CBS_CFS:
1404 /* Slave mode PLL */
1405 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
1406 0x80);
1407 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
1408 0x00);
1409 break;
1410 case SND_SOC_DAIFMT_CBM_CFM:
1411 /* Set to master mode */
1412 reg14val |= M98088_DAI_MAS;
1413 break;
1414 case SND_SOC_DAIFMT_CBS_CFM:
1415 case SND_SOC_DAIFMT_CBM_CFS:
1416 default:
1417 dev_err(codec->dev, "Clock mode unsupported");
1418 return -EINVAL;
1419 }
1420
1421 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1422 case SND_SOC_DAIFMT_I2S:
1423 reg14val |= M98088_DAI_DLY;
1424 break;
1425 case SND_SOC_DAIFMT_LEFT_J:
1426 break;
1427 default:
1428 return -EINVAL;
1429 }
1430
1431 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1432 case SND_SOC_DAIFMT_NB_NF:
1433 break;
1434 case SND_SOC_DAIFMT_NB_IF:
1435 reg14val |= M98088_DAI_WCI;
1436 break;
1437 case SND_SOC_DAIFMT_IB_NF:
1438 reg14val |= M98088_DAI_BCI;
1439 break;
1440 case SND_SOC_DAIFMT_IB_IF:
1441 reg14val |= M98088_DAI_BCI|M98088_DAI_WCI;
1442 break;
1443 default:
1444 return -EINVAL;
1445 }
1446
1447 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1448 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1449 M98088_DAI_WCI, reg14val);
1450
1451 reg15val = M98088_DAI_BSEL64;
1452 if (max98088->digmic)
1453 reg15val |= M98088_DAI_OSR64;
1454 snd_soc_write(codec, M98088_REG_15_DAI1_CLOCK, reg15val);
1455 }
1456
1457 return 0;
1458}
1459
1460static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1461 unsigned int fmt)
1462{
1463 struct snd_soc_codec *codec = codec_dai->codec;
1464 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1465 struct max98088_cdata *cdata;
1466 u8 reg1Cval = 0;
1467
1468 cdata = &max98088->dai[1];
1469
1470 if (fmt != cdata->fmt) {
1471 cdata->fmt = fmt;
1472
1473 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1474 case SND_SOC_DAIFMT_CBS_CFS:
1475 /* Slave mode PLL */
1476 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
1477 0x80);
1478 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
1479 0x00);
1480 break;
1481 case SND_SOC_DAIFMT_CBM_CFM:
1482 /* Set to master mode */
1483 reg1Cval |= M98088_DAI_MAS;
1484 break;
1485 case SND_SOC_DAIFMT_CBS_CFM:
1486 case SND_SOC_DAIFMT_CBM_CFS:
1487 default:
1488 dev_err(codec->dev, "Clock mode unsupported");
1489 return -EINVAL;
1490 }
1491
1492 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1493 case SND_SOC_DAIFMT_I2S:
1494 reg1Cval |= M98088_DAI_DLY;
1495 break;
1496 case SND_SOC_DAIFMT_LEFT_J:
1497 break;
1498 default:
1499 return -EINVAL;
1500 }
1501
1502 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1503 case SND_SOC_DAIFMT_NB_NF:
1504 break;
1505 case SND_SOC_DAIFMT_NB_IF:
1506 reg1Cval |= M98088_DAI_WCI;
1507 break;
1508 case SND_SOC_DAIFMT_IB_NF:
1509 reg1Cval |= M98088_DAI_BCI;
1510 break;
1511 case SND_SOC_DAIFMT_IB_IF:
1512 reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI;
1513 break;
1514 default:
1515 return -EINVAL;
1516 }
1517
1518 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1519 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1520 M98088_DAI_WCI, reg1Cval);
1521
1522 snd_soc_write(codec, M98088_REG_1D_DAI2_CLOCK,
1523 M98088_DAI_BSEL64);
1524 }
1525
1526 return 0;
1527}
1528
Jin Park25709f62011-05-12 14:58:38 +0900[diff] [blame]1529static int max98088_dai1_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1530{
1531 struct snd_soc_codec *codec = codec_dai->codec;
1532 int reg;
1533
1534 if (mute)
1535 reg = M98088_DAI_MUTE;
1536 else
1537 reg = 0;
1538
1539 snd_soc_update_bits(codec, M98088_REG_2F_LVL_DAI1_PLAY,
1540 M98088_DAI_MUTE_MASK, reg);
1541 return 0;
1542}
1543
1544static int max98088_dai2_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1545{
1546 struct snd_soc_codec *codec = codec_dai->codec;
1547 int reg;
1548
1549 if (mute)
1550 reg = M98088_DAI_MUTE;
1551 else
1552 reg = 0;
1553
1554 snd_soc_update_bits(codec, M98088_REG_31_LVL_DAI2_PLAY,
1555 M98088_DAI_MUTE_MASK, reg);
1556 return 0;
1557}
1558
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1559static int max98088_set_bias_level(struct snd_soc_codec *codec,
1560 enum snd_soc_bias_level level)
1561{
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]1562 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1563
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]1564 switch (level) {
1565 case SND_SOC_BIAS_ON:
1566 break;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1567
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]1568 case SND_SOC_BIAS_PREPARE:
1569 break;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1570
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]1571 case SND_SOC_BIAS_STANDBY:
1572 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1573 regcache_sync(max98088->regmap);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1574
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]1575 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1576 M98088_MBEN, M98088_MBEN);
1577 break;
1578
1579 case SND_SOC_BIAS_OFF:
1580 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1581 M98088_MBEN, 0);
1582 regcache_mark_dirty(max98088->regmap);
1583 break;
1584 }
1585 codec->dapm.bias_level = level;
1586 return 0;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1587}
1588
1589#define MAX98088_RATES SNDRV_PCM_RATE_8000_96000
1590#define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1591
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100[diff] [blame]1592static const struct snd_soc_dai_ops max98088_dai1_ops = {
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1593 .set_sysclk = max98088_dai_set_sysclk,
1594 .set_fmt = max98088_dai1_set_fmt,
1595 .hw_params = max98088_dai1_hw_params,
Jin Park25709f62011-05-12 14:58:38 +0900[diff] [blame]1596 .digital_mute = max98088_dai1_digital_mute,
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1597};
1598
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100[diff] [blame]1599static const struct snd_soc_dai_ops max98088_dai2_ops = {
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1600 .set_sysclk = max98088_dai_set_sysclk,
1601 .set_fmt = max98088_dai2_set_fmt,
1602 .hw_params = max98088_dai2_hw_params,
Jin Park25709f62011-05-12 14:58:38 +0900[diff] [blame]1603 .digital_mute = max98088_dai2_digital_mute,
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1604};
1605
1606static struct snd_soc_dai_driver max98088_dai[] = {
1607{
1608 .name = "HiFi",
1609 .playback = {
1610 .stream_name = "HiFi Playback",
1611 .channels_min = 1,
1612 .channels_max = 2,
1613 .rates = MAX98088_RATES,
1614 .formats = MAX98088_FORMATS,
1615 },
1616 .capture = {
1617 .stream_name = "HiFi Capture",
1618 .channels_min = 1,
1619 .channels_max = 2,
1620 .rates = MAX98088_RATES,
1621 .formats = MAX98088_FORMATS,
1622 },
1623 .ops = &max98088_dai1_ops,
1624},
1625{
1626 .name = "Aux",
1627 .playback = {
1628 .stream_name = "Aux Playback",
1629 .channels_min = 1,
1630 .channels_max = 2,
1631 .rates = MAX98088_RATES,
1632 .formats = MAX98088_FORMATS,
1633 },
1634 .ops = &max98088_dai2_ops,
1635}
1636};
1637
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1638static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"};
1639
1640static int max98088_get_channel(struct snd_soc_codec *codec, const char *name)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1641{
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1642 int i;
1643
1644 for (i = 0; i < ARRAY_SIZE(eq_mode_name); i++)
1645 if (strcmp(name, eq_mode_name[i]) == 0)
1646 return i;
1647
1648 /* Shouldn't happen */
1649 dev_err(codec->dev, "Bad EQ channel name '%s'\n", name);
1650 return -EINVAL;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1651}
1652
1653static void max98088_setup_eq1(struct snd_soc_codec *codec)
1654{
1655 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1656 struct max98088_pdata *pdata = max98088->pdata;
1657 struct max98088_eq_cfg *coef_set;
1658 int best, best_val, save, i, sel, fs;
1659 struct max98088_cdata *cdata;
1660
1661 cdata = &max98088->dai[0];
1662
1663 if (!pdata || !max98088->eq_textcnt)
1664 return;
1665
1666 /* Find the selected configuration with nearest sample rate */
1667 fs = cdata->rate;
1668 sel = cdata->eq_sel;
1669
1670 best = 0;
1671 best_val = INT_MAX;
1672 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1673 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1674 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1675 best = i;
1676 best_val = abs(pdata->eq_cfg[i].rate - fs);
1677 }
1678 }
1679
1680 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1681 pdata->eq_cfg[best].name,
1682 pdata->eq_cfg[best].rate, fs);
1683
1684 /* Disable EQ while configuring, and save current on/off state */
1685 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
1686 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
1687
1688 coef_set = &pdata->eq_cfg[sel];
1689
1690 m98088_eq_band(codec, 0, 0, coef_set->band1);
1691 m98088_eq_band(codec, 0, 1, coef_set->band2);
1692 m98088_eq_band(codec, 0, 2, coef_set->band3);
1693 m98088_eq_band(codec, 0, 3, coef_set->band4);
1694 m98088_eq_band(codec, 0, 4, coef_set->band5);
1695
1696 /* Restore the original on/off state */
1697 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save);
1698}
1699
1700static void max98088_setup_eq2(struct snd_soc_codec *codec)
1701{
1702 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1703 struct max98088_pdata *pdata = max98088->pdata;
1704 struct max98088_eq_cfg *coef_set;
1705 int best, best_val, save, i, sel, fs;
1706 struct max98088_cdata *cdata;
1707
1708 cdata = &max98088->dai[1];
1709
1710 if (!pdata || !max98088->eq_textcnt)
1711 return;
1712
1713 /* Find the selected configuration with nearest sample rate */
1714 fs = cdata->rate;
1715
1716 sel = cdata->eq_sel;
1717 best = 0;
1718 best_val = INT_MAX;
1719 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1720 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1721 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1722 best = i;
1723 best_val = abs(pdata->eq_cfg[i].rate - fs);
1724 }
1725 }
1726
1727 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1728 pdata->eq_cfg[best].name,
1729 pdata->eq_cfg[best].rate, fs);
1730
1731 /* Disable EQ while configuring, and save current on/off state */
1732 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
1733 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
1734
1735 coef_set = &pdata->eq_cfg[sel];
1736
1737 m98088_eq_band(codec, 1, 0, coef_set->band1);
1738 m98088_eq_band(codec, 1, 1, coef_set->band2);
1739 m98088_eq_band(codec, 1, 2, coef_set->band3);
1740 m98088_eq_band(codec, 1, 3, coef_set->band4);
1741 m98088_eq_band(codec, 1, 4, coef_set->band5);
1742
1743 /* Restore the original on/off state */
1744 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN,
1745 save);
1746}
1747
1748static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
1749 struct snd_ctl_elem_value *ucontrol)
1750{
1751 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1752 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1753 struct max98088_pdata *pdata = max98088->pdata;
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1754 int channel = max98088_get_channel(codec, kcontrol->id.name);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1755 struct max98088_cdata *cdata;
1756 int sel = ucontrol->value.integer.value[0];
1757
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1758 if (channel < 0)
1759 return channel;
1760
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1761 cdata = &max98088->dai[channel];
1762
1763 if (sel >= pdata->eq_cfgcnt)
1764 return -EINVAL;
1765
1766 cdata->eq_sel = sel;
1767
1768 switch (channel) {
1769 case 0:
1770 max98088_setup_eq1(codec);
1771 break;
1772 case 1:
1773 max98088_setup_eq2(codec);
1774 break;
1775 }
1776
1777 return 0;
1778}
1779
1780static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol,
1781 struct snd_ctl_elem_value *ucontrol)
1782{
1783 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1784 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1785 int channel = max98088_get_channel(codec, kcontrol->id.name);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1786 struct max98088_cdata *cdata;
1787
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1788 if (channel < 0)
1789 return channel;
1790
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1791 cdata = &max98088->dai[channel];
1792 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1793 return 0;
1794}
1795
1796static void max98088_handle_eq_pdata(struct snd_soc_codec *codec)
1797{
1798 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1799 struct max98088_pdata *pdata = max98088->pdata;
1800 struct max98088_eq_cfg *cfg;
1801 unsigned int cfgcnt;
1802 int i, j;
1803 const char **t;
1804 int ret;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1805 struct snd_kcontrol_new controls[] = {
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1806 SOC_ENUM_EXT((char *)eq_mode_name[0],
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1807 max98088->eq_enum,
1808 max98088_get_eq_enum,
1809 max98088_put_eq_enum),
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1810 SOC_ENUM_EXT((char *)eq_mode_name[1],
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1811 max98088->eq_enum,
1812 max98088_get_eq_enum,
1813 max98088_put_eq_enum),
1814 };
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1815 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name));
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1816
1817 cfg = pdata->eq_cfg;
1818 cfgcnt = pdata->eq_cfgcnt;
1819
1820 /* Setup an array of texts for the equalizer enum.
1821 * This is based on Mark Brown's equalizer driver code.
1822 */
1823 max98088->eq_textcnt = 0;
1824 max98088->eq_texts = NULL;
1825 for (i = 0; i < cfgcnt; i++) {
1826 for (j = 0; j < max98088->eq_textcnt; j++) {
1827 if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0)
1828 break;
1829 }
1830
1831 if (j != max98088->eq_textcnt)
1832 continue;
1833
1834 /* Expand the array */
1835 t = krealloc(max98088->eq_texts,
1836 sizeof(char *) * (max98088->eq_textcnt + 1),
1837 GFP_KERNEL);
1838 if (t == NULL)
1839 continue;
1840
1841 /* Store the new entry */
1842 t[max98088->eq_textcnt] = cfg[i].name;
1843 max98088->eq_textcnt++;
1844 max98088->eq_texts = t;
1845 }
1846
1847 /* Now point the soc_enum to .texts array items */
1848 max98088->eq_enum.texts = max98088->eq_texts;
1849 max98088->eq_enum.max = max98088->eq_textcnt;
1850
Liam Girdwood022658b2012-02-03 17:43:09 +0000[diff] [blame]1851 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1852 if (ret != 0)
1853 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
1854}
1855
1856static void max98088_handle_pdata(struct snd_soc_codec *codec)
1857{
1858 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1859 struct max98088_pdata *pdata = max98088->pdata;
1860 u8 regval = 0;
1861
1862 if (!pdata) {
1863 dev_dbg(codec->dev, "No platform data\n");
1864 return;
1865 }
1866
1867 /* Configure mic for analog/digital mic mode */
1868 if (pdata->digmic_left_mode)
1869 regval |= M98088_DIGMIC_L;
1870
1871 if (pdata->digmic_right_mode)
1872 regval |= M98088_DIGMIC_R;
1873
1874 max98088->digmic = (regval ? 1 : 0);
1875
1876 snd_soc_write(codec, M98088_REG_48_CFG_MIC, regval);
1877
1878 /* Configure receiver output */
1879 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0);
1880 snd_soc_update_bits(codec, M98088_REG_2A_MIC_REC_CNTL,
1881 M98088_REC_LINEMODE_MASK, regval);
1882
1883 /* Configure equalizers */
1884 if (pdata->eq_cfgcnt)
1885 max98088_handle_eq_pdata(codec);
1886}
1887
1888#ifdef CONFIG_PM
Lars-Peter Clausen84b315e2011-12-02 10:18:28 +0100[diff] [blame]1889static int max98088_suspend(struct snd_soc_codec *codec)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1890{
1891 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF);
1892
1893 return 0;
1894}
1895
1896static int max98088_resume(struct snd_soc_codec *codec)
1897{
1898 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1899
1900 return 0;
1901}
1902#else
1903#define max98088_suspend NULL
1904#define max98088_resume NULL
1905#endif
1906
1907static int max98088_probe(struct snd_soc_codec *codec)
1908{
1909 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1910 struct max98088_cdata *cdata;
1911 int ret = 0;
1912
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]1913 regcache_mark_dirty(max98088->regmap);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1914
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]1915 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1916 if (ret != 0) {
1917 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1918 return ret;
1919 }
1920
Uwe Kleine-Königb5950762010-11-01 15:38:34 -0400[diff] [blame]1921 /* initialize private data */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1922
1923 max98088->sysclk = (unsigned)-1;
1924 max98088->eq_textcnt = 0;
1925
1926 cdata = &max98088->dai[0];
1927 cdata->rate = (unsigned)-1;
1928 cdata->fmt = (unsigned)-1;
1929 cdata->eq_sel = 0;
1930
1931 cdata = &max98088->dai[1];
1932 cdata->rate = (unsigned)-1;
1933 cdata->fmt = (unsigned)-1;
1934 cdata->eq_sel = 0;
1935
1936 max98088->ina_state = 0;
1937 max98088->inb_state = 0;
1938 max98088->ex_mode = 0;
1939 max98088->digmic = 0;
1940 max98088->mic1pre = 0;
1941 max98088->mic2pre = 0;
1942
1943 ret = snd_soc_read(codec, M98088_REG_FF_REV_ID);
1944 if (ret < 0) {
1945 dev_err(codec->dev, "Failed to read device revision: %d\n",
1946 ret);
1947 goto err_access;
1948 }
Dylan Reid98682062013-04-16 20:02:34 -0700[diff] [blame]1949 dev_info(codec->dev, "revision %c\n", ret - 0x40 + 'A');
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1950
1951 snd_soc_write(codec, M98088_REG_51_PWR_SYS, M98088_PWRSV);
1952
1953 /* initialize registers cache to hardware default */
1954 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1955
1956 snd_soc_write(codec, M98088_REG_0F_IRQ_ENABLE, 0x00);
1957
1958 snd_soc_write(codec, M98088_REG_22_MIX_DAC,
1959 M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL|
1960 M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR);
1961
1962 snd_soc_write(codec, M98088_REG_4E_BIAS_CNTL, 0xF0);
1963 snd_soc_write(codec, M98088_REG_50_DAC_BIAS2, 0x0F);
1964
1965 snd_soc_write(codec, M98088_REG_16_DAI1_IOCFG,
1966 M98088_S1NORMAL|M98088_SDATA);
1967
1968 snd_soc_write(codec, M98088_REG_1E_DAI2_IOCFG,
1969 M98088_S2NORMAL|M98088_SDATA);
1970
1971 max98088_handle_pdata(codec);
1972
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1973err_access:
1974 return ret;
1975}
1976
1977static int max98088_remove(struct snd_soc_codec *codec)
1978{
Axel Linbc5954f2010-11-23 15:56:21 +0800[diff] [blame]1979 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1980
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1981 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF);
Axel Linbc5954f2010-11-23 15:56:21 +0800[diff] [blame]1982 kfree(max98088->eq_texts);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1983
1984 return 0;
1985}
1986
1987static struct snd_soc_codec_driver soc_codec_dev_max98088 = {
Mark Brown356d86e2013-09-23 17:22:17 +0100[diff] [blame]1988 .probe = max98088_probe,
1989 .remove = max98088_remove,
1990 .suspend = max98088_suspend,
1991 .resume = max98088_resume,
1992 .set_bias_level = max98088_set_bias_level,
Mark Brownad65adf2013-09-23 17:54:02 +0100[diff] [blame]1993 .controls = max98088_snd_controls,
1994 .num_controls = ARRAY_SIZE(max98088_snd_controls),
Lu Guanqundc6fc492011-03-30 21:53:10 +0800[diff] [blame]1995 .dapm_widgets = max98088_dapm_widgets,
1996 .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets),
1997 .dapm_routes = max98088_audio_map,
1998 .num_dapm_routes = ARRAY_SIZE(max98088_audio_map),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1999};
2000
2001static int max98088_i2c_probe(struct i2c_client *i2c,
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]2002 const struct i2c_device_id *id)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2003{
2004 struct max98088_priv *max98088;
2005 int ret;
2006
Axel Lin49ba7672011-12-29 12:01:07 +0800[diff] [blame]2007 max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv),
2008 GFP_KERNEL);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2009 if (max98088 == NULL)
2010 return -ENOMEM;
2011
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame^]2012 max98088->regmap = devm_regmap_init_i2c(i2c, &max98088_regmap);
2013 if (IS_ERR(max98088->regmap))
2014 return PTR_ERR(max98088->regmap);
2015
Jesse Marroquinfb762a52010-11-17 14:26:40 -0600[diff] [blame]2016 max98088->devtype = id->driver_data;
2017
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2018 i2c_set_clientdata(i2c, max98088);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2019 max98088->pdata = i2c->dev.platform_data;
2020
2021 ret = snd_soc_register_codec(&i2c->dev,
2022 &soc_codec_dev_max98088, &max98088_dai[0], 2);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2023 return ret;
2024}
2025
Bill Pemberton7a79e942012-12-07 09:26:37 -0500[diff] [blame]2026static int max98088_i2c_remove(struct i2c_client *client)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2027{
2028 snd_soc_unregister_codec(&client->dev);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2029 return 0;
2030}
2031
2032static const struct i2c_device_id max98088_i2c_id[] = {
Jesse Marroquinfb762a52010-11-17 14:26:40 -0600[diff] [blame]2033 { "max98088", MAX98088 },
2034 { "max98089", MAX98089 },
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2035 { }
2036};
2037MODULE_DEVICE_TABLE(i2c, max98088_i2c_id);
2038
2039static struct i2c_driver max98088_i2c_driver = {
Bill Pemberton69395652012-11-19 13:19:39 -0500[diff] [blame]2040 .driver = {
2041 .name = "max98088",
2042 .owner = THIS_MODULE,
2043 },
2044 .probe = max98088_i2c_probe,
2045 .remove = max98088_i2c_remove,
2046 .id_table = max98088_i2c_id,
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2047};
2048
Sachin Kamat2342a072012-08-06 17:25:51 +0530[diff] [blame]2049module_i2c_driver(max98088_i2c_driver);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2050
2051MODULE_DESCRIPTION("ALSA SoC MAX98088 driver");
2052MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin");
2053MODULE_LICENSE("GPL");