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gerrit-public.fairphone.software / kernel / msm-5.4 / 4294f8baaf174c9aa57886e7ed27caf4b02578f6 / . / arch / arm / include / asm / hardware / gic.h
blob: 43a05d90e43bfc06f3c3fce066532873541c3445 [file] [log] [blame]
Russell Kingf27ecac2005-08-18 21:31:00 +0100[diff] [blame]1/*
Russell King4baa9922008-08-02 10:55:55 +0100[diff] [blame]2 * arch/arm/include/asm/hardware/gic.h
Russell Kingf27ecac2005-08-18 21:31:00 +0100[diff] [blame]3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_ARM_HARDWARE_GIC_H
11#define __ASM_ARM_HARDWARE_GIC_H
12
13#include <linux/compiler.h>
14
15#define GIC_CPU_CTRL 0x00
16#define GIC_CPU_PRIMASK 0x04
17#define GIC_CPU_BINPOINT 0x08
18#define GIC_CPU_INTACK 0x0c
19#define GIC_CPU_EOI 0x10
20#define GIC_CPU_RUNNINGPRI 0x14
21#define GIC_CPU_HIGHPRI 0x18
22
23#define GIC_DIST_CTRL 0x000
24#define GIC_DIST_CTR 0x004
25#define GIC_DIST_ENABLE_SET 0x100
26#define GIC_DIST_ENABLE_CLEAR 0x180
27#define GIC_DIST_PENDING_SET 0x200
28#define GIC_DIST_PENDING_CLEAR 0x280
29#define GIC_DIST_ACTIVE_BIT 0x300
30#define GIC_DIST_PRI 0x400
31#define GIC_DIST_TARGET 0x800
32#define GIC_DIST_CONFIG 0xc00
33#define GIC_DIST_SOFTINT 0xf00
34
35#ifndef __ASSEMBLY__
Rob Herring4294f8b2011-09-28 21:25:31 -0500[diff] [blame^]36#include <linux/irqdomain.h>
37struct device_node;
38
Russell Kingff2e27a2010-12-04 16:13:29 +0000[diff] [blame]39extern void __iomem *gic_cpu_base_addr;
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +0100[diff] [blame]40extern struct irq_chip gic_arch_extn;
Russell Kingff2e27a2010-12-04 16:13:29 +0000[diff] [blame]41
Russell Kingb580b892010-12-04 15:55:14 +0000[diff] [blame]42void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
Russell King38489532010-12-04 16:01:03 +0000[diff] [blame]43void gic_secondary_init(unsigned int);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100[diff] [blame]44void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
Russell King82668102009-05-17 16:20:18 +0100[diff] [blame]45void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
Changhwan Youne807acb2011-07-16 10:49:47 +0900[diff] [blame]46
47struct gic_chip_data {
Changhwan Youne807acb2011-07-16 10:49:47 +0900[diff] [blame]48 void __iomem *dist_base;
49 void __iomem *cpu_base;
Colin Cross254056f2011-02-10 12:54:10 -0800[diff] [blame]50#ifdef CONFIG_CPU_PM
51 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
52 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
53 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
54 u32 __percpu *saved_ppi_enable;
55 u32 __percpu *saved_ppi_conf;
56#endif
Rob Herring4294f8b2011-09-28 21:25:31 -0500[diff] [blame^]57#ifdef CONFIG_IRQ_DOMAIN
58 struct irq_domain domain;
59#endif
Colin Cross254056f2011-02-10 12:54:10 -0800[diff] [blame]60 unsigned int gic_irqs;
Changhwan Youne807acb2011-07-16 10:49:47 +0900[diff] [blame]61};
Russell Kingf27ecac2005-08-18 21:31:00 +0100[diff] [blame]62#endif
63
64#endif