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Jonas Jensen448e7ed2013-12-18 13:58:46 +01001/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC
2 *
3 * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com>
4 *
5 * Licensed under GPLv2 or later.
6 */
7
8/include/ "skeleton.dtsi"
9
10/ {
11 compatible = "moxa,moxart";
12 model = "MOXART";
13 interrupt-parent = <&intc>;
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "faraday,fa526";
22 reg = <0>;
23 };
24 };
25
26 clocks {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 ref12: ref12M {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <12000000>;
34 };
35 };
36
37 soc {
38 compatible = "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
41 reg = <0x90000000 0x10000000>;
42 ranges;
43
44 intc: interrupt-controller@98800000 {
45 compatible = "moxa,moxart-ic";
46 reg = <0x98800000 0x38>;
47 interrupt-controller;
48 #interrupt-cells = <2>;
49 interrupt-mask = <0x00080000>;
50 };
51
52 clk_pll: clk_pll@98100000 {
53 compatible = "moxa,moxart-pll-clock";
54 #clock-cells = <0>;
55 reg = <0x98100000 0x34>;
56 };
57
58 clk_apb: clk_apb@98100000 {
59 compatible = "moxa,moxart-apb-clock";
60 #clock-cells = <0>;
61 reg = <0x98100000 0x34>;
62 clocks = <&clk_pll>;
63 };
64
65 timer: timer@98400000 {
66 compatible = "moxa,moxart-timer";
67 reg = <0x98400000 0x42>;
68 interrupts = <19 1>;
69 clocks = <&clk_apb>;
70 };
71
72 gpio: gpio@98700000 {
73 gpio-controller;
74 #gpio-cells = <2>;
75 compatible = "moxa,moxart-gpio";
76 reg = <0x98700000 0xC>;
77 };
78
79 rtc: rtc {
80 compatible = "moxa,moxart-rtc";
81 gpio-rtc-sclk = <&gpio 5 0>;
82 gpio-rtc-data = <&gpio 6 0>;
83 gpio-rtc-reset = <&gpio 7 0>;
84 };
85
86 dma: dma@90500000 {
87 compatible = "moxa,moxart-dma";
88 reg = <0x90500080 0x40>;
89 interrupts = <24 0>;
90 #dma-cells = <1>;
91 };
92
93 watchdog: watchdog@98500000 {
94 compatible = "moxa,moxart-watchdog";
95 reg = <0x98500000 0x10>;
96 clocks = <&clk_apb>;
97 };
98
99 sdhci: sdhci@98e00000 {
100 compatible = "moxa,moxart-sdhci";
101 reg = <0x98e00000 0x5C>;
102 interrupts = <5 0>;
103 clocks = <&clk_apb>;
104 dmas = <&dma 5>,
105 <&dma 5>;
106 dma-names = "tx", "rx";
107 status = "disabled";
108 };
109
110 mdio0: mdio@90900090 {
111 compatible = "moxa,moxart-mdio";
112 reg = <0x90900090 0x8>;
113 #address-cells = <1>;
114 #size-cells = <0>;
115 status = "disabled";
116 };
117
118 mdio1: mdio@92000090 {
119 compatible = "moxa,moxart-mdio";
120 reg = <0x92000090 0x8>;
121 #address-cells = <1>;
122 #size-cells = <0>;
123 status = "disabled";
124 };
125
126 mac0: mac@90900000 {
127 compatible = "moxa,moxart-mac";
128 reg = <0x90900000 0x90>;
129 interrupts = <25 0>;
130 phy-handle = <&ethphy0>;
131 phy-mode = "mii";
132 status = "disabled";
133 };
134
135 mac1: mac@92000000 {
136 compatible = "moxa,moxart-mac";
137 reg = <0x92000000 0x90>;
138 interrupts = <27 0>;
139 phy-handle = <&ethphy1>;
140 phy-mode = "mii";
141 status = "disabled";
142 };
143
144 uart0: uart@98200000 {
145 compatible = "ns16550a";
146 reg = <0x98200000 0x20>;
147 interrupts = <31 8>;
148 reg-shift = <2>;
149 reg-io-width = <4>;
150 clock-frequency = <14745600>;
151 status = "disabled";
152 };
153 };
154};