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gerrit-public.fairphone.software / kernel / msm-5.4 / 48538b5863d8e8f8d567fc9a1d27a68623e0a0ff / . / arch / x86 / include / asm / inst.h
blob: 3e115273ed885110de583ce5b228ad6caf993eec [file] [log] [blame]
Huang Yingfd650a62009-11-09 13:52:26 -0500[diff] [blame]1/*
2 * Generate .byte code for some instructions not supported by old
3 * binutils.
4 */
5#ifndef X86_ASM_INST_H
6#define X86_ASM_INST_H
7
8#ifdef __ASSEMBLY__
9
Huang Ying32cbd7d2010-03-13 16:28:42 +0800[diff] [blame]10#define REG_NUM_INVALID 100
11
Jan Beulich2baad612013-05-29 13:43:54 +0100[diff] [blame]12#define REG_TYPE_R32 0
13#define REG_TYPE_R64 1
14#define REG_TYPE_XMM 2
Huang Ying32cbd7d2010-03-13 16:28:42 +0800[diff] [blame]15#define REG_TYPE_INVALID 100
16
Jan Beulich2baad612013-05-29 13:43:54 +0100[diff] [blame]17 .macro R32_NUM opd r32
18 \opd = REG_NUM_INVALID
19 .ifc \r32,%eax
20 \opd = 0
21 .endif
22 .ifc \r32,%ecx
23 \opd = 1
24 .endif
25 .ifc \r32,%edx
26 \opd = 2
27 .endif
28 .ifc \r32,%ebx
29 \opd = 3
30 .endif
31 .ifc \r32,%esp
32 \opd = 4
33 .endif
34 .ifc \r32,%ebp
35 \opd = 5
36 .endif
37 .ifc \r32,%esi
38 \opd = 6
39 .endif
40 .ifc \r32,%edi
41 \opd = 7
42 .endif
43#ifdef CONFIG_X86_64
44 .ifc \r32,%r8d
45 \opd = 8
46 .endif
47 .ifc \r32,%r9d
48 \opd = 9
49 .endif
50 .ifc \r32,%r10d
51 \opd = 10
52 .endif
53 .ifc \r32,%r11d
54 \opd = 11
55 .endif
56 .ifc \r32,%r12d
57 \opd = 12
58 .endif
59 .ifc \r32,%r13d
60 \opd = 13
61 .endif
62 .ifc \r32,%r14d
63 \opd = 14
64 .endif
65 .ifc \r32,%r15d
66 \opd = 15
67 .endif
68#endif
69 .endm
70
Huang Ying32cbd7d2010-03-13 16:28:42 +0800[diff] [blame]71 .macro R64_NUM opd r64
72 \opd = REG_NUM_INVALID
Jan Beulich2baad612013-05-29 13:43:54 +0100[diff] [blame]73#ifdef CONFIG_X86_64
Huang Ying32cbd7d2010-03-13 16:28:42 +0800[diff] [blame]74 .ifc \r64,%rax
75 \opd = 0
76 .endif
77 .ifc \r64,%rcx
78 \opd = 1
79 .endif
80 .ifc \r64,%rdx
81 \opd = 2
82 .endif
83 .ifc \r64,%rbx
84 \opd = 3
85 .endif
86 .ifc \r64,%rsp
87 \opd = 4
88 .endif
89 .ifc \r64,%rbp
90 \opd = 5
91 .endif
92 .ifc \r64,%rsi
93 \opd = 6
94 .endif
95 .ifc \r64,%rdi
96 \opd = 7
97 .endif
98 .ifc \r64,%r8
99 \opd = 8
100 .endif
101 .ifc \r64,%r9
102 \opd = 9
103 .endif
104 .ifc \r64,%r10
105 \opd = 10
106 .endif
107 .ifc \r64,%r11
108 \opd = 11
109 .endif
110 .ifc \r64,%r12
111 \opd = 12
112 .endif
113 .ifc \r64,%r13
114 \opd = 13
115 .endif
116 .ifc \r64,%r14
117 \opd = 14
118 .endif
119 .ifc \r64,%r15
120 \opd = 15
121 .endif
Jan Beulich2baad612013-05-29 13:43:54 +0100[diff] [blame]122#endif
Huang Ying32cbd7d2010-03-13 16:28:42 +0800[diff] [blame]123 .endm
124
Huang Yingfd650a62009-11-09 13:52:26 -0500[diff] [blame]125 .macro XMM_NUM opd xmm
Huang Ying32cbd7d2010-03-13 16:28:42 +0800[diff] [blame]126 \opd = REG_NUM_INVALID
Huang Yingfd650a62009-11-09 13:52:26 -0500[diff] [blame]127 .ifc \xmm,%xmm0
128 \opd = 0
129 .endif
130 .ifc \xmm,%xmm1
131 \opd = 1
132 .endif
133 .ifc \xmm,%xmm2
134 \opd = 2
135 .endif
136 .ifc \xmm,%xmm3
137 \opd = 3
138 .endif
139 .ifc \xmm,%xmm4
140 \opd = 4
141 .endif
142 .ifc \xmm,%xmm5
143 \opd = 5
144 .endif
145 .ifc \xmm,%xmm6
146 \opd = 6
147 .endif
148 .ifc \xmm,%xmm7
149 \opd = 7
150 .endif
151 .ifc \xmm,%xmm8
152 \opd = 8
153 .endif
154 .ifc \xmm,%xmm9
155 \opd = 9
156 .endif
157 .ifc \xmm,%xmm10
158 \opd = 10
159 .endif
160 .ifc \xmm,%xmm11
161 \opd = 11
162 .endif
163 .ifc \xmm,%xmm12
164 \opd = 12
165 .endif
166 .ifc \xmm,%xmm13
167 \opd = 13
168 .endif
169 .ifc \xmm,%xmm14
170 \opd = 14
171 .endif
172 .ifc \xmm,%xmm15
173 \opd = 15
174 .endif
175 .endm
176
Huang Ying32cbd7d2010-03-13 16:28:42 +0800[diff] [blame]177 .macro REG_TYPE type reg
Jan Beulich2baad612013-05-29 13:43:54 +0100[diff] [blame]178 R32_NUM reg_type_r32 \reg
Huang Ying32cbd7d2010-03-13 16:28:42 +0800[diff] [blame]179 R64_NUM reg_type_r64 \reg
180 XMM_NUM reg_type_xmm \reg
Huang Ying62e7bec2010-03-24 21:37:57 +0800[diff] [blame]181 .if reg_type_r64 <> REG_NUM_INVALID
Huang Ying32cbd7d2010-03-13 16:28:42 +0800[diff] [blame]182 \type = REG_TYPE_R64
Jan Beulich2baad612013-05-29 13:43:54 +0100[diff] [blame]183 .elseif reg_type_r32 <> REG_NUM_INVALID
184 \type = REG_TYPE_R32
Huang Ying62e7bec2010-03-24 21:37:57 +0800[diff] [blame]185 .elseif reg_type_xmm <> REG_NUM_INVALID
Huang Ying32cbd7d2010-03-13 16:28:42 +0800[diff] [blame]186 \type = REG_TYPE_XMM
187 .else
188 \type = REG_TYPE_INVALID
189 .endif
190 .endm
191
Huang Yingfd650a62009-11-09 13:52:26 -0500[diff] [blame]192 .macro PFX_OPD_SIZE
193 .byte 0x66
194 .endm
195
Huang Ying32cbd7d2010-03-13 16:28:42 +0800[diff] [blame]196 .macro PFX_REX opd1 opd2 W=0
197 .if ((\opd1 | \opd2) & 8) || \W
198 .byte 0x40 | ((\opd1 & 8) >> 3) | ((\opd2 & 8) >> 1) | (\W << 3)
Huang Yingfd650a62009-11-09 13:52:26 -0500[diff] [blame]199 .endif
200 .endm
201
202 .macro MODRM mod opd1 opd2
203 .byte \mod | (\opd1 & 7) | ((\opd2 & 7) << 3)
204 .endm
205
206 .macro PSHUFB_XMM xmm1 xmm2
207 XMM_NUM pshufb_opd1 \xmm1
208 XMM_NUM pshufb_opd2 \xmm2
209 PFX_OPD_SIZE
210 PFX_REX pshufb_opd1 pshufb_opd2
211 .byte 0x0f, 0x38, 0x00
212 MODRM 0xc0 pshufb_opd1 pshufb_opd2
213 .endm
214
215 .macro PCLMULQDQ imm8 xmm1 xmm2
216 XMM_NUM clmul_opd1 \xmm1
217 XMM_NUM clmul_opd2 \xmm2
218 PFX_OPD_SIZE
219 PFX_REX clmul_opd1 clmul_opd2
220 .byte 0x0f, 0x3a, 0x44
221 MODRM 0xc0 clmul_opd1 clmul_opd2
222 .byte \imm8
223 .endm
224
Jan Beulich2baad612013-05-29 13:43:54 +0100[diff] [blame]225 .macro PEXTRD imm8 xmm gpr
226 R32_NUM extrd_opd1 \gpr
227 XMM_NUM extrd_opd2 \xmm
228 PFX_OPD_SIZE
229 PFX_REX extrd_opd1 extrd_opd2
230 .byte 0x0f, 0x3a, 0x16
231 MODRM 0xc0 extrd_opd1 extrd_opd2
232 .byte \imm8
233 .endm
234
Huang Yingfd650a62009-11-09 13:52:26 -0500[diff] [blame]235 .macro AESKEYGENASSIST rcon xmm1 xmm2
236 XMM_NUM aeskeygen_opd1 \xmm1
237 XMM_NUM aeskeygen_opd2 \xmm2
238 PFX_OPD_SIZE
239 PFX_REX aeskeygen_opd1 aeskeygen_opd2
240 .byte 0x0f, 0x3a, 0xdf
241 MODRM 0xc0 aeskeygen_opd1 aeskeygen_opd2
242 .byte \rcon
243 .endm
244
245 .macro AESIMC xmm1 xmm2
246 XMM_NUM aesimc_opd1 \xmm1
247 XMM_NUM aesimc_opd2 \xmm2
248 PFX_OPD_SIZE
249 PFX_REX aesimc_opd1 aesimc_opd2
250 .byte 0x0f, 0x38, 0xdb
251 MODRM 0xc0 aesimc_opd1 aesimc_opd2
252 .endm
253
254 .macro AESENC xmm1 xmm2
255 XMM_NUM aesenc_opd1 \xmm1
256 XMM_NUM aesenc_opd2 \xmm2
257 PFX_OPD_SIZE
258 PFX_REX aesenc_opd1 aesenc_opd2
259 .byte 0x0f, 0x38, 0xdc
260 MODRM 0xc0 aesenc_opd1 aesenc_opd2
261 .endm
262
263 .macro AESENCLAST xmm1 xmm2
264 XMM_NUM aesenclast_opd1 \xmm1
265 XMM_NUM aesenclast_opd2 \xmm2
266 PFX_OPD_SIZE
267 PFX_REX aesenclast_opd1 aesenclast_opd2
268 .byte 0x0f, 0x38, 0xdd
269 MODRM 0xc0 aesenclast_opd1 aesenclast_opd2
270 .endm
271
272 .macro AESDEC xmm1 xmm2
273 XMM_NUM aesdec_opd1 \xmm1
274 XMM_NUM aesdec_opd2 \xmm2
275 PFX_OPD_SIZE
276 PFX_REX aesdec_opd1 aesdec_opd2
277 .byte 0x0f, 0x38, 0xde
278 MODRM 0xc0 aesdec_opd1 aesdec_opd2
279 .endm
280
281 .macro AESDECLAST xmm1 xmm2
282 XMM_NUM aesdeclast_opd1 \xmm1
283 XMM_NUM aesdeclast_opd2 \xmm2
284 PFX_OPD_SIZE
285 PFX_REX aesdeclast_opd1 aesdeclast_opd2
286 .byte 0x0f, 0x38, 0xdf
287 MODRM 0xc0 aesdeclast_opd1 aesdeclast_opd2
288 .endm
Huang Ying32cbd7d2010-03-13 16:28:42 +0800[diff] [blame]289
290 .macro MOVQ_R64_XMM opd1 opd2
291 REG_TYPE movq_r64_xmm_opd1_type \opd1
292 .if movq_r64_xmm_opd1_type == REG_TYPE_XMM
293 XMM_NUM movq_r64_xmm_opd1 \opd1
294 R64_NUM movq_r64_xmm_opd2 \opd2
295 .else
296 R64_NUM movq_r64_xmm_opd1 \opd1
297 XMM_NUM movq_r64_xmm_opd2 \opd2
298 .endif
299 PFX_OPD_SIZE
300 PFX_REX movq_r64_xmm_opd1 movq_r64_xmm_opd2 1
301 .if movq_r64_xmm_opd1_type == REG_TYPE_XMM
302 .byte 0x0f, 0x7e
303 .else
304 .byte 0x0f, 0x6e
305 .endif
306 MODRM 0xc0 movq_r64_xmm_opd1 movq_r64_xmm_opd2
307 .endm
Huang Yingfd650a62009-11-09 13:52:26 -0500[diff] [blame]308#endif
309
310#endif